Prosecution Insights
Last updated: October 25, 2026
Application No. 19/350,268

PEROVSKITE-BASED WHITE OR MULTI-WAVELENGTH LASER

Non-Final OA §102§103§112
Filed
Oct 06, 2025
Examiner
CHAN, CANDICE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
King Saud University
OA Round
2 (Non-Final)
72%
Grant Probability
Favorable
2-3
OA Rounds
2y 3m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
403 granted / 556 resolved
+4.5% vs TC avg
Strong +20% interview lift
Without
With
+19.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
15 currently pending
Career history
617
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.1%
+13.1% vs TC avg
§102
26.2%
-13.8% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 556 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office action is in response to the amendment filed 11 March 2026. Claims 1-13 and 20 are currently pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Regarding claim 1, Applicant argues “one of ordinary skill in the art would understand that there are only 11 different embodiments, not the 24 possible combinations as alleged by the Examiner” and that claim 1 “should be construed in light of the different embodiments of the drawings as discussed supra.” (Remarks, pp. 31-32.) The Examiner respectfully disagrees and reminds Applicant that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant has submitted new figures 2A-2B, 3A-3D, and 4A-4E, however it is noted that the following permutations of claim 1 are not illustrated: third emission layer not present, fourth spacer layer present, third spacer layer present; third emission layer not present, fourth spacer layer present, third spacer layer not present; third emission layer not present, fourth spacer not present, third spacer not present. The absence of figures or written description is not construed to disclaim or restrict claim scope. Rather, the subject matter of the claims must be described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor had possession of the claimed invention. Here, the scope of claim 1 as currently drafted includes permutations that are not described in the specification or in the drawings. Drawings The drawings were received on 11 March 2026. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features not present must be shown or the feature(s) canceled from the claim(s): the following permutations of claim 1: third emission layer not present, fourth spacer layer present, third spacer layer present; third emission layer not present, fourth spacer layer present, third spacer layer not present; third emission layer not present, fourth spacer not present, third spacer not present. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 6 and 7 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 6 recites the limitation "omitting the depositing of the first spacer layer on the substrate" in line 5. This limitation conflicts with the positive recitation of steps of depositing or forming the first spacer layer in claims 2 and 3. Claims 6 fails to further limit the subject matter of the claim upon which it depends. For the purposes of examination, claim 6 is interpreted consistent with the limitations of the claims from which it depends. Claim 7 recites the limitations “omitting the depositing of the first spacer layer on the substrate” in line 5 and “omitting the depositing of the fourth spacer layer on the third emission layer” in line 7. These limitations conflict with the positive recitation of steps of depositing the first spacer layer and fourth spacer layer in claims 2 and 3. Claim 7 fails to further limit the subject matter of the claim upon which it depends. For the purposes of examination, claim 7 is interpreted consistent with the limitations of the claims from which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0296618 A1 to Levermore (hereinafter “Levermore”). Regarding claim 1, Levermore (Fig. 20(a)) discloses a method for manufacturing an optoelectronic device using halide perovskite layers, the method comprising: providing a substrate 1010 (¶ 0226); optionally depositing a first spacer layer on the substrate (optional step); depositing a first emission layer 1030 (¶ 0234) on the first spacer layer, if present, or on the substrate 1010; depositing a second spacer layer 1045 (¶ 0234 - 1045 may be disposed between 1030 and 1060) on the first emission layer 1030; depositing a second emission layer 1060 (¶ 0234) on the second spacer layer 1045; optionally depositing a third spacer layer on the second emission layer (optional step); optionally depositing a third emission layer on the third spacer layer, if present (optional step); optionally depositing a fourth spacer layer on the third emission layer, if present (optional step); wherein the first emission layer, the second emission layer, and the third emission layer each comprise a halide perovskite layer (¶ 0234 - PeLED emissive layers; ¶¶ 0082-0083 - disclosing halide perovskite materials); and wherein the halide perovskite layer of each of the first emission layer, the second emission layer, and the third emission layer comprises a three-dimensional halide perovskite, a two-dimensional halide perovskite, or a combination thereof (¶ 0082). Applicant is respectfully reminded that language that suggests or makes a feature or step optional but does not require that feature or step does not limit the scope of a claim under the broadest reasonable claim interpretation. MPEP § 2143.03. Here, the steps of depositing the first spacer layer, third spacer layer, third emission layer, and fourth spacer layer are recited as optional (and are not required) in the claim as currently drafted. Regarding claim 20, Levermore discloses the method for manufacturing an optoelectronic device of claim 1, wherein the three-dimensional halide perovskite has a formula ABX3: wherein A is selected from the group consisting of methylammonium (CH3NH3+), formamidinium (CH(NH2)2+), cesium (Cs+), rubidium (Rb+), potassium (K+), and a combination thereof; wherein B is selected from the group consisting of lead (Pb2+), tin (Sn2+), germanium (Ge2+), bismuth (Bi3+), antimony (Sb3+), and a combination thereof; and wherein X is selected from the group consisting of iodide (I ), bromide (Br ), chloride (Cl-), fluoride (F-), and a combination thereof; and wherein the two-dimensional halide perovskite has formulas R2An_1B~X3n+1, and DAn_1B~X3n+1: wherein R is selected from the group consisting of butylammonium (BA), butylammonium (C4H9NH3+), phenethylamine (PEA), phenethylammonium (C6H5C2H4NH3+),octylammonium (OA), CsH17NH3+, hexylammonium (HA), C6H13NH3+, benzylammonium (BZA), aminobenzyl (C6H5CH2NH3+), cyclohexylammonium (C6H13N), C6H11NH3+, and a combination thereof; wherein D is selected from the group consisting of 1,4-butanediammonium (C4H14N2+2), NH3(CH2)4NH3, 1,3-propanediammonium (PDA), NH3(CH2)3NH3, ethylenediammonium (C2HsN2), NH3(CH2)2NH3, 1,6-hexanediamine (HDA), NH3(CH2)6NH3, and a combination thereof; wherein A is selected from the group consisting of methylammonium (CH3NH3+), formamidinium (CH(NH2)2+), cesium (Cs+), rubidium (Rb+), potassium (K+), and a combination thereof; wherein B is selected from the group consisting of lead (Pb2+), tin (Sn2+), germanium(Ge2+), bismuth (Bi3+), antimony (Sb3+), and a combination thereof; and wherein X is selected from the group consisting of iodide (I-), bromide (Br ), chloride (Cl-), fluoride (F-), and a combination thereof (¶¶ 0082-83). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Levermore. Regarding claim 2, Levermore discloses the method for manufacturing an optoelectronic device of claim 1, wherein steps of depositing the first emission layer, second spacer layer, second emission layer are independently conducted via a process of spin coating, dip coating, doctor blading, slot-die coating, inkjet printing, spray coating, screen printing, chemical vapor deposition, sputtering, pulsed laser deposition, or thermal evaporation (¶ 0114). Levermore fails to expressly disclose: steps of depositing the first spacer layer, the third spacer layer, the third emission layer, and the fourth spacer layer. Levermore (Fig. 20(a)) does disclose depositing a first spacer layer 1015 (labelled in Fig. 18, ¶ 0106) on the substrate 1010, depositing a third emission layer 1065 (Fig. 20(a), ¶ 0234), and depositing a fourth spacer layer 1085 (labelled in Fig. 18, ¶ 0106) on the third emission layer 1065. Levermore fails to expressly disclose: depositing the third spacer layer on the second emission layer, however, does contemplate including more than one spacer layer separating emissive layers in the device (¶ 0105). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include forming a third spacer layer on the second emission layer, and thus the step of depositing the third spacer layer on the second emission layer, the third emission layer on the third spacer layer, utilizing the methods discussed in ¶ 0114, for the purpose of charge generation (¶ 0105). Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Levermore as applied to claims 1 and 2 above, and further in view of US 2021/0242357 A1 to Gamelin et al. (hereinafter “Gamelin”). Regarding claim 3, Levermore discloses the method for manufacturing an optoelectronic device of claim 2, wherein the process for each of the first spacer layer, the first emission layer, the second spacer layer, the second emission layer, the third spacer layer, the third emission layer, and the fourth spacer layer is the thermal evaporation (¶ 0114). Levermore fails to expressly disclose using a thermal evaporation vacuum chamber system. In the same field of endeavor, Gamelin discloses the use of a thermal evaporation vacuum chamber system to perform thermal evaporation steps (¶¶ 0310-0312). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the thermal evaporation steps using a thermal evaporation vacuum chamber system, for the purpose of using an art-recognized apparatus to perform thermal evaporation steps, as is customary and conventional in the art (as exemplified by Gamelin, see, e.g., ¶¶ 0310-0312). Regarding claim claim 4, Levermore and Gamelin disclose the method for manufacturing an optoelectronic device of claim 3, wherein the substrate is loaded onto a substrate holder of the thermal evaporation vacuum chamber system (Gamelin, ¶ 0310). Regarding claim 5, Levermore and Gamelin disclose the method for manufacturing an optoelectronic device of claim 4, wherein the steps of optionally depositing the first spacer layer on the substrate, optionally depositing the third spacer layer on the second emission layer, optionally depositing the third emission layer on the third spacer layer, and optionally depositing the fourth spacer layer on the third emission layer comprise depositing the first spacer layer 1015 (Levermore, labelled in Fig. 18, ¶ 0106) on the substrate 1010, depositing the third emission layer 1065 (Levermore, Fig. 20(a), ¶ 0234), and depositing the fourth spacer layer 1085 (Levermore, labelled in Fig. 18, ¶ 0106) on the third emission layer 1065. Levermore fails to expressly disclose: depositing the third spacer layer on the second emission layer, however, does contemplate including more than one spacer layer separating emissive layers in the device (¶ 0105). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a third spacer layer on the second emission layer, and thus the step of depositing the third spacer layer on the second emission layer, the third emission layer on the third spacer layer, for the purpose of charge generation (¶ 0105). Regarding claim 6, as best understood, Levermore and Gamelin disclose the method for manufacturing an optoelectronic device of claim 4, wherein the steps of optionally depositing the first spacer layer on the substrate, optionally depositing the third spacer layer on the second emission layer, optionally depositing the third emission layer on the third spacer layer, and optionally depositing the fourth spacer layer on the third emission layer comprise omitting the depositing of the first spacer layer on the substrate (since this step is not required in base claim 1, this limitation does not further limit the scope of this dependent claim), depositing the third emission layer 1065 (Levermore, Fig. 20(a), ¶ 0234), and depositing the fourth spacer layer 1085 (Levermore,, labelled in Fig. 18, ¶ 0106) on the third emission layer 1065. Levermore fails to expressly disclose: depositing the third spacer layer on the second emission layer, however, does contemplate including more than one spacer layer separating emissive layers in the device (¶ 0105). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a third spacer layer on the second emission layer, and thus the step of depositing the third spacer layer on the second emission layer, the third emission layer on the third spacer layer, for the purpose of charge generation (¶ 0105). Regarding claim 7, as best understood, Levermore and Gamelin disclose the method for manufacturing an optoelectronic device of claim 4, wherein the steps of optionally depositing the first spacer layer on the substrate, optionally depositing the third spacer layer on the second emission layer, optionally depositing the third emission layer on the third spacer layer, and optionally depositing the fourth spacer layer on the third emission layer comprise omitting the depositing of the first spacer layer on the substrate, depositing the third emission layer 1065 (Levermore, Fig. 20(a), ¶ 0234), and omitting the depositing of the fourth spacer layer on the third emission layer. Levermore fails to expressly disclose: depositing the third spacer layer on the second emission layer, however, does contemplate including more than one spacer layer separating emissive layers in the device (¶ 0105). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a third spacer layer on the second emission layer, and thus the step of depositing the third spacer layer on the second emission layer, the third emission layer on the third spacer layer, for the purpose of charge generation (¶ 0105). Claims 8, 9, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Levermore and Gamelin as applied to claim 5 above, and further in view of WO 8804475 A1 to Im (hereinafter “Im”) and US 2021/0408428 A1 to Duan et al. (hereinafter “Duan”). Regarding claim 8, Levermore and Gamelin disclose the method for manufacturing an optoelectronic device of claim 5, however fail to expressly disclose wherein each of the first spacer layer, the second spacer layer, the third spacer layer, and the fourth spacer layer comprise polymethyl methacrylate. In the same field of endeavor, Im discloses the use of polymethyl methacrylate in electrodes (p. 6, l. 25-30), and Duan discloses the use of polymethyl methacrylate in charge transport layers in perovskite light emitting devices (¶ 0034). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the first spacer layer and the fourth spacer layer using the material as disclosed by Im, and the second spacer layer and third spacer layer using the material as disclosed by Duan, for the purpose of utilizing materials known in the art to be suitable for use in electrodes (e.g., first spacer layer 1015, fourth spacer layer 1085 of Levermore) and charge layers of perovskite light emitting devices (e.g., second spacer layer 1045, third spacer layer of Levermore). Regarding claim 9, Levermore and Gamelin disclose the method for manufacturing an optoelectronic device of claim 5, however fail to expressly disclose wherein each of the second spacer layer, the third spacer layer, and the fourth spacer layer comprise a transparent polymer or a transparent metal having a refractive index that is less than, greater than, or equal to a refractive index of each of the first emission layer, the second emission layer, and the third emission layer, respectively. In the same field of endeavor, Im discloses the use of a polymer in electrodes (p. 6, l. 25-30), and Duan discloses the use of a transparent polymer in charge transport layers in perovskite light emitting devices (¶ 0034). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the fourth spacer layer using the material as disclosed by Im, and the second spacer layer and third spacer layer using the material as disclosed by Duan, for the purpose of utilizing materials known in the art to be suitable for use in electrodes (e.g., fourth spacer layer 1085 of Levermore) and charge layers of perovskite light emitting devices (e.g., second spacer layer 1045, third spacer layer of Levermore). It also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a transparent fourth spacer layer for the purpose of increased optoelectronic device output and efficiency. Regarding claim 11, Levermore, Gamelin, Im, and Duan disclose the method for manufacturing an optoelectronic device of claim 8, wherein the halide perovskite layer of each of the first emission layer, the second emission layer, and the third emission layer comprises CsPbIl.5Brl.5, CsPbBr3, and CsPbCl3, respectively (Levermore, ¶¶ 0082-83). Regarding claim 12, Levermore, Gamelin, Im, and Duan disclose the method for manufacturing an optoelectronic device of claim 9, wherein the halide perovskite layer of each of the first emission layer, the second emission layer, and the third emission layer comprises CsPbIl.5Brl.5, CsPbBr3, and CsPbCl3, respectively (¶¶ 0082-83). Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Levermore and Gamelin as applied to claim 5 above, and further in view of Duan. Regarding claim 10, Levermore and Gamelin disclose the method for manufacturing an optoelectronic device of claim 5, however fail to expressly disclose wherein each of the second spacer layer and the third spacer layer comprise a transparent polymer or a transparent metal having a refractive index that is greater than or equal to a refractive index of each of the first emission layer and the second emission layer, respectively. In the same field of endeavor, Duan discloses the use of a transparent polymer in charge transport layers in perovskite light emitting devices (¶ 0034). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the second spacer layer and third spacer layer using the material as disclosed by Duan, for the purpose of utilizing materials known in the art to be suitable for use in charge layers of perovskite light emitting devices (e.g., second spacer layer 1045, third spacer layer of Levermore). It also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a transparent fourth spacer layer for the purpose of increased optoelectronic device output and efficiency. Regarding claim 13, Levermore, Gamelin, and Duan disclose the method for manufacturing an optoelectronic device of claim 10, wherein the halide perovskite layer of each of the first emission layer, the second emission layer, and the third emission layer comprises CsPbI1.5Brl.5, CsPbBr3, and CsPbCl3 (Levermore, ¶¶ 0082-83). Levermorem, Gamelin, and Duan fail to expressly disclose the recited order of the emission layers and materials, respectively, however, it would have been obvious because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. The recited materials are within a finite number of identified, predictable solutions with a reasonable expectation of success, and are known to be suitable for use in perovskite light-emitting layers (Levermore, ¶¶ 0082-83); a person of ordinary skill in the art has good reason to pursue known options within his or her technical grasp. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CANDICE Y. CHAN Examiner Art Unit 2813 29 June 2026 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

Oct 06, 2025
Application Filed
Jan 29, 2026
Non-Final Rejection mailed — §102, §103, §112
Mar 11, 2026
Response Filed
Jul 07, 2026
Non-Final Rejection mailed — §102, §103, §112
Oct 14, 2026
Interview Requested
Oct 21, 2026
Examiner Interview Summary

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Prosecution Projections

2-3
Expected OA Rounds
72%
Grant Probability
92%
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