DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 7, 8, 10, 11, 17, 13, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 10, and 13-16 of U.S. Patent No. 11,580,927. Although the claims at issue are not identical, they are not patentably distinct from each other.
Application 19/351,756
Patent No. 11,580,927
1. A display system for displaying an image comprising:
a display panel having a plurality of pixels, each individual pixel of the plurality of pixels being driven between time-varying values of a pixel electrode voltage (VPEV) for the individual pixel and a common electrode voltage (VCOM) shared by the plurality of pixels; and
a digital drive device coupled to the display panel comprising: a bit plane memory for providing the VPEV to each individual pixel; and
a common electrode circuit for providing the VCOM, the common electrode circuit comprising:
at least one amplifier configured to generate a maximum pixel voltage (VPIX+) and a minimum pixel voltage (VPIX-);
the VPEV of each individual pixel switching between VPIX+ and VPIX- according to a voltage received by at least one of the plurality of pixels from the bit plane memory; and
the VCOM set to a midpoint between VPIX+ and VPIX-, offset by an offset value.
1. A display system for displaying an image comprising:
a display panel having a plurality of pixels, each of the plurality of pixels having a pixel electrode voltage (VPEV), and a common electrode voltage (VCOM); and
a digital drive device coupled to the display panel comprising: a bit plane memory for providing the VPEV to each of the plurality of pixels;
a common electrode circuit coupled to the display panel for providing the VCOM; and
at least one first amplifier coupled to the display panel configured to generate a maximum pixel voltage (VPIX+) and a minimum pixel voltage (VPIX-);
wherein the VPEV switches from VPIX+ to VPIX- according to a voltage received by at least one of the plurality of pixels from the bit plane memory,
wherein the common electrode circuit further comprises at least one second amplifier configured to generate a predetermined voltage VDAC_COM, wherein a value of VCOM switches between i) VPIX- minus VDAC_COM; and ii) VPIX+ plus VDAC_COM, and wherein the common electrode voltage VCOM maintains DC voltage balance across the display panel.
Application 19/351,756
Claim 7
Claim 8
Claim 10
Claim 11
Claim 17
Claim 18
Claim 20
Patent No. 11,580,927
Claim 2
Claim 3
Claim 15
Claim 10
Claim 14
Claim 13
Claim 16
Claims 9 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,580,927 in view of claim 13 of U.S. Patent No. 11,776,501. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of U.S. Patent No. 11,580,927 and include the common electrode circuit and the display panel are formed in a same integrated circuit as taught by 11,776,501, thereby using known techniques to yield predictable results.
Allowable Subject Matter
Claims 2-6, and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J KOHLMAN whose telephone number is (571)270-5503. The examiner can normally be reached 9-5:30.
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/CHRISTOPHER J KOHLMAN/Primary Examiner, Art Unit 2628
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