DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 11, 14, 15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pub. No. 2022/0383824 by Shin et al. (“Shin”).
As to claim 1, Shin discloses a display apparatus (Shin, display device, Figure 1), comprising:
a display panel (Shin, display panel 100, Figure 1) configured to display an image;
a data driver (Shin, data drivers 111 and 112, Figure 4A) configured to supply data voltages to the display panel (Shin, The data drivers 111 and 112 convert the pixel data from the timing controller 130 into a data voltage using a gamma compensation voltage, and output the data voltage to data lines 102. The data drivers 111 and 112 convert black grayscale data set separately from the pixel data of the input image into a black grayscale voltage using the gamma compensation voltage under the control of the timing controller 130, and may output the black grayscale voltage to the data lines 102. Accordingly, the pixel data voltage or the black grayscale voltage may be applied to each of the sub-pixels 101 through the data lines 102. Figure 4A, ¶ [0071]); The data drivers and gate drivers are within the display driver 200 (Shin, Figure 1).
a gate driver (Shin, gate drivers 121 and 122, Figure 4A) configured to supply scan signals to the display panel (Shin, The gate drivers 121 and 122 output a gate signal (or scan signal) synchronized with the pixel data to gate lines 104. The gate drivers 121 and 122 include shift registers for sequentially supplying the gate signal to gate lines G1 to Gn by shifting the pulse of the gate signal. Figure 4A, ¶ [0072]); The data drivers and gate drivers are within the display driver 200 (Shin, Figure 1).
a controller (Shin, system controller 300, Figure 1) configured to:
select a gaze focus area as a scan driving start point, based on a focus position of a gaze and foveated rendering information, wherein the gaze focus area is an area on which the gaze of a user is being focused (Shin, The system controller 300 analyzes image data from the camera 320 that captures user's left and right eyes with a preset eye tracking algorithm to estimate the focal region to which the user's left and right eyes are directed. The system controller 300 adjusts the resolution of the input image in the focal region and the non-focal region outside the focal region by using a foveated rendering algorithm. The system controller 300 converts the pixel data resolution of the input image according to the resolution of the focal region and the non-focal region by using a scaler. Figure 1, ¶ [0052]); and
control the gate driver to first supply a first subset of the scan signals to the gaze focus area as the scan driving start point (Shin, The foveated rendering algorithm may increase the resolution of pixel data corresponding to the focal region displayed on the display panel 100 by using the position information of the pupils, and may reduce the amount of transmitted data and the number of transitions by repeatedly constructing the same data on a predetermined pixel block basis in the non-focal region other than the focal region. The foveated rendering algorithm may reduce the amount of data transmitted to the display driver 200 by 80% or more by encoding pixel data to be written to the pixels of the focal region into a representative value. Figures 1 and 2, ¶ [0053])(Shin, The timing controller 130 may count the pixel data of the input image as a clock to determine the positions of pixels into which the pixel data is written. The timing controller 130 transmits a control signal for controlling the pixel luminance of the focal region and the non-focal region to the data drivers 111 and 112, and if the pixel data of the input image is to be written into pixels belonging to the non-focal region, activates the control signal for lowering the pixel luminance to control the pixel luminance of the non-focal region to be lower than that of the focal region. Figure 4A, ¶ [0073]).
As to claim 2, Shin discloses the display apparatus wherein the controller is further configured to:
divide a region of the display panel into the gaze focus area, a middle area, and a peripheral area, based on a distance from the focus position of the gaze (Shin, The focal region may be divided into N (N being a positive integer greater than or equal to 2) regions from the center to the edge. Figure 2, ¶ [0056]); and
control the data driver and the gate driver to drive the gaze focus area at a full resolution, the middle area at a medium resolution, and the peripheral area at a low resolution (Shin, In the case where the focal region is divided into three regions having different resolutions, if the pixel data resolution of a first region FR1 corresponding to the center of the focal region is 100%, the pixel data resolution of a second region FR2 outside the first region FR1 may be reduced to 25%, and the pixel data resolution of a third region FR3 outside the second region FR2 may be reduced to 11.1%. Figure 2, ¶ [0056]), and
wherein the full resolution is higher than the medium resolution, and the medium resolution is higher than the low resolution (Shin, In the case where the focal region is divided into three regions having different resolutions, if the pixel data resolution of a first region FR1 corresponding to the center of the focal region is 100%, the pixel data resolution of a second region FR2 outside the first region FR1 may be reduced to 25%, and the pixel data resolution of a third region FR3 outside the second region FR2 may be reduced to 11.1%. Figure 2, ¶ [0056]).
As to claim 5, Shin discloses the display apparatus wherein the controller is further configured to:
calculate a luminance gain value of each of the gaze focus area, the middle area, and the peripheral area (Shin, The display driver 200 writes high-resolution pixel data into the pixels of the focal region on the screen AA of the display panel 100 (steps S2 and S3). The resolution of the pixel data within the focal region may be gradually or stepwisely lowered from the center to the edge. On the other hand, the display driver 200 writes low-resolution pixel data into the pixels of the non-focal region outside the focal region, and lowers the luminance of the non-focal region than that of the focal region (steps S2 and S4). Figures 3 and 4a, ¶ [0059]); and
maintain luminance of the gaze focus area, and control luminance of the middle area to be lower than the luminance of the gaze focus area, and control luminance of the peripheral area to be lower than the luminance of the middle area, based on the calculated luminance gain values (Shin, The display driver 200 writes high-resolution pixel data into the pixels of the focal region on the screen AA of the display panel 100 (steps S2 and S3). The resolution of the pixel data within the focal region may be gradually or stepwisely lowered from the center to the edge. On the other hand, the display driver 200 writes low-resolution pixel data into the pixels of the non-focal region outside the focal region, and lowers the luminance of the non-focal region than that of the focal region (steps S2 and S4). Figures 3 and 4a, ¶ [0059]).
As to claim 6, Shin discloses the display apparatus wherein the controller is configured to adjust a gamma reference voltage of a gamma voltage generator, which is configured to supply the gamma reference voltage to the data driver, thereby controlling the luminance of each of the gaze focus area, the middle area, and the peripheral area (Shin, The data drivers 111 and 112 convert the pixel data from the timing controller 130 into a data voltage using a gamma compensation voltage, and output the data voltage to data lines 102. The data drivers 111 and 112 convert black grayscale data set separately from the pixel data of the input image into a black grayscale voltage using the gamma compensation voltage under the control of the timing controller 130, and may output the black grayscale voltage to the data lines 102. Accordingly, the pixel data voltage or the black grayscale voltage may be applied to each of the sub-pixels 101 through the data lines 102. Figure 4A, ¶ [0071]) (Shin, The display driver 200 writes high-resolution pixel data into the pixels of the focal region on the screen AA of the display panel 100 (steps S2 and S3). The resolution of the pixel data within the focal region may be gradually or stepwisely lowered from the center to the edge. On the other hand, the display driver 200 writes low-resolution pixel data into the pixels of the non-focal region outside the focal region, and lowers the luminance of the non-focal region than that of the focal region (steps S2 and S4). Figures 3 and 4a, ¶ [0059]).
As to claim 11, Shin discloses the display apparatus wherein the controller is configured to group image data of each of a middle area and a peripheral area other than the gaze focus area, to align the grouped image data, and to transmit the aligned image data to the data driver (Shin, The system controller 300 may transmit high-resolution data to the display driver 200 by increasing or without lowering the resolution of the pixel data to be written to the pixels of the focal region on the display panel 100. In this regard, the system controller 300 may gradually or stepwisely lower the resolution of the pixel data from the center of the focal region to the edge thereof. The system controller 300 significantly lowers the resolution of the non-focal region to reduce the data transmission amount and the number of transitions. ¶ [0054])(Shin, The display driver 200 writes high-resolution pixel data into the pixels of the focal region on the screen AA of the display panel 100 (steps S2 and S3). The resolution of the pixel data within the focal region may be gradually or stepwisely lowered from the center to the edge. On the other hand, the display driver 200 writes low-resolution pixel data into the pixels of the non-focal region outside the focal region, and lowers the luminance of the non-focal region than that of the focal region (steps S2 and S4). Figure 3, ¶ [0059]).
As to claim 14, Shin discloses a display apparatus (Shin, display device, Figure 1), comprising:
a display panel (Shin, display panel 100, Figure 1) in which a plurality of pixels (Shin, sub-pixels 101, Figure 4A) are disposed in an area where each of data lines (Shin, data lines 102, Figure 4A) and each of scan lines (Shin, gate lines 104, Figure 4A) intersect each other,
wherein the display apparatus is configured to:
select a gaze focus area as a scan driving start point on the display panel, based on a focus position of a gaze of a user (Shin, The system controller 300 analyzes image data from the camera 320 that captures user's left and right eyes with a preset eye tracking algorithm to estimate the focal region to which the user's left and right eyes are directed. The system controller 300 adjusts the resolution of the input image in the focal region and the non-focal region outside the focal region by using a foveated rendering algorithm. The system controller 300 converts the pixel data resolution of the input image according to the resolution of the focal region and the non-focal region by using a scaler. Figure 1, ¶ [0052]); and
first supply a first subset of scan signals to the gaze focus area via a first subset of the scan lines (Shin, The foveated rendering algorithm may increase the resolution of pixel data corresponding to the focal region displayed on the display panel 100 by using the position information of the pupils, and may reduce the amount of transmitted data and the number of transitions by repeatedly constructing the same data on a predetermined pixel block basis in the non-focal region other than the focal region. The foveated rendering algorithm may reduce the amount of data transmitted to the display driver 200 by 80% or more by encoding pixel data to be written to the pixels of the focal region into a representative value. Figures 1 and 2, ¶ [0053])(Shin, The timing controller 130 may count the pixel data of the input image as a clock to determine the positions of pixels into which the pixel data is written. The timing controller 130 transmits a control signal for controlling the pixel luminance of the focal region and the non-focal region to the data drivers 111 and 112, and if the pixel data of the input image is to be written into pixels belonging to the non-focal region, activates the control signal for lowering the pixel luminance to control the pixel luminance of the non-focal region to be lower than that of the focal region. Figure 4A, ¶ [0073]).
As to claim 15, Shin discloses the display apparatus wherein the display apparatus is further configured to:
divide a region of the display panel into the gaze focus area, a middle area, and a peripheral area based on the focus position of the gaze (Shin, The focal region may be divided into N (N being a positive integer greater than or equal to 2) regions from the center to the edge. Figure 2, ¶ [0056]); and
drive the gaze focus area at a full resolution, drive the middle area at a medium resolution, and drive the peripheral area at a low resolution (Shin, In the case where the focal region is divided into three regions having different resolutions, if the pixel data resolution of a first region FR1 corresponding to the center of the focal region is 100%, the pixel data resolution of a second region FR2 outside the first region FR1 may be reduced to 25%, and the pixel data resolution of a third region FR3 outside the second region FR2 may be reduced to 11.1%. Figure 2, ¶ [0056]), and
wherein the full resolution is higher than the medium resolution, and the medium resolution is higher than the low resolution (Shin, In the case where the focal region is divided into three regions having different resolutions, if the pixel data resolution of a first region FR1 corresponding to the center of the focal region is 100%, the pixel data resolution of a second region FR2 outside the first region FR1 may be reduced to 25%, and the pixel data resolution of a third region FR3 outside the second region FR2 may be reduced to 11.1%. Figure 2, ¶ [0056]).
As to claim 19, Shin discloses the display apparatus wherein the display apparatus is further configured to maintain luminance of the gaze focus area, and to control luminance of each of the middle area and the peripheral area to be lower than the luminance of the gaze focus area, based on image data (Shin, The display driver 200 writes high-resolution pixel data into the pixels of the focal region on the screen AA of the display panel 100 (steps S2 and S3). The resolution of the pixel data within the focal region may be gradually or stepwisely lowered from the center to the edge. On the other hand, the display driver 200 writes low-resolution pixel data into the pixels of the non-focal region outside the focal region, and lowers the luminance of the non-focal region than that of the focal region (steps S2 and S4). Figures 3 and 4a, ¶ [0059]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7-9, 12, 13, 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2022/0383824 by Shin et al. (“Shin”) in view of U.S. Pub. No. 2019/005884 by Yoo (“Yoo”).
As to claim 3, Shin does not expressly disclose the display apparatus wherein the controller is further configured to control the gate driver to output the first subset of the scan signals to the gaze focus area on a single scan line basis, to output a second subset of the scan signals to the middle area on a basis of at least two scan lines, and to output a third subset of the scan signals to the peripheral area on a basis of at least four scan lines.
Yoo teaches a display device and gate driving circuit wherein the controller is further configured to control the gate driver to output the first subset of the scan signals to the gaze focus area on a single scan line basis, to output a second subset of the scan signals to the middle area on a basis of at least two scan lines, and to output a third subset of the scan signals to the peripheral area on a basis of at least four scan lines (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. In the neighboring area and peripheral area, a plurality of pixel lines may be scanned simultaneously as a gate signal is applied simultaneously to a plurality of gate lines. In the peripheral area, every four pixel lines are scanned simultaneously. In the display panel driving method of FIG. 10C, the total scan count, i.e., the number of gate shifts, is 1,920 in the UHD (3840×2160) standard. In this case, the display panel 100 may be driven at a frame rate of 120 Hz. Figure 10C, ¶ [0095]).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Shin’s display driving to include Yoo’s display driving because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Shin’s display driving and Yoo’s display driving perform the same general and predictable function, the predictable function being providing display driving methods for a display device. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Shin’s display driving by replacing it with Yoo’s display driving. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Shin, as modified by Yoo, teaches the display driving for the focal area and the outside area.
As to claim 7, Shin discloses the display apparatus with a shift register in the gate driver (Shin, gate drivers 121 and 122 include shift registers, ¶ [0072]).
Shin does not expressly disclose wherein the gate driver includes:
first to (N+1)th logic circuits configured to operate in response to a carry signal or a clock signal;
first to (N+1)th enable transistors, wherein first electrodes of the first to N-th enable transistors are connected to output terminals of the first to N-th logic circuits, respectively, and second electrodes of the first to N-th enable transistors are connected to input terminals of the second to (N+1)th logic circuits, respectively;
the (N+1)th enable transistor has a second electrode;
first to N-th connection transistors connected to and disposed between the second electrodes of the first to (N+1)th enable transistors, respectively; and
first to (N+1)th output circuits connected to the second electrodes of the first to (N+1)th enable transistors, respectively, wherein each of the first to (N+1)th output circuits is configured to perform a pull-up or pull-down operation to output a respective one of first to (N+1)th scan signals, wherein the scan signals comprise the first to (N+1)th scan signals, and wherein N is a whole number.
Yoo teaches a display device and gate driving circuit
wherein the gate driver includes:
first to (N+1)th logic circuits configured to operate in response to a carry signal or a clock signal (Yoo, Referring to FIGS. 14 and 15, each of the stages of the shift register receives a start pulse or a carry signal CAR from the previous stage as the start pulse and produces output upon receipt of a shift clock CLK(N−1) or CLK(N). Accordingly, the output waveforms are shifted in synchronization with the timing of the shift clocks CLK(N−1) and CLK(N) that are input into the stages. The (N−1)th stage generates an (N−1)th output voltage OUT(N−1) of gate-on voltage upon receipt of the (N−1)th clock CLK(N−1). The Nth stage generates an Nth output voltage OUT(N) of gate-on voltage upon receipt of the Nth clock CLK(N). Figure 14, ¶ [0115]);
first to (N+1)th enable transistors, wherein first electrodes of the first to N-th enable transistors are connected to output terminals of the first to N-th logic circuits, respectively, and second electrodes of the first to N-th enable transistors are connected to input terminals of the second to (N+1)th logic circuits (Yoo, Nth switching circuits 140-146, Figures 14 and 16)(Yoo, Each of the switching circuit 140 and 141 charges the Q node in response to a start pulse input via the Vst terminal or a carry signal received from the previous stage, and discharges the Q node in response to a signal received via an RST terminal or VNEXT terminal. Figures 14 and 16, ¶ [0119]), respectively;
the (N+1)th enable transistor has a second electrode (Yoo, Nth switching circuits 140-146, Figures 14 and 16); The Nth switching circuits include a transistor with switching elements which inherently have a first and second electrode which are connected based on the control of the switch.
first to N-th connection transistors connected to and disposed between the second electrodes of the first to (N+1)th enable transistors (Yoo, The first multiplexer 151 feeds the Nth output voltage OUT(N) from the Nth switching circuit 141 to the first gate line of an (N+1)th pixel line, in response to a selection signal SEL. The second multiplexer 152 feeds the Nth output OUT(N) from the Nth switching circuit 141 to the Vst terminal of the (N+1)th switching circuit 142, in response to the selection signal SEL. As a result, the (N+1)th switching circuit 142 outputs an (N+1)th output voltage OUT(N+1) to the second gate line of the (N+1)th pixel line upon receipt of an (N+1)th clock. Figure 16, ¶ [0124]), respectively; and
first to (N+1)th output circuits connected to the second electrodes of the first to (N+1)th enable transistors, respectively, wherein each of the first to (N+1)th output circuits is configured to perform a pull-up or pull-down operation to output a respective one of first to (N+1)th scan signals, wherein the scan signals comprise the first to (N+1)th scan signals (Yoo, Each of the stages comprises a pull-up transistor Tu that pulls up the output voltage OUT(N−1) or OUT(N) by charging an output node in response to a Q node voltage, a pull-down transistor Td that pulls down the output voltage OUT(N−1) or OUT(N) by discharging the output node in response to a QB node voltage, and a switching circuit 140 or 141 for charging and discharging the Q node and the QB node. The output node of each stage is connected to a gate line on the display panel 100. Figure 14, ¶ [0116]), and wherein N is a whole number.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Shin’s gate drivers to include Yoo’s gate driver with shift register because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Shin’s gate drivers and Yoo’s gate driver with shift register perform the same general and predictable function, the predictable function being providing gate drivers to display devices. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Shin’s gate drivers by replacing it with Yoo’s gate driver with shift register. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Shin, as modified by Yoo, teaches the gate drivers including the stages to drive each of the scan lines.
As to claim 8, Shin, as modified by Yoo, teaches the display apparatus wherein the first to (N+1)th enable transistors are configured to operate in response to first to (N+1)th grouping enable signals, respectively (Yoo, The first multiplexer 151 feeds the Nth output voltage OUT(N) from the Nth switching circuit 141 to the first gate line of an (N+1)th pixel line, in response to a selection signal SEL. The second multiplexer 152 feeds the Nth output OUT(N) from the Nth switching circuit 141 to the Vst terminal of the (N+1)th switching circuit 142, in response to the selection signal SEL. As a result, the (N+1)th switching circuit 142 outputs an (N+1)th output voltage OUT(N+1) to the second gate line of the (N+1)th pixel line upon receipt of an (N+1)th clock. Figure 16, ¶ [0124]),
wherein the first to N-th connection transistors are configured to operate in response to first to N-th grouping signals, respectively, and wherein the first to (N+1)th enable transistors are configured to be selectively enabled based on the first to (N+1)th grouping enable signals, respectively (Yoo, The first multiplexer 151 feeds the Nth output voltage OUT(N) from the Nth switching circuit 141 to the first gate line of an (N+1)th pixel line, in response to a selection signal SEL. The second multiplexer 152 feeds the Nth output OUT(N) from the Nth switching circuit 141 to the Vst terminal of the (N+1)th switching circuit 142, in response to the selection signal SEL. As a result, the (N+1)th switching circuit 142 outputs an (N+1)th output voltage OUT(N+1) to the second gate line of the (N+1)th pixel line upon receipt of an (N+1)th clock. Figure 16, ¶ [0124]), and
the first to N-th connection transistors are configured to be selectively enabled based on the first to N-th grouping signals, thereby selectively grouping the first to (N+1)th scan signals (Yoo, The first multiplexer 151 feeds the Nth output voltage OUT(N) from the Nth switching circuit 141 to the first gate line of an (N+1)th pixel line, in response to a selection signal SEL. The second multiplexer 152 feeds the Nth output OUT(N) from the Nth switching circuit 141 to the Vst terminal of the (N+1)th switching circuit 142, in response to the selection signal SEL. As a result, the (N+1)th switching circuit 142 outputs an (N+1)th output voltage OUT(N+1) to the second gate line of the (N+1)th pixel line upon receipt of an (N+1)th clock. Figure 16, ¶ [0124]). Based on the selection signal SEL, the multiplexers MUX activate to connect to the scan lines. In addition, the motivation used is the same as in the rejection of claim 7.
As to claim 9, Shin, as modified by Yoo, teaches the display apparatus wherein the controller is further configured to include the first to (N+1)th grouping enable signals and the first to N-th grouping signals into gate control signals, and provide the gate control signals to the gate driver (Yoo, The timing controller 130 receives timing signals synchronized with the input image data from the system controller 50, and controls the operation timings of the data driver 110 and gate driver 120 based on these timing signals. The timing controller 130 controls the gate driver 120 so that the number of gate shifts in the focal area, neighboring area, and peripheral area is adjusted in proportion to the resolution of each area. ¶ [0061]). In addition, the motivation used is the same as in the rejection of claim 7.
As to claim 12, Shin does not expressly disclose the display apparatus wherein the controller is further configured to control the gate driver:
to first supply the first subset of the scan signals to the gaze focus area in a sequential manner; and
to subsequently supply a subset of the scan signals to each of a middle area and a peripheral area other than the gaze focus area in a sequential and grouped manner.
Yoo teaches a display device and gate driving circuit wherein the controller is further configured to control the gate driver:
to first supply the first subset of the scan signals to the gaze focus area in a sequential manner (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. Figure 10C, ¶ [0095]); and
to subsequently supply a subset of the scan signals to each of a middle area and a peripheral area other than the gaze focus area in a sequential and grouped manner (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. In the neighboring area and peripheral area, a plurality of pixel lines may be scanned simultaneously as a gate signal is applied simultaneously to a plurality of gate lines. In the peripheral area, every four pixel lines are scanned simultaneously. In the display panel driving method of FIG. 10C, the total scan count, i.e., the number of gate shifts, is 1,920 in the UHD (3840×2160) standard. In this case, the display panel 100 may be driven at a frame rate of 120 Hz. Figure 10C, ¶ [0095]).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Shin’s display driving to include Yoo’s display driving because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Shin’s display driving and Yoo’s display driving perform the same general and predictable function, the predictable function being providing display driving methods for a display device. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Shin’s display driving by replacing it with Yoo’s display driving. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Shin, as modified by Yoo, teaches the display driving for the focal area and the outside area.
As to claim 13, Shin does not expressly disclose the display apparatus wherein the controller is further configured to control the gate driver:
to first supply the first subset of the scan signals to the gaze focus area in a sequential manner and in a vertical alternating manner; and
to subsequently supply, in a sequential and grouped manner and in a vertical alternating manner, a second subset of the scan signals to a middle area and a third subset of the scan signals to a peripheral area, without supplying the second subset and the third subset to the gaze focus area
Yoo teaches a display device and gate driving circuit wherein the controller is further configured to control the gate driver:
to first supply the first subset of the scan signals to the gaze focus area in a sequential manner and in a vertical alternating manner (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. Figure 10C, ¶ [0095]); and
to subsequently supply, in a sequential and grouped manner and in a vertical alternating manner, a second subset of the scan signals to a middle area and a third subset of the scan signals to a peripheral area, without supplying the second subset and the third subset to the gaze focus area (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. In the neighboring area and peripheral area, a plurality of pixel lines may be scanned simultaneously as a gate signal is applied simultaneously to a plurality of gate lines. In the peripheral area, every four pixel lines are scanned simultaneously. In the display panel driving method of FIG. 10C, the total scan count, i.e., the number of gate shifts, is 1,920 in the UHD (3840×2160) standard. In this case, the display panel 100 may be driven at a frame rate of 120 Hz. Figure 10C, ¶ [0095]).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Shin’s display driving to include Yoo’s display driving because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Shin’s display driving and Yoo’s display driving perform the same general and predictable function, the predictable function being providing display driving methods for a display device. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Shin’s display driving by replacing it with Yoo’s display driving. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Shin, as modified by Yoo, teaches the display driving for the focal area and the outside area.
As to claim 16, Shin does not expressly teach the display apparatus wherein the display apparatus is further configured to:
sequentially drive the gaze focus area on a single scan line basis; and
drive each of the middle area and the peripheral area on a basis of at least two scan lines in a sequential and grouped manner.
Yoo teaches a display device and gate driving circuit wherein the display apparatus is further configured to:
sequentially drive the gaze focus area on a single scan line basis (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. Figure 10C, ¶ [0095]); and
drive each of the middle area and the peripheral area on a basis of at least two scan lines in a sequential and grouped manner (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. In the neighboring area and peripheral area, a plurality of pixel lines may be scanned simultaneously as a gate signal is applied simultaneously to a plurality of gate lines. In the peripheral area, every four pixel lines are scanned simultaneously. In the display panel driving method of FIG. 10C, the total scan count, i.e., the number of gate shifts, is 1,920 in the UHD (3840×2160) standard. In this case, the display panel 100 may be driven at a frame rate of 120 Hz. Figure 10C, ¶ [0095]).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Shin’s display driving to include Yoo’s display driving because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Shin’s display driving and Yoo’s display driving perform the same general and predictable function, the predictable function being providing display driving methods for a display device. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Shin’s display driving by replacing it with Yoo’s display driving. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Shin, as modified by Yoo, teaches the display driving for the focal area and the outside area.
As to claim 17, Shin does not expressly teach the display apparatus wherein the display apparatus is further configured to:
drive the gaze focus area on a single scan line basis sequentially and in a vertical alternating manner; and
drive each of the middle area and the peripheral area on a basis of at least two scan lines in a sequential and grouped manner and in a vertical alternating manner.
Yoo teaches a display device and gate driving circuit apparatus wherein the display apparatus is further configured to:
drive the gaze focus area on a single scan line basis sequentially and in a vertical alternating manner (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. Figure 10C, ¶ [0095]); and
drive each of the middle area and the peripheral area on a basis of at least two scan lines in a sequential and grouped manner and in a vertical alternating manner (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. In the neighboring area and peripheral area, a plurality of pixel lines may be scanned simultaneously as a gate signal is applied simultaneously to a plurality of gate lines. In the peripheral area, every four pixel lines are scanned simultaneously. In the display panel driving method of FIG. 10C, the total scan count, i.e., the number of gate shifts, is 1,920 in the UHD (3840×2160) standard. In this case, the display panel 100 may be driven at a frame rate of 120 Hz. Figure 10C, ¶ [0095]).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Shin’s display driving to include Yoo’s display driving because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Shin’s display driving and Yoo’s display driving perform the same general and predictable function, the predictable function being providing display driving methods for a display device. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Shin’s display driving by replacing it with Yoo’s display driving. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Shin, as modified by Yoo, teaches the display driving for the focal area and the outside area.
As to claim 20, Shin discloses the display apparatus with a shift register in the gate driver (Shin, gate drivers 121 and 122 include shift registers, ¶ [0072]).
Shin does not expressly disclose wherein the display apparatus further comprises a gate driver for sequentially driving the scan lines, for driving at least two scan lines in a grouped manner, or for sequentially driving the scan lines and driving at least two scan lines in a grouped manner,
wherein the gate driver includes:
first to (N+1)th logic circuits configured to operate in response to a carry signal or a clock signal;
first to (N+1)th enable transistors, wherein first electrodes of the first to N-th enable transistors are connected to output terminals of the first to N-th logic circuits, respectively, and second electrodes of the first to N-th enable transistors are connected to input terminals of the second to (N+1)th logic circuits, respectively;
the (N+1)th enable transistor has a second electrode;
first to N-th connection transistors connected to and disposed between the second electrodes of the first to (N+1)th enable transistors, respectively; and
first to (N+1)th output circuits connected to the second electrodes of the first to (N+1)th enable transistors, respectively, wherein each of the first to (N+1)th output circuits is configured to perform a pull-up or pull-down operation to output a respective one of first to (N+1)th scan signals,
wherein the scan signals comprise the first to (N+1)th scan signals, and wherein N is a whole number.
Yoo teaches a display device and gate driving circuit wherein the display apparatus further comprises a gate driver for sequentially driving the scan lines, for driving at least two scan lines in a grouped manner, or for sequentially driving the scan lines and driving at least two scan lines in a grouped manner (Yoo, FIG. 10C shows an example in which the focal area is converted to a size of 20% of the screen. The neighboring area, which is divided in two with the focal area in between, takes up 40%, and the peripheral area takes up 40%. The pixel lines in the focal area are sequentially scanned line by line as gate signals are shifted for each line. In the neighboring area and peripheral area, a plurality of pixel lines may be scanned simultaneously as a gate signal is applied simultaneously to a plurality of gate lines. In the peripheral area, every four pixel lines are scanned simultaneously. In the display panel driving method of FIG. 10C, the total scan count, i.e., the number of gate shifts, is 1,920 in the UHD (3840×2160) standard. In this case, the display panel 100 may be driven at a frame rate of 120 Hz. Figure 10C, ¶ [0095]),
wherein the gate driver includes:
first to (N+1)th logic circuits configured to operate in response to a carry signal or a clock signal (Yoo, Referring to FIGS. 14 and 15, each of the stages of the shift register receives a start pulse or a carry signal CAR from the previous stage as the start pulse and produces output upon receipt of a shift clock CLK(N−1) or CLK(N). Accordingly, the output waveforms are shifted in synchronization with the timing of the shift clocks CLK(N−1) and CLK(N) that are input into the stages. The (N−1)th stage generates an (N−1)th output voltage OUT(N−1) of gate-on voltage upon receipt of the (N−1)th clock CLK(N−1). The Nth stage generates an Nth output voltage OUT(N) of gate-on voltage upon receipt of the Nth clock CLK(N). Figure 14, ¶ [0115]);
first to (N+1)th enable transistors, wherein first electrodes of the first to N-th enable transistors are connected to output terminals of the first to N-th logic circuits, respectively, and second electrodes of the first to N-th enable transistors are connected to input terminals of the second to (N+1)th logic circuits, respectively (Yoo, Nth switching circuits 140-146, Figures 14 and 16)(Yoo, Each of the switching circuit 140 and 141 charges the Q node in response to a start pulse input via the Vst terminal or a carry signal received from the previous stage, and discharges the Q node in response to a signal received via an RST terminal or VNEXT terminal. Figures 14 and 16, ¶ [0119]);
the (N+1)th enable transistor has a second electrode (Yoo, Nth switching circuits 140-146, Figures 14 and 16); The Nth switching circuits include a transistor with switching elements which inherently have a first and second electrode which are connected based on the control of the switch.
first to N-th connection transistors connected to and disposed between the second electrodes of the first to (N+1)th enable transistors (Yoo, The first multiplexer 151 feeds the Nth output voltage OUT(N) from the Nth switching circuit 141 to the first gate line of an (N+1)th pixel line, in response to a selection signal SEL. The second multiplexer 152 feeds the Nth output OUT(N) from the Nth switching circuit 141 to the Vst terminal of the (N+1)th switching circuit 142, in response to the selection signal SEL. As a result, the (N+1)th switching circuit 142 outputs an (N+1)th output voltage OUT(N+1) to the second gate line of the (N+1)th pixel line upon receipt of an (N+1)th clock. Figure 16, ¶ [0124]), respectively; and
first to (N+1)th output circuits connected to the second electrodes of the first to (N+1)th enable transistors, respectively, wherein each of the first to (N+1)th output circuits is configured to perform a pull-up or pull-down operation to output a respective one of first to (N+1)th scan signals (Yoo, Each of the stages comprises a pull-up transistor Tu that pulls up the output voltage OUT(N−1) or OUT(N) by charging an output node in response to a Q node voltage, a pull-down transistor Td that pulls down the output voltage OUT(N−1) or OUT(N) by discharging the output node in response to a QB node voltage, and a switching circuit 140 or 141 for charging and discharging the Q node and the QB node. The output node of each stage is connected to a gate line on the display panel 100. Figure 14, ¶ [0116]),
wherein the scan signals comprise the first to (N+1)th scan signals (Yoo, Each of the stages comprises a pull-up transistor Tu that pulls up the output voltage OUT(N−1) or OUT(N) by charging an output node in response to a Q node voltage, a pull-down transistor Td that pulls down the output voltage OUT(N−1) or OUT(N) by discharging the output node in response to a QB node voltage, and a switching circuit 140 or 141 for charging and discharging the Q node and the QB node. The output node of each stage is connected to a gate line on the display panel 100. Figure 14, ¶ [0116]), and wherein N is a whole number.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Shin’s gate drivers to include Yoo’s gate driver with shift register because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Shin’s gate drivers and Yoo’s gate driver with shift register perform the same general and predictable function, the predictable function being providing gate drivers to display devices. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Shin’s gate drivers by replacing it with Yoo’s gate driver with shift register. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Shin, as modified by Yoo, teaches the gate drivers including the stages to drive each of the scan lines.
Allowable Subject Matter
Claims 4, 10, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 4, Shin, as modified by Yoo, does not expressly teach the display apparatus wherein the controller is further configured to control the data driver to apply a first subset of the data voltages to the gaze focus area on a single pixel basis, to apply a second subset of the data voltages to the middle area on a basis of at least two pixels, and to apply a third subset of the data voltages to the peripheral area on a basis of at least four pixels.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to claim 10, Shin, as modified by Yoo, does not expressly teach the display apparatus wherein a pulse width of the clock signal is determined in proportion to a number of scan signals grouped into one group.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to claim 18, Shin does not expressly teach the display apparatus wherein the display apparatus is further configured to:
apply a subset of data voltages to the gaze focus area on a single data line basis; and
apply a subset of the data voltages to each of the middle area and the peripheral area on a basis of at least two data lines in a grouped manner.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Pub. No. 2019/0287495 by Mathur et al. teaches a display system which produces images at higher resolution based on the user gaze point.
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623
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