DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are pending.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed: THIN FILM TRANSISTOR SUBSTRATE HAVING GATE ELECTRODE INTEGRALLY FORMING CLOSED LOOP SHAPE AND DISPLAY APPARATUS COMPRISING THE SAME.
Drawings
The drawing, FIG. 7, is objected because the unlabeled rectangular boxes (e.g. boxes 320-370) shown in the drawing should be provided with descriptive text labels (see 37 CFR 1.83 and 37 CFR 1.84(n)).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency.
Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2023/0071859 A1, IDS).
As to claim 1, Park discloses a thin film transistor substrate (Park, FIGS. 1A-1B, [0059], “thin film transistor substrate 100”), comprising:
a base substrate (Park, FIG. 1B, [0059], “base substrate 110”); and
a first thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT1”) and a second thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT2”) on the base substrate (Park, FIG. 1B, [0059], “base substrate 110”) and connected to each other in series (Park, see FIGS. 1A-1B),
wherein the first thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT1”) includes:
a first active layer (Park, FIGS. 1A-1B, [0076], “first active layer 130”) having a first channel portion (Park, FIGS. 1A-1B, [0076], “channel portion 130n”);
a first gate electrode (Park, FIGS. 1A-1B, [0083], “first gate electrode 150”) insulated from (Park, see FIGS. 1A-1B, [0083], by “first gate insulating layer 141”) the first active layer (Park, FIGS. 1A-1B, [0076], “first active layer 130”) and overlapping (Park, see FIGS. 1A-1B) the first active layer (Park, FIGS. 1A-1B, [0076], “first active layer 130”); and
a first source electrode (Park, FIGS. 1A-1B, [0098], “source electrode 161”) and a first drain electrode (Park, FIG. 1B, [0102], “connection portion 130b … may be a drain area”) in contact with (Park, see FIG. 1B) the first active layer (Park, FIGS. 1A-1B, [0076], “first active layer 130”) and spaced apart from each other (Park, see FIG. 1B),
wherein the second thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT2”) includes:
a second active layer (Park, FIGS. 1A-1B, [0060], “second active layer 230”) having a second channel portion (Park, FIG. 1B, [0077], “channel portion 230n”);
a second gate electrode (Park, FIGS. 1A-1B, [0083], “auxiliary gate electrode 240”) insulated from (Park, see FIG. 1B) the second active layer (Park, FIGS. 1A-1B, [0060], “second active layer 230”) and overlapping (Park, see FIG. 1B) the second active layer (Park, FIGS. 1A-1B, [0060], “second active layer 230”); and
a second source electrode (Park, FIG. 1B, [0102], “connection portion 230a … may serve as source electrodes or drain electrodes without a separate electrode or a separate pad member”) and a second drain electrode (Park, FIG. 1B, [0098], “drain electrode 262”) in contact with (Park, see FIG. 1B) the second active layer (Park, FIGS. 1A-1B, [0060], “second active layer 230”) and spaced apart from each other (Park, see FIG. 1B), and
wherein the first drain electrode (Park, FIG. 1B, [0102], “connection portion 130b … may be a drain area”) and the second source electrode (Park, FIG. 1B, [0102], “connection portion 230a … may serve as source electrodes or drain electrodes without a separate electrode or a separate pad member”) are formed integrally (Park, see FIG. 1B, [0072], “the first active layer 130 and the second active layer 230 may be integrally formed and connected to each other”) and disposed on (Park, see FIG. 1B) a same underlying layer (Park, FIG. 1B, [0081], “second buffer layer 122”).
As to claim 2, Park discloses the thin film transistor substrate of claim 1, wherein the integrally formed first drain electrode and second source electrode together (Park, FIG. 1B, [0102], “connection portions 130b and 230a”) have a circular, rounded (Park, see FIGS. 1A-1B, U-shape; [0046], “a shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details”; it is reasonably inferred that the U shape shown in FIGS. 1A-1B may comprise a rounded U shape), oval, or elliptical shape in a plan view.
As to claim 6, Park discloses the thin film transistor substrate of claim 1, wherein the second channel portion (Park, FIG. 1B, [0077], “channel portion 230n”) has a larger planar area than (Park, see FIGS. 1A-1B) the first channel portion (Park, FIGS. 1A-1B, [0076], “channel portion 130n”) in a plan view.
As to claim 14, Park discloses a display apparatus (Park, FIG. 6, [0139], “display device 600”) comprising the thin film transistor substrate (Park, FIGS. 1A-1B, [0059], “thin film transistor substrate 100”) of claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 10, 17-18 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2023/0071859 A1, IDS) in view of Kim (US 2026/0075932 A1, hereinafter Kim 1).
As to claim 3, Park does not teach the thin film transistor substrate of claim 1, wherein: the first gate electrode and the second gate electrode integrally form a closed loop shape in a plan view; and the first drain electrode and the second source electrode are disposed inside of the closed loop shape integrally formed by the first gate electrode and the second gate electrode in the plan view.
However, Kim 1 teaches the concepts that the first gate electrode (Kim 1, FIGS. 1A-1B, [0032], left portion of “gate electrode 130”) and the second gate electrode (Kim 1, FIGS. 1A-1B, [0032], right portion of “gate electrode 130”) integrally form a closed loop shape in a plan view (Kim 1, see FIGS. 1A-1B, [0040], “gate electrode 130 may have a closed-loop shape”); and
the first drain electrode and the second source electrode (Kim 1, FIGS. 1A-1B, [0035], “source/drain regions 116”) are disposed inside of (Kim 1, see FIGS. 1A-1B) the closed loop shape integrally formed by the first gate electrode and the second gate electrode in the plan view (Kim 1, see FIGS. 1A-1B, [0040], “gate electrode 130 may have a closed-loop shape”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “first gate electrode 150” and the “auxiliary gate electrode 240” to further integrally form the “closed loop-shape” in a plan view, as taught by Kim 1, in order to provide “an integrated circuit device with the intended performance with a minimum area in a highly reduced area by reducing an occupied area of a high-voltage transistor as well as by preventing the formation of an unintended edge channel in the vicinity of an interface between a device isolation region and an active region in the high-voltage transistor and preventing a reduction in threshold voltage through the suppression of a hump phenomenon” (Kim 1, [0006]).
As to claim 10, Kim 1 teaches the thin film transistor substrate of claim 1, wherein: the first gate electrode and the second gate electrode integrally form any one of a circular ring, an elliptical ring, and a rectangular ring with rounded corners in a plan view (Kim 1, see FIGS. 1A-1B, [0040], “gate electrode 130 may have a closed-loop shape”, i.e., a rectangular ring with rounded corners); and
each of an inner surface of the first source electrode and an inner surface of the second drain electrode has a round or curved shape in the plan view (Kim 1, see FIG. 1A, [0035], “first source/drain region 116A”, i.e., a round or curved shape). Examiner renders the same motivation as in claim 3.
As to claim 17, Park teaches a thin film transistor substrate (Park, FIGS. 1A-1B, [0059], “thin film transistor substrate 100”), comprising:
a base substrate (Park, FIG. 1B, [0059], “base substrate 110”); and
a first thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT1”) and a second thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT2”) on the base substrate (Park, FIG. 1B, [0059], “base substrate 110”) and connected to each other in series (Park, see FIGS. 1A-1B),
wherein the first thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT1”) includes:
a first active layer (Park, FIGS. 1A-1B, [0076], “first active layer 130”) having a first channel portion (Park, FIGS. 1A-1B, [0076], “channel portion 130n”);
the first gate electrode (Park, FIGS. 1A-1B, [0083], “ first gate electrode 150”) insulated from the first channel portion (Park, FIGS. 1A-1B, [0076], “channel portion 130n”) and overlapping the first channel portion (Park, see FIGS. 1A-1B, [0076], “channel portion 130n”); and
a first source electrode (Park, FIGS. 1A-1B, [0098], “source electrode 161”) and a first drain electrode (Park, FIG. 1B, [0102], “connection portion 130b … may be a drain area”) in contact with the first active layer (Park, FIGS. 1A-1B, [0076], “first active layer 130”) and disposed respectively at opposite sides of the first channel portion (Park, see FIGS. 1A-1B, [0076], “channel portion 130n”), and
wherein the second thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT1”) includes:
a second active layer (Park, FIGS. 1A-1B, [0060], “second active layer 230”) having a second channel portion (Park, FIG. 1B, [0077], “channel portion 230n”);
the second gate electrode (Park, FIGS. 1A-1B, [0083], “auxiliary gate electrode 240”) insulated from the second channel portion (Park, FIG. 1B, [0077], “channel portion 230n”) and overlapping the second channel portion (Park, see FIG. 1B, [0077], “channel portion 230n”); and
a second source electrode (Park, FIG. 1B, [0102], “connection portion 230a … may serve as source electrodes or drain electrodes without a separate electrode or a separate pad member”) and a second drain electrode (Park, FIG. 1B, [0098], “drain electrode 262”) in contact with the second active layer (Park, FIGS. 1A-1B, [0060], “second active layer 230”) and disposed respectively at opposite sides of the second channel portion (Park, see FIG. 1B, [0077], “channel portion 230n”).
Park does not teach “wherein the first thin film transistor and the second thin film transistor share an integrated gate electrode having a closed loop shape in a plan view, the integrated gate electrode including a first gate electrode at one portion of the closed loop shape and a second gate electrode at another portion of the closed loop shape”.
However, Kim 1 teaches the concepts that wherein the first thin film transistor and the second thin film transistor share an integrated gate electrode (Kim 1, see FIGS. 1A-1B, [0040], “gate electrode 130”) having a closed loop shape (Kim 1, see FIGS. 1A-1B, [0040], “may have a closed-loop shape”) in a plan view, the integrated gate electrode (Kim 1, see FIGS. 1A-1B, [0040], “gate electrode 130”) including a first gate electrode (Kim 1, FIGS. 1A-1B, [0032], left portion of “gate electrode 130”) at one portion of the closed loop shape and a second gate electrode (Kim 1, FIGS. 1A-1B, [0032], right portion of “gate electrode 130”) at another portion of the closed loop shape (Kim 1, see FIGS. 1A-1B). Examiner renders the same motivation as in claim 3.
As to claim 18, Park teaches the thin film transistor substrate of claim 17, wherein:
the first drain electrode (Park, FIG. 1B, [0102], “connection portion 130b … may be a drain area”) and the second source electrode (Park, FIG. 1B, [0102], “connection portion 230a … may serve as source electrodes or drain electrodes without a separate electrode or a separate pad member”) are formed integrally (Park, see FIG. 1B, [0072], “the first active layer 130 and the second active layer 230 may be integrally formed and connected to each other”) and disposed on a same underlying layer (Park, FIG. 1B, [0081], “second buffer layer 122”); and
the integrally formed first drain electrode and second source electrode together (Park, FIG. 1B, [0102], “connection portions 130b and 230a”) have a circular, rounded (Park, see FIGS. 1A-1B, U-shape), oval, or elliptical shape in the plan view.
As to claim 22, Kim 1 teaches the thin film transistor substrate of claim 17, wherein the closed loop shape of the integrated gate electrode is a shape of a circular ring, an oval ring, an elliptical ring, or a rectangular ring with rounded corners (Kim 1, see FIGS. 1A-1B, [0040], “gate electrode 130 may have a closed-loop shape”, i.e., a rectangular ring with rounded corners) in the plan view. Examiner renders the same motivation as in claim 3.
As to claim 23, it recites substantially the same limitations as in claim 6, and Park teaches them. Please see claim 6 for detailed analysis.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2023/0071859 A1, IDS) in view of Kim et al. (KR 20220087742 A, English translation provided by Clarivate Analytics, hereinafter Kim 2).
As to claim 15, Park teaches the display apparatus of claim 14, further comprising:
a plurality of pixels (Park, FIG. 6, [0140], “pixels P”) each having a pixel driving circuit (Park, FIGS. 6-7, [0154], “pixel driving circuit PDC”);
a plurality of gate lines (Park, FIGS. 6-7, [0140], “gate lines GL”) connected respectively to (Park, see FIGS. 6-7) the plurality of pixels (Park, FIG. 6, [0140], “pixels P”); and
a gate driver (Park, FIG. 6, [0147], “gate driver 320”) having a plurality of stages (Park, FIG. 6, [0147], “may include a shift register 350”) each configured to drive a corresponding one of the plurality of gate lines (Park, FIGS. 6-7, [0140], “gate lines GL”) and the pixel driving circuit (Park, FIGS. 6-7, [0154], “pixel driving circuit PDC”) of the corresponding one of the plurality of pixels (Park, FIG. 6, [0140], “pixels P”).
Park does not teach “wherein each of the plurality of stages includes: an output circuit including a pull-up transistor configured to be pulled up by control of a Q node and to output a first clock signal input through a first clock terminal as an output to an output terminal, and including a pull-down transistor configured to pull down the output terminal by control of a QB node; and a control circuit configured to charge and discharges the Q node and to charge and discharge the QB node opposite to the Q node, wherein the control circuit includes QB charging transistors configured to charge the QB node with a high potential voltage, wherein the QB charging transistors include a first QB charging transistor and a second QB charging transistor, wherein a drain electrode of the first QB charging transistor is configured to receive the high potential voltage, and a source electrode of the second QB charging transistor is connected to the QB node, and wherein the first QB charging transistor is the second thin film transistor, and the second QB charging transistor is the first thin film transistor”.
However, Kim 2 teaches the concepts that each of the plurality of stages includes:
an output circuit (Kim 2, FIG. 6, “output unit 50A”) including a pull-up transistor (Kim 2, FIG. 6, “first pull-up transistor T6”) configured to be pulled up by control of a Q node (Kim 2, FIG. 6, “Q node”) and to output a first clock signal input (Kim 2, FIG. 6, “CLKn”) through a first clock terminal (Kim 2, FIG. 6, “clock terminal 12”) as an output to an output terminal (Kim 2, see FIG. 6), and including a pull-down transistor (Kim 2, FIG. 6, “first pull-down transistor T7”) configured to pull down the output terminal (Kim 2, see FIG. 6) by control of a QB node (Kim 2, FIG. 6, “QB node”); and
a control circuit (Kim 2, FIG. 6, “QB stabilization circuit 60” in association with “first discharge unit 20A” and “second charging unit 30A”) configured to charge and discharges the Q node and to charge and discharge the QB node opposite to the Q node (Kim 2, see, e.g., FIGS. 5-6),
wherein the control circuit (Kim 2, FIG. 6, “QB stabilization circuit 60” in association with “first discharge unit 20A” and “second charging unit 30A”) includes QB charging transistors (Kim 2, FIG. 6, “a pair of QB charging transistors T4”) configured to charge the QB node (Kim 2, FIG. 6, “QB node”) with a high potential voltage (Kim 2, FIG. 6, “charged with the above voltage VDD”),
wherein the QB charging transistors (Kim 2, FIG. 6, “a pair of QB charging transistors T4”) include a first QB charging transistor and a second QB charging transistor (Kim 2, see FIG. 6, “a pair of QB charging transistors T4”, upper and lower “QB charging transistors T4”, respectively),
wherein a drain electrode of the first QB charging transistor (Kim 2, see FIG. 6, upper “QB charging transistors T4”) is configured to receive the high potential voltage (Kim 2, see FIG. 6, “charged with the above voltage VDD”), and a source electrode of the second QB charging transistor (Kim 2, see FIG. 6, lower “QB charging transistors T4”) is connected to the QB node (Kim 2, see FIG. 6, “QB node”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “shift register 350” taught by Park to (1) further comprise the circuit of FIG. 6 including the “output unit 50A” and the “QB stabilization circuit 60”, etc., as taught by Kim 2; so that (2) the first QB charging transistor (Kim 2, see FIG. 6, upper “QB charging transistors T4”) is the second thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT2”), and the second QB charging transistor (Kim 2, see FIG. 6, lower “QB charging transistors T4”) is the first thin film transistor (Park, FIGS. 1A-1B, [0059], “TFT1”), in order to provide that, e.g., “the first Q discharge transistor T3 is stably turned off by the sufficiently low and stable gate-off voltage VSS of the QB node to minimize the leakage current of the Q node through the first Q discharge transistor T3. and distortion of the Q node and the gate output OUTn due to the leakage current can be prevented” (Kim, FIG. 6).
Allowable Subject Matter
Claims 4-5, 7-9, 11-13 and 16 and 19-21 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 4, the closest known prior art, i.e., Park et al. (US 2023/0071859 A1, IDS), Kim (US 2026/0075932 A1), Kim et al. (KR 20220087742 A), Sakakura et al. (US 2015/0034945 A1, IDS) and Ofuji et al. (US 2010/0085801 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the first channel portion and the second channel portion are separated from each other by an opening portion therebetween”.
As to claim 5, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the first channel portion has a first length and has a first width perpendicular to the first length and extending along the first channel portion; the second channel portion has a second length and has a second width perpendicular to the second length and extending along the second channel portion; the second width is longer than the first width; and the first length and the second length are equal”.
As to claim 7, Park teaches the thin film transistor substrate of claim 1, wherein the second drain electrode (Park, FIG. 1B, [0098], “drain electrode 262”) has a larger planar area than (Park, see FIG. 1A) the first source electrode (Park, FIGS. 1A-1B, [0098], “source electrode 161”) in a plan view
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the first source electrode has a larger planar area than the first drain electrode in the plan view”.
As to claim 8, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the first channel portion has a U shape in a plan view, and the second channel portion has an inverted U shape in the plan view; and the first gate electrode has a U shape in the plan view, and the second gate electrode has an inverted U shape in the plan view”.
As to claim 9, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the first source electrode has a U shape in a plan view, and the second drain electrode has an inverted U shape in the plan view”.
As to claim 11, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the same underlying layer”.
As to claim 12, it depends from claim 11, and is allowable at least for the same reason above.
As to claim 13, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the first gate electrode is disposed between the base substrate and the first active layer; and the second gate electrode is disposed between the base substrate and the second active layer”.
As to claim 16, Kim 2 teaches the display apparatus of claim 15, wherein:
the control circuit (Kim 2, FIG. 6, “QB stabilization circuit 60” in association with “first discharge unit 20A” and “second charging unit 30A”) further includes Q discharge transistors (Kim 2, FIG. 6, “a pair of first Q discharge transistors T3”) configured to discharge the Q node (Kim 2, FIG. 6, “Q node”) to a gate-off voltage by control of the QB node (Kim 2, FIG. 6, “may be turned on when the QB node has a high voltage to discharge the Q node to the first gate-off voltage VSS of the second power terminal 8”);
the Q discharge transistors (Kim 2, FIG. 6, the “pair of first Q discharge transistors T3”, i.e., upper and lower “first Q discharge transistors T3”, respectively) include a third thin film transistor (Kim 2, FIG. 6, upper “first Q discharge transistors T3”) and a fourth thin film transistor (Kim 2, FIG. 6, upper “first Q discharge transistors T3”) connected in series with each other (Kim 2, see FIG. 6).
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “a planar area of the third channel portion is equal to a planar area of the fourth channel portion in a plan view”.
As to claim 19, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the integrated gate electrode further includes at least one connection portion connected between the first gate electrode and the second gate electrode; and the first gate electrode, the second gate electrode, and the at least one connection portion together integrally form the closed loop shape of the integrated gate electrode”.
As to claim 20, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the first channel portion of the first active layer and the second channel portion of the second active layer are separated from each other by at least one opening portion; and the at least one connection portion of the integrated gate electrode overlap the at least one opening portion in the plan view”.
As to claim 21, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the first channel portion has a U shape, and the second channel portion has an inverted U shape in the plan view; and the first gate electrode has a U shape, and the second gate electrode has an inverted U shape in a plan view”.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure:
Sakakura et al. (US 2015/0034945 A1, IDS) teaches the concept of “semiconductor device with a transistor in which current flowing between a source and a drain when the voltage of a gate electrode is 0 V can be reduced” (Abs.); and
Ofuji et al. (US 2010/0085801 A1) teaches the concept of “TFT1 and TFT2 connected in series with integrally formed 1st drain electrode and 2nd source electrode” (e.g., FIG. 4).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Jul. 30, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2623
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