DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takashi et al. (JP 2011211274 A, hereinafter referred as “Takashi”) in view of Armstrong et al. (US 2004/0215858 A1, hereinafter referred as “Armstrong”).
Regarding claim 1, Takashi discloses a projection image correction system (¶0015-¶0017 discloses projector 100 trapezoidal distortion correction), comprising:
a state control circuit, issuing at least one read request (¶0051 discloses hit determination unit 131 issues a miss-hit request) corresponding to an interpolation operation (¶0013 and ¶0021 discloses method of pixel interpolation) to a first memory (¶0059 discloses the requested cache blocks are read from frame buffer 150) when the at least one read request has not yet been sent to the first memory (¶0073 and ¶0085-¶0088 discloses issuance of request sets writing=1 for the corresponding block; writing=1 signifies that the block is already being fetched/written, so the system waits rather issuing another request; a read request is issued when the corresponding entry is not valid and is not already being written) to obtain at least one set of first pixel information from the first memory (¶0037 discloses the cache block control unit 121 acquires a portion of the uncorrected video data stored in the frame buffer 150 in units of 8x8 pixel cache blocks), storing the at least one set of first pixel information to a second memory (¶0037-¶0038 discloses 8x8 pixel cache blocks are stored in the cache block storage unit 122),…; and
obtaining a plurality of sets of second pixel information used for the interpolation operation from the second memory for an interpolation device (¶0040 discloses the interpolation block reading unit 124 reads interpolation blocks consisting of 4x4 pixels necessary for pixel interpolation in the pixel interpolation unit 125 from the cache block storage unit 122 and supplies them to the pixel interpolation unit 125) …thus the interpolation device performing the interpolation operation according to the plurality of sets of second pixel information (¶0041 and ¶0051 discloses the pixel interpolation unit 125 calculates the pixel value of one interpolated pixel from one interpolation block and filter coefficients based on if the hit detection result indicates that the cache block storage unit 122 has the pixel values necessary for pixel interpolation),
wherein the at least one write completion signal indicates that the least one set of first pixel information has been stored to the second memory (¶0073 and ¶0088 discloses when the specified cache block is stored in the block area specified by the pre-read request, the pre-read request issuing unit 132 updates the corresponding tag information in the cache block tag information storage unit 123 to VALID=1 and WRITING=0), and the plurality of sets of second pixel information include the at least one set of first pixel information (¶0059 discloses when the specified cache block is stored in the block area specified by the pre-read request, the pre-read request issuing unit 132 updates the corresponding tag information in the cache block tag information storage unit 123 to VALID=1 and WRITING=0).
Takashi doesn’t disclose counting the number of the at least one read request sent to the first memory to generate a first count value; a data output circuit, counting according to at least one write completion signal to generate a second count value, and …when the second count value is equal to the first count value.
However, in the same field of endeavor, Armstrong discloses counting the number of the at least one read request sent to the first memory to generate a first count value (¶0030 discloses for each generated request, request counter 62 is incremented to a next identifier, with that identifier stored in the server process in a my_request variable 70 to uniquely identify that request; ¶0069 discloses a frame-buffer implementation to which the request counter is incremented); a data output circuit, counting according to at least one write completion signal to generate a second count value (¶0031 discloses counter 64 is referred to herein as a done counter, and is used to track the number of access requests that have completed; ¶0071-¶0073 discloses incrementing the done counter 62 after completion of the frame-buffer data-transfer request), and …when the second count value is equal to the first count value (¶0039-¶0041 discloses last-done counter 66 is set the current request identifier of the most recently completed request; determining whether the value stored in done counter 64 is equal to the value stored in last_done counter 66).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takashi for the purpose of preventing premature interpolation using incomplete data, supported multiple outstanding memory requests, and improving processing throughput.
Regarding claim(s) 10, this/these method claim(s) has/have similar limitations as system claim(s) 1, and therefore rejected on similar grounds.
4. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takashi in view of Armstrong and in further view of Glasco et al. (US 8,135,926 B1, hereinafter referred as “Glasco”).
Regarding claim 2, Takashi as modified doesn’t disclose the projection image correction system according to claim 1, wherein the state control circuit further records at least one sent request, and compares the at least one read request with the at least one sent request to confirm whether the at least one read request has not yet been sent to the first memory.
However, in the same field of endeavor, Glasco discloses wherein the state control circuit further records at least one sent request (col. 12, lines 21-36 discloses the read command generator 402 also keeps track of all outstanding read commands transmitted to the L2 cache slice 438), and compares the at least one read request with the at least one sent request (col. 12, lines 25-40 discloses the read command generator 402… compares the memory address of the other portion of data necessary to process the atomic operation with the memory addresses associated with the outstanding read commands) to confirm whether the at least one read request has not yet been sent to the first memory (col. 12, lines 36-45 and 57-61 discloses a new read command is generate only when read-command generator 402 determines that local ROP cache 414 will not have the required data).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Takashi for the purpose of allowing operations to continue while requested data is pending and generating memory requests when required data is unavailable locally.
5. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takashi in view of Armstrong and in further view of Minkin et al. (US 2023/0289292 A1, hereinafter referred as “Minkin”).
Regarding claim 5, Takashi as modified doesn’t disclose the projection image correction system according to claim 1, further comprising: a data write circuit, reading the at least one set of first pixel information from the first memory according to the at least one read request, writing the at least one set of first pixel information to the second memory, and accordingly issuing the at least one write completion signal.
However, in the same field of endeavor, Minkin discloses a data write circuit, reading the at least one set of first pixel information (¶0119) from the first memory according to the at least one read request (¶0058 and ¶0061 discloses when a thread running on SM 102 needs access to a block of data, the SM determines access parameters for the block of data in the global memory and, at operation 204, commands TMAU 112, by transmission of a single memory access request, to obtain the block of data), writing the at least one set of first pixel information to the second memory (¶0058 discloses the load from memory command may load data from the global memory 116 and store the data in shared memory 110), and accordingly issuing the at least one write completion signal (¶0149-¶0150 discloses the TMAU supports dedicated instruction that could be used to detect completion of all previously issued TMAU requests).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Takashi for the purpose of providing an indication that each requested pixel block has actually been stored locally.
6. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takashi in view of Armstrong and in further view of Iourcha et al. (US 6,304,268 B1, hereinafter referred as “Iourcha”).
Regarding claim 6, Takashi as modified doesn’t disclose the projection image correction system according to claim 1, wherein the second memory comprises a plurality of memory banks, the plurality of memory banks store a plurality of sets of original pixel information of original image data according to a predetermined order, and the plurality of sets of original pixel information comprise the at least one set of first pixel information.
However, in the same field of endeavor, Iourcha discloses wherein the second memory comprises a plurality of memory banks (col. 11, lines 14-22 and Fig. 9 discloses texture cache 804 is preferably organized into a plurality of banks 902, 904, 906, 908. Each bank 902, 904, 906, 908 includes channel data for 256 texels), the plurality of memory banks store a plurality of sets of original pixel information of original image data according to a predetermined order (col. 1, lines 17-27 discloses texture data representing an digitized image; col. 10, lines 4-18 discloses texture cache 804 provides temporary storage of portions of texture memory 802… each of the texels in the 8x8 block are stored according to a predefined scheme), and the plurality of sets of original pixel information comprise the at least one set of first pixel information (col. 10, lines 4-10 and col. 11, lines 3-10 discloses texel data is transferred from texture memory 802 through write port 802 into texture cache 804. Once transferred, the requested source-image texels become part of the texel information stored in the four-bank texture cache).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Takashi for the purpose of predictably allowing the projection correction system to obtain several neighboring pixels from different banks concurrently rather than through repeated sequential access.
Allowable Subject Matter
7. Claims 3-4 and 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ghebretinsae, Temesghen can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2626
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