CONTROLLER WITH CACHING AND NON-CACHING MODES

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/15/2025 is being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 of U.S. Patent/Application No. 12,461,775 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-20 of the instant application. Claim 1 of the present application corresponds to claims 1-3 of the ‘775 patent, where “A system…” corresponds to claim 1, line 1 of the ‘775 patent; where “a first cache memory…” corresponds to claim 1, lines 3-4 of the ‘775 patent; “a cache controller coupled…” corresponds to claim 1, lines 5-6 of the ‘775 patent; “a second cache memory coupled…” corresponds to claim 1, lines 7-9 of the ‘775 patent; “a configuration register configurable to store…” corresponds to claim 1, lines 10-12 of the ‘775 patent; “wherein the cache controller is configurable to: receive data retrieved…” corresponds to claim 1, lines 14-18 of the ‘775 patent; “store the data in the first cache memory…” corresponds to claim 1, lines 19-21 and claim 2, lines 3-4 of the ‘775 patent; “determine a change of the configuration…” corresponds to claim 3, lines 3-5 of the ‘775 patent; and “based on the change, evict the data…” corresponds to claim 3, lines 3-5 of the ‘775 patent. Claim 1 of the present application corresponds to claims 9-11 of the ‘775 patent, where “A system…” corresponds to claim 9, line 1 of the ‘775 patent; where “a first cache memory…” corresponds to claim 9, lines 4-5 of the ‘775 patent; “a cache controller coupled…” corresponds to claim 9, lines 6-7 of the ‘775 patent; “a second cache memory coupled…” corresponds to claim 9, lines 8-10 of the ‘775 patent; “a configuration register configurable to store…” corresponds to claim 9, lines 11-13 of the ‘775 patent; “wherein the cache controller is configurable to: receive data retrieved…” corresponds to claim 9, lines 17-19 of the ‘775 patent; “store the data in the first cache memory…” corresponds to claim 9, lines 20-22 and claim 10, lines 3-4 of the ‘775 patent; “determine a change of the configuration…” corresponds to claim 11, lines 3-5 of the ‘775 patent; and “based on the change, evict the data…” corresponds to claim 11, lines 3-5 of the ‘775 patent. Claim 2 of the present application corresponds to claim 2 of the ‘775 patent, where “wherein the cache controller is configurable to…” corresponds to claim 2, lines 1-2 of the ‘775 patent; and “store the data in the first cache memory…” corresponds to claim 2, lines 3-4 of the ‘775 patent. Claim 2 of the present application corresponds to claim 10 of the ‘775 patent, where “wherein the cache controller is configurable to…” corresponds to claim 10, lines 1-2 of the ‘775 patent; and “store the data in the first cache memory…” corresponds to claim 10, lines 3-4 of the ‘775 patent. Claim 3 of the present application corresponds to claim 3 of the ‘775 patent, where “wherein the cache controller is configurable to…” corresponds to claim 3, lines 1-2 of the ‘775 patent; and “determine the change of the configuration value…” corresponds to claim 3, lines 3-5 of the ‘775 patent. Claim 3 of the present application corresponds to claim 11 of the ‘775 patent, where “wherein the cache controller is configurable to…” corresponds to claim 11, lines 1-2 of the ‘775 patent; and “determine the change of the configuration value…” corresponds to claim 11, lines 3-5 of the ‘775 patent. Claim 4 of the present application corresponds to claims 1, 3 and 5 of the ‘775 patent, where “a processor…” corresponds to claim 5, line 2 of the ‘775 patent; “provide a memory request to the cache controller…” corresponds to claim 1, lines 14-18 of the ‘775 patent; and “provide the memory request…” corresponds to claim 1, line 16 of the ‘775 patent. Claim 4 of the present application corresponds to claim 9 of the ‘775 patent, where “a processor…” corresponds to claim 9, line 2 of the ‘775 patent; “provide a memory request to the cache controller…” corresponds to claim 9, lines 14-19 of the ‘775 patent; and “provide the memory request…” corresponds to claim 9, lines 18-19 of the ‘775 patent. Claim 5 of the present application corresponds to claims 1 and 3-4 of the ‘775 patent, where “wherein the processor is configurable to inhibit providing memory requests…” corresponds to claim 4, lines 3-6 of the ‘775 patent. Claim 5 of the present application corresponds to claims 9 and 11-12 of the ‘775 patent, where “wherein the processor is configurable to inhibit providing memory requests…” corresponds to claim 12, lines 1-4 of the ‘775 patent. Claim 6 of the present application corresponds to claims 1, 3 and 5 of the ‘775 patent, where “the second cache memory further includes a second address…” corresponds to claim 5, lines 4-5 of the ‘775 patent; and “the processor is configurable to provide a memory request…” corresponds to claim 5, lines 6-8 of the ‘775 patent. Claim 6 of the present application corresponds to claims 9, 11 and 13 of the ‘775 patent, where “the second cache memory further includes a second address…” corresponds to claim 13, lines 1-2 of the ‘775 patent; and “the processor is configurable to provide a memory request…” corresponds to claim 13, lines 2-5 of the ‘775 patent. Claim 7 of the present application corresponds to claim 6 of the ‘775 patent, where “invalidate at least one cache line of the first cache memory…” corresponds to claim 6, lines 1-5 of the ‘775 patent. Claim 7 of the present application corresponds to claim 14 of the ‘775 patent, where “invalidate at least one cache line of the first cache memory…” corresponds to claim 14, lines 1-5 of the ‘775 patent. Claim 8 of the present application corresponds to claim 7 of the ‘775 patent, where “invalidate the at least one cache line by writing back…” corresponds to claim 7, lines 1-4 of the ‘775 patent. Claim 8 of the present application corresponds to claims 9 and 14-15 of the ‘775 patent, where “invalidate the at least one cache line by writing back…” corresponds to claim 15, lines 1-4 of the ‘775 patent. Claim 9 of the present application corresponds to claim 8 of the ‘775 patent, where “provide an indication based on that invalidation…” corresponds to claim 8, lines 1-4 of the ‘775 patent. Claim 9 of the present application corresponds to claim 9 and 14-16 of the ‘775 patent, where “provide an indication based on that invalidation…” corresponds to claim 16, lines 1-4 of the ‘775 patent. Claim 10 of the present application corresponds to claim 1 of the ‘775 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 1, lines 2-4 and 7-9 of the ‘775 patent. Claim 10 of the present application corresponds to claim 9 of the ‘775 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 9, lines 4-5 and 8-10 of the ‘775 patent. Claim 11 of the present application corresponds to claims 1-3 of the ‘775 patent, where “receiving, at a cache controller, data retrieved…” corresponds to claim 1, lines 14-18 of the ‘775 patent; “storing, by the cache controller, the data in the first cache memory…” corresponds to claim 1, lines 19-21 and claim 2, lines 3-4 of the ‘775 patent; “determining, by the cache controller, a change of the configuration…” corresponds to claim 3, lines 3-5 of the ‘775 patent; and “based on the change, evicting…” corresponds to claim 3, lines 3-5 of the ‘775 patent. Claim 11 of the present application corresponds to claims 9-11 of the ‘775 patent, where “receiving, at a cache controller, data retrieved…” corresponds to claim 9, lines 17-19 of the ‘775 patent; “storing, by the cache controller, the data in the first cache memory…” corresponds to claim 9, lines 20-22 and claim 10, lines 3-4 of the ‘775 patent; “determining, by the cache controller, a change of the configuration…” corresponds to claim 11, lines 3-5 of the ‘775 patent; and “based on the change, evictinng…” corresponds to claim 11, lines 3-5 of the ‘775 patent. Claim 11 of the present application corresponds to claims 17-18 of the ‘775 patent, where “receiving, at a cache controller, data retrieved…” corresponds to claim 17, lines 10-14 of the ‘775 patent; “storing, by the cache controller, the data in the first cache memory…” corresponds to claim 17, lines 15-18 of the ‘775 patent; “determining, by the cache controller, a change of the configuration…” corresponds to claim 18, lines 2-5 of the ‘775 patent; and “based on the change, evicting…” corresponds to claim 18, lines 6-7 of the ‘775 patent. Claim 12 of the present application corresponds to claim 2 of the ‘775 patent, where “wherein storing the data in the first cache memory…” corresponds to claim 2, lines 3-4 of the ‘775 patent. Claim 12 of the present application corresponds to claim 10 of the ‘775 patent, where “wherein storing the data in the first cache memory…” corresponds to claim 10, lines 3-4 of the ‘775 patent. Claim 13 of the present application corresponds to claim 2 of the ‘775 patent, where “wherein determining the change of the configuration value…” corresponds to claim 2, lines 1-2 of the ‘775 patent. Claim 13 of the present application corresponds to claim 11 of the ‘775 patent, where “wherein determining the change of the configuration value…” corresponds to claim 11, lines 3-5 of the ‘775 patent. Claim 13 of the present application corresponds to claim 18 of the ‘775 patent, where “wherein determining the change of the configuration value…” corresponds to claim 18, lines 2-5 of the ‘775 patent. Claim 14 of the present application corresponds to claims 1, 3 and 5 of the ‘775 patent, where “prior to receiving data, receiving, by the cache controller, a memory request …” corresponds to claim 1, lines 14-18 of the ‘775 patent; and “providing, by the cache controller the memory request…” corresponds to claim 1, line 16 of the ‘775 patent. Claim 14 of the present application corresponds to claim 9 of the ‘775 patent, where “prior to receiving data, receiving, by the cache controller, a memory request…” corresponds to claim 9, lines 14-19 of the ‘775 patent; and “providing, by the cache controller the memory request…” corresponds to claim 9, lines 18-19 of the ‘775 patent. Claim 15 of the present application corresponds to claims 1, 3-4 of the ‘775 patent, where “inhibiting providing memory requests…” corresponds to claim 4, lines 3-6 of the ‘775 patent. Claim 15 of the present application corresponds to claims 9 and 11-12 of the ‘775 patent, where “inhibiting providing memory requests…” corresponds to claim 12, lines 1-4 of the ‘775 patent. Claim 15 of the present application corresponds to claim 19 of the ‘775 patent, where “inhibiting providing memory requests…” corresponds to claim 19, lines 2-4 of the ‘775 patent. Claim 16 of the present application corresponds to claims 1, 3 and 5 of the ‘775 patent, where “the second cache memory further includes a second address…” corresponds to claim 5, lines 4-5 of the ‘775 patent; and “providing a memory request…” corresponds to claim 5, lines 6-8 of the ‘775 patent. Claim 16 of the present application corresponds to claims 9, 11 and 13 of the ‘775 patent, where “the second cache memory further includes a second address…” corresponds to claim 13, lines 1-2 of the ‘775 patent; and “providing a memory request…” corresponds to claim 13, lines 2-5 of the ‘775 patent. Claim 16 of the present application corresponds to claim 20 of the ‘775 patent, where “the second cache memory further includes a second address…” corresponds to claim 20, lines 1-3 of the ‘775 patent; and “providing a memory request…” corresponds to claim 20, lines 4-6 of the ‘775 patent. Claim 17 of the present application corresponds to claim 6 of the ‘775 patent, where “invalidating at least one cache line of the first cache memory…” corresponds to claim 6, lines 1-5 of the ‘775 patent. Claim 17 of the present application corresponds to claim 14 of the ‘775 patent, where “invalidating at least one cache line of the first cache memory…” corresponds to claim 14, lines 1-5 of the ‘775 patent. Claim 18 of the present application corresponds to claim 7 of the ‘775 patent, where “invalidating the at least one cache line by writing back…” corresponds to claim 7, lines 1-4 of the ‘775 patent. Claim 18 of the present application corresponds to claims 9 and 14-15 of the ‘775 patent, where “invalidating the at least one cache line by writing back…” corresponds to claim 15, lines 1-4 of the ‘775 patent. Claim 19 of the present application corresponds to claim 8 of the ‘775 patent, where “providing an indication based on that invalidation…” corresponds to claim 8, lines 1-4 of the ‘775 patent. Claim 19 of the present application corresponds to claim 9 and 14-16 of the ‘775 patent, where “providing an indication based on that invalidation…” corresponds to claim 16, lines 1-4 of the ‘775 patent. Claim 20 of the present application corresponds to claim 1 of the ‘775 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 1, lines 2-4 and 7-9 of the ‘775 patent. Claim 20 of the present application corresponds to claim 9 of the ‘775 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 9, lines 4-5 and 8-10 of the ‘775 patent. Claims 1-20 of U.S. Patent/Application No. 11,907,753 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-20 of the instant application. Claim 1 of the present application corresponds to claim 1 of the ‘753 patent, “a first cache memory…” corresponds to claim 1, lines 2 of the ‘753 patent; “a cache controller coupled…” corresponds to claim 1, line 3 of the ‘753 patent; “a second cache memory coupled…” corresponds to claim 1, lines 4-8 of the ‘753 patent; “a configuration register configurable to store…” corresponds to claim 1, lines 11-16 of the ‘753 patent; “wherein the cache controller is configurable to: receive data retrieved…” corresponds to claim 1, lines 17-20 of the ‘753 patent; “store the data in the first cache memory…” corresponds to claim 1, lines 21-22 of the ‘753 patent; “determine a change of the configuration…” corresponds to claim 1, line 23 of the ‘753 patent; and “based on the change, evict the data…” corresponds to claim 1, lines 27-28 of the ‘753 patent. Claim 1 of the present application corresponds to claim 12 of the ‘753 patent, where “a first cache memory…” corresponds to claim 12, lines 3-4 of the ‘753 patent; “a cache controller coupled…” corresponds to claim 12, line 5-6 of the ‘753 patent; “a second cache memory coupled…” corresponds to claim 12, 9-10 of the ‘753 patent; “a configuration register configurable to store…” corresponds to claim 12, lines 7-8 of the ‘753 patent; “wherein the cache controller is configurable to: receive data retrieved…” corresponds to claim 12, lines 22-24 of the ‘753 patent; “store the data in the first cache memory…” corresponds to claim 12, lines 26-28 of the ‘753 patent; “determine a change of the configuration…” corresponds to claim 12, lines 29-32 of the ‘753 patent; and “based on the change, evict the data…” corresponds to claim 12, lines 33-34 of the ‘753 patent. Claim 2 of the present application corresponds to claim 1 of the ‘753 patent, where “store the data in the first cache memory…” corresponds to claim 1, lines 21-22 of the ‘753 patent. Claim 2 of the present application corresponds to claim 12 of the ‘753 patent, where “store the data in the first cache memory…” corresponds to claim 12, lines 12-15 of the ‘753 patent. Claim 3 of the present application corresponds to claim 1 of the ‘753 patent, where “determine the change of the configuration value …” corresponds to claim 1, lines 23-26 of the ‘775 patent. Claim 3 of the present application corresponds to claim 12 of the ‘753 patent, where “determine the change of the configuration value …” corresponds to claim 12, lines 29-32 of the ‘753 patent. Claim 4 of the present application corresponds to claims 1-2 and 9 of the ‘753 patent, where “a processor…” corresponds to claim 2, line 1 of the ‘753 patent; “provide a memory request to the cache controller…” corresponds to claim 2, lines 1-4 of the ‘753 patent; and “provide the memory request…” corresponds to claim 9, line 1-4 of the ‘753 patent. Claim 4 of the present application corresponds to claims 12 of the ‘753 patent, where “a processor…” corresponds to claim 12, line 2 of the ‘753 patent; “provide a memory request to the cache controller…” corresponds to claim 12, lines 22-23 of the ‘753 patent; and “provide the memory request…” corresponds to claim 12, line 22-24 of the ‘753 patent. Claim 5 of the present application corresponds to claims 6 of the ‘753 patent, where “wherein the processor is configurable to inhibit providing memory requests…” corresponds to claim 4, lines 3-5 of the ‘753 patent. Claim 5 of the present application corresponds to claims 15 of the ‘753 patent, where “wherein the processor is configurable to inhibit providing memory requests…” corresponds to claim 15, lines 3-6 of the ‘753 patent. Claim 6 of the present application corresponds to claims 1 and 6 of the ‘753 patent, where “the second cache memory further includes a second address…” corresponds to claim 6, lines 2-4 of the ‘753 patent; and “the processor is configurable to provide a memory request…” corresponds to claim 6, lines 1-5 of the ‘753 patent. Claim 6 of the present application corresponds to claims 12 and 15-16 of the ‘753 patent, where “the second cache memory further includes a second address…” corresponds to claim 16, lines 2-3 of the ‘753 patent; and “the processor is configurable to provide a memory request…” corresponds to claim 16, lines 1-4 of the ‘753 patent. Claim 7 of the present application corresponds to claim 4 of the ‘753 patent, where “invalidate at least one cache line of the first cache memory…” corresponds to claim 4, lines 1-3 of the ‘753 patent. Claim 7 of the present application corresponds to claim 13 of the ‘753 patent, where “invalidate at least one cache line of the first cache memory…” corresponds to claim 13, lines 1-3 of the ‘753 patent. Claim 8 of the present application corresponds to claim 5 of the ‘753 patent, where “invalidate the at least one cache line by writing back…” corresponds to claim 5, lines 1-3 of the ‘753 patent. Claim 8 of the present application corresponds to claim 14 of the ‘753 patent, where “invalidate the at least one cache line by writing back…” corresponds to claim 14, lines 1-3 of the ‘753 patent. Claim 9 of the present application corresponds to claim 8 of the ‘753 patent, where “provide an indication based on that invalidation…” corresponds to claim 8, lines 3-5 of the ‘753 patent. Claim 9 of the present application corresponds to claim 12, 15 and 17 of the ‘753 patent, where “provide an indication based on that invalidation…” corresponds to claim 17, lines 4-6 of the ‘753 patent. Claim 10 of the present application corresponds to claim 3 of the ‘753 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 3, lines 2 and 4-5 of the ‘753 patent. Claim 10 of the present application corresponds to claim 12 of the ‘753 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 12, lines 3-4 and 9-10 of the ‘753 patent. Claim 11 of the present application corresponds to claim 1 of the ‘753 patent, where “receiving, at a cache controller, data retrieved…” corresponds to claim 1, lines 17-20 of the ‘753 patent; “storing, by the cache controller, the data in the first cache memory…” corresponds to claim 1, lines 21-22 of the ‘753 patent; “determining, by the cache controller, a change of the configuration…” corresponds to claim 1, line 23 of the ‘753 patent; and “based on the change, evicting…” corresponds to claim 1, lines 27-28 of the ‘753 patent. Claim 11 of the present application corresponds to claim 12 of the ‘753 patent, where “receiving, at a cache controller, data retrieved…” corresponds to claim 12, lines 22-24 of the ‘753 patent; “storing, by the cache controller, the data in the first cache memory…” corresponds to claim 12, lines 26-28 of the ‘753 patent; “determining, by the cache controller, a change of the configuration…” corresponds to claim 12, lines 29-32 of the ‘753 patent; and “based on the change, evicting…” corresponds to claim 12, lines 33-34 of the ‘753 patent. Claim 11 of the present application corresponds to claim 19 of the ‘753 patent, where “receiving, at a cache controller, data retrieved…” corresponds to claim 19, lines 10-14 of the ‘753 patent; “storing, by the cache controller, the data in the first cache memory…” corresponds to claim 19, lines 23-25 of the ‘753 patent; “determining, by the cache controller, a change of the configuration…” corresponds to claim 19, lines 26-29 of the ‘775 patent; and “based on the change, evicting…” corresponds to claim 19, lines 30-31 of the ‘775 patent. Claim 12 of the present application corresponds to claim 1 of the ‘753 patent, where “wherein storing the data in the first cache memory…” corresponds to claim 1, lines 21-22 of the ‘753 patent. Claim 12 of the present application corresponds to claim 12 of the ‘753 patent, where “store the data in the first cache memory…” corresponds to claim 12, lines 12-15 of the ‘753 patent. Claim 12 of the present application corresponds to claim 19 of the ‘753 patent, where “store the data in the first cache memory…” corresponds to claim 19, lines 7-9 and 26-29 of the ‘753 patent. Claim 13 of the present application corresponds to claim 1 of the ‘753 patent, where “wherein determining the change of the configuration value …” corresponds to claim 1, lines 23-26 of the ‘775 patent. Claim 13 of the present application corresponds to claim 12 of the ‘753 patent, where “wherein determining the change of the configuration value …” corresponds to claim 12, lines 29-32 of the ‘753 patent. Claim 13 of the present application corresponds to claim 19 of the ‘753 patent, where “wherein determining the change of the configuration value …” corresponds to claim 19, lines 26-29 of the ‘753 patent. Claim 14 of the present application corresponds to claims 1-2 and 9 of the ‘753 patent, where “prior to receiving data, receiving, by the cache controller, a memory request” corresponds to claim 2, lines 1-4 of the ‘753 patent; and “providing, by the cache controller, the memory request…” corresponds to claim 9, line 1-4 of the ‘753 patent. Claim 14 of the present application corresponds to claims 12 of the ‘753 patent, where “prior to receiving data, receiving, by the cache controller, a memory request…” corresponds to claim 12, lines 22-23 of the ‘753 patent; and “providing, by the cache controller, the memory request…” corresponds to claim 12, line 22-24 of the ‘753 patent. Claim 14 of the present application corresponds to claims 12 of the ‘753 patent, where “prior to receiving data, receiving, by the cache controller, a memory request…” corresponds to claim 19, lines 14-16 of the ‘753 patent; and “providing, by the cache controller, the memory request…” corresponds to claim 19, line 19-25 of the ‘753 patent. Claim 15 of the present application corresponds to claims 6 of the ‘753 patent, where “inhibiting providing memory requests…” corresponds to claim 4, lines 3-5 of the ‘753 patent. Claim 15 of the present application corresponds to claims 15 of the ‘753 patent, where “inhibiting providing memory requests…” corresponds to claim 15, lines 3-6 of the ‘753 patent. Claim 15 of the present application corresponds to claim 20 of the ‘753 patent, where “wherein the processor is configurable to inhibit providing memory requests…” corresponds to claim 20, lines 2-4 of the ‘753 patent. Claim 16 of the present application corresponds to claims 1 and 6 of the ‘753 patent, where “the second cache memory further includes a second address…” corresponds to claim 6, lines 2-4 of the ‘753 patent; and “providing a memory request…” corresponds to claim 6, lines 1-5 of the ‘753 patent. Claim 16 of the present application corresponds to claims 12 and 15-16 of the ‘753 patent, where “the second cache memory further includes a second address…” corresponds to claim 16, lines 2-3 of the ‘753 patent; and “providing a memory request…” corresponds to claim 16, lines 1-4 of the ‘753 patent. Claim 16 of the present application corresponds to claims 20 of the ‘753 patent, where “the second cache memory further includes a second address…” corresponds to claim 20, lines 5-6 of the ‘753 patent; and “the processor is configurable to provide a memory request…” corresponds to claim 20, lines 5-8 of the ‘753 patent. Claim 17 of the present application corresponds to claim 4 of the ‘753 patent, where “invalidating at least one cache line of the first cache memory…” corresponds to claim 4, lines 1-3 of the ‘753 patent. Claim 17 of the present application corresponds to claim 13 of the ‘753 patent, where “invalidating at least one cache line of the first cache memory…” corresponds to claim 13, lines 1-3 of the ‘753 patent. Claim 18 of the present application corresponds to claim 5 of the ‘753 patent, where “invalidating the at least one cache line by writing back…” corresponds to claim 5, lines 1-3 of the ‘753 patent. Claim 18 of the present application corresponds to claim 14 of the ‘753 patent, where “invalidating the at least one cache line by writing back…” corresponds to claim 14, lines 1-3 of the ‘753 patent. Claim 19 of the present application corresponds to claim 8 of the ‘753 patent, where “providing an indication based on that invalidation…” corresponds to claim 8, lines 3-5 of the ‘753 patent. Claim 19 of the present application corresponds to claim 12, 15 and 17 of the ‘753 patent, where “providing an indication based on that invalidation…” corresponds to claim 17, lines 4-6 of the ‘753 patent. Claim 20 of the present application corresponds to claim 3 of the ‘753 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 3, lines 2 and 4-5 of the ‘753 patent. Claim 20 of the present application corresponds to claim 12 of the ‘753 patent, where “wherein the first cache memory is a level-two (L2) cache memory and the second cache memory is a level-three (L3) cache memory” corresponds to claim 12, lines 3-4 and 9-10 of the ‘753 patent. Allowable Subject Matter Claim 1-20 would be allowable if Double Patenting rejection is overcome. The following is a statement of reasons for the indication of allowable subject matter: wherein the cache controller is configurable to: receive data retrieved from the first address region of the second cache memory; store the data in the first cache memory based on the configuration value associated with the first address region of the second cache memory; determine a change of the configuration value; and based on the change, evict the data from the first cache memory as recited in claims 1 and 11. Comparan et al. (US2009/0182944) teaches load/store unit 202 is responsive to a bypass signal 214 which is used to selectively enable or disable L1 cache bypass consistent with the invention. When L1 cache bypass is disabled, returning data requested by a data request is forwarded to L1 cache 210 by load/store unit 202 over signal path 216. When L1 cache bypass is enabled, however, signal path 216 is deactivated such that returning data forwarded to register file 204 is not concurrently provided to the L1 cache (see paragraph 66). However, Comparan does not teach wherein the cache controller is configurable to: receive data retrieved from the first address region of the second cache memory; store the data in the first cache memory based on the configuration value associated with the first address region of the second cache memory; determine a change of the configuration value; and based on the change, evict the data from the first cache memory as recited in claims 1 and 11. Selgas et al. (US 5,724,549) teaches wherein comparator 61 receives the NC0 bit from cache configuration register CCR0, while comparator 62 receives the NC1 bit from the same register. (See, Table 3A.) If either, or both, of these bits is set, thereby defining the corresponding region of address space as non-cacheable, then the associated comparator output will indicate that the current address is non-cacheable if it is within such non-cacheable region (see column 13, lines 15-25)… FLMIO could be implemented by designating the non-cacheable region register NCR4 to be programmable to define a region of memory-mapped I/O space as either (a) non-cacheable, or (b) non-cacheable with FLUSH. That is, a read or read/write access directed to a FLMIO location within the region specified by NCR4 would not be cached by the microprocessor, and would also cause the microprocessor to invalidate the contents of the cache (see column 17, lines 49-56). However, Selgas et al. does not teach wherein the cache controller is configurable to: receive data retrieved from the first address region of the second cache memory; store the data in the first cache memory based on the configuration value associated with the first address region of the second cache memory; determine a change of the configuration value; and based on the change, evict the data from the first cache memory as recited in claims 1 and 11. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Klaiber et al. (US 8,117,421) teaches a cacheability bit 203 that states whether the corresponding page in physical memory is currently cacheable or non-cacheable (see column 4, lines 41-43)… first cacheability mismatch indicates that the current cacheability characteristic reflected by cacheability bit 203 is "cacheable," but that the desired cacheability state 303 is "non-cacheable." This mismatch is indicative that a cacheable-to-non-cacheable transition is to occur in accessing the data associated with the new TLB entry (see column 5, lines 18-45). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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