Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
2. The continuation application filed on October 15, 2025, has been received and made of record. There are 1-20 claims in the application of which claim 1 is independent claim and 2-20 are dependent claims. Therefore, claims 1-20 are pending for consideration.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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4. Claims 1, and 4-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of US Patent No. US 12,471,376 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because except for minor wording and insignificant change in terminology, each and every limitation of claims 1-20 of US published Patent No. US 12,471,376 B2 reads the corresponding limitations of claims 1, and 4-20 of the current application No. 19/358,842. Both the current application No. 19/358,842 and the published patent No. US 12,471,376 B2 claimed a display array substrate having display panel with pixel driving circuit.
Comparison of claims 1 and 4-20 of the current application and claims 1-20 of the US published Patent No. 12,471,376 B2 is given below: -
Patent Application
No. 19/358,842
US Patent
No. US 12,471,376 B2
Claim 1: An array substrate, comprising a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines, and a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a light emitting control transistor, a sixth transistor, and a seventh transistor; a respective first reset signal line of the plurality of first reset signal lines is connected to a row of first connecting lines of the plurality of first connecting lines, which in turn are connected to source electrodes of six transistors in a row of subpixels, respectively;
a respective second reset signal line of the plurality of second reset signal lines is connected to one or more of the plurality of third reset signal lines;
the respective third reset signal line is connected to source electrodes of second reset transistors in a column of subpixels;
a drain electrode of the seventh transistor is connected to an N3 node; and
the N3 node is a node connected to a drain electrode of the driving transistor and a source electrode of the light emitting control transistor.
Claim 5: The array substrate of claim 1, comprising a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises an N1 node connected to a gate electrode of a driving transistor and an N4 node connected to a drain electrode of a light emitting control transistor; and
reset voltage levels at the N1 node and the N4 node are different from each other.
Claim 1: An array substrate, comprising a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines;
wherein a respective first reset signal line of the plurality of first reset signal lines is connected to a row of first connecting lines of the plurality of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively;
the plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network;
a respective second reset signal line of the plurality of second reset signal lines is connected to one or more of the plurality of third reset signal lines; a respective third reset signal line of the plurality of third reset signal lines is connected to one or more of the plurality of second reset signal lines;
the plurality of second reset signal lines respectively cross over the plurality of third reset signal lines; and
the respective third reset signal line is connected to source electrodes of second reset transistors in a column of subpixels.
Claim 3: The array substrate of claim 1, comprising a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises an N1 node connected to a gate electrode of a driving transistor and an N4 node connected to a drain electrode of a light emitting control transistor; and
reset voltage levels at the N1 node and the N4 node are different from each other.
Claim 16: The array substrate of claim 1, comprising a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a third reset transistor;
a drain electrode of the third reset transistor is connected to an N3 node; and
the N3 node is a node connected to a drain electrode of a driving transistor and a source electrode of a light emitting control transistor.
Claim 6 corresponds to part of claim 4 of US patent No. US 12,471,376 B2;
Claim 7 corresponds to part of claim 16 of US patent No. US 12,471,376 B2;
Claim 8 corresponds to part of claim 6 of US patent No. US 12,471,376 B2;
Claim 9 corresponds to part of claim 6 of US patent No. US 12,471,376 B2;
Claim 10 corresponds to part of claim 5 of US patent No. US 12,471,376 B2;
Claim 11 corresponds to part of claims 6 and 7 of US patent No. US 12,471,376 B2;
Claim 12 corresponds to part of claim 7 of US patent No. US 12,471,376 B2;
Claim 13 corresponds to part of claim 8 of US patent No. US 12,471,376 B2;
Claim 14 corresponds to part of claim 9 of US patent No. US 12,471,376 B2;
Claim 15 corresponds to part of claim 13 of US patent No. US 12,471,376 B2;
Claim 16 corresponds to part of claim 15 of US patent No. US 12,471,376 B2;
Claim 17 corresponds to part of claim 17 of US patent No. US 12,471,376 B2;
Claim 18 corresponds to claim 18 of US patent No. US 12,471, 376 B2;
Claim 19 corresponds to part of claim 1 of US patent No. US 12,471,376 B2; and
Claim 20 corresponds to part of claim 20 of US patent No. US 12,471,376 B2.
5. Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,271,250 B2 in view of Park et al.(US 2019/0221165 A1) (herein after Park).
Regarding claim 2, claims of US published patent No. US 12,471,376 B2 is not found to recite the claim limitations, “the array substrate of claim 1, wherein gate electrodes of sixth transistors in a first row and gate electrodes of seventh transistors in a second row are parts of a unitary structure”.
However, Park teaches a pixel and organic light emitting display device, wherein gate electrodes of sixth transistors in a first row and gate electrodes of seventh transistors in a second row are parts of a unitary structure(fig.3, Para 86-88).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to have modified claims 1-20 of U.S. Patent No. US 12,471,376 B2 with the teaching of Park to include the feature in order to provide a display device including a pixel capable of improving display quality of the display device.
6. Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,471,376 B2 in view of Huang et al.(US 2021/0134219 A1) (herein after Huang).
Regarding claim 3, claims of US published patent No. US 12,471,376 B2 is not found to recite the claim limitations, “the array substrate of claim 1, wherein sixth transistors in a first row and seventh transistors in a second row are configured to receive reset signals from a same reset signal”.
However, Huang teaches a pixel and organic light emitting display device, wherein sixth transistors(M3, fig.2) in a first row and seventh transistors(M4, fig.2) in a second row are configured to receive reset signals(V1) from a same reset signal(Para-49)”.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to have modified claims 1-20 of U.S. Patent No. US 12,471,376 B2 with the teaching of Huang to include the feature in order to provide a display device having Pixel circuit capable of inhibiting residual images.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
10. Claims 1-3, 5, and 20 are rejected under 35 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al.(US 2021/0134 219 A1) (herein after Huang).
Regarding claim 1, Huang teaches an array substrate, comprising a plurality of first reset signal lines(first voltage V1, fig.2, Para-49) configured to provide a plurality of first reset signals(Para-60, 89-90), a plurality of second reset signal lines(V1) configured to provide a plurality of second reset signals(V1, applied to M3), a plurality of third reset signal lines(V1), and a plurality of first connecting lines(figs.8-10), and a plurality of pixel driving circuits(fig.1, Para-42, 44) configured to drive light emission in a plurality of subpixels(pixel circuit 100, fig.1, Para-42);
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor(Md), a light emitting control transistor(M5 or M6), a sixth transistor(M3), and a seventh transistor(M4);
a respective first reset signal line(V1) of the plurality of first reset signal lines is connected to a row of first connecting lines of the plurality of first connecting lines (figs.2, 8-10), which in turn are connected to source electrodes of six transistors(M3) in a row of subpixels, respectively;
a respective second reset signal line(V1) of the plurality of second reset signal lines is connected to one or more of the plurality of third reset signal lines(V1);
the respective third reset signal line is connected to source electrodes of second reset transistors(M2) in a column of subpixels;
a drain electrode of the seventh transistor(M4) is connected to an N3 node(N2); and
the N3 node(N2) is a node connected to a drain electrode of the driving transistor(Md) and a source electrode of the light emitting control transistor(M6).
Regarding claim 2, Huang teaches the array substrate of claim 1, wherein gate electrodes of sixth transistors in a first row and gate electrodes of seventh transistors in a second row are parts of a unitary structure(fig.2, Para-50).
Regarding claim 3, Huang teaches the array substrate of claim 1, wherein sixth transistors(M3, fig.2) in a first row and seventh transistors(M4, fig.2) in a second row are configured to receive reset signals from a same reset signal(Para-49).
Regarding claim 4, Huang teaches the array substrate of claim 1, wherein voltage levels of the plurality of first reset signals and the plurality of second reset signals are different from each other(Para-50).
Regarding claim 5, Huang teaches the array substrate of claim 1, comprising a plurality of pixel driving circuits(driving sub-circuit 120, fig.1, Para-49) configured to drive light emission in a plurality of subpixels(light-emitting element 110, fig.1);
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises an N1 node(N3) connected to a gate electrode of a driving transistor(Md) and an N4 node (N2) connected to a drain electrode of a light emitting control transistor(M6); and
reset voltage levels at the N1 node and the N4 node are different from each other(it is obvious).
Regarding claim 20, Huang teaches a display apparatus(display panel 600, fig.6, Para-111), comprising the array substrate of claim 1(see the rejection of claim 1), and an integrated circuit connected to the array substrate(fig.6).
Examiner Note
11. The Examiner cites particular figures, paragraphs, columns and line numbers in the references, as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicants fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the references or as disclosed by the Examiner.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached Mon-Fri: 9:00AM - 5:30PM.
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/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2626
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