DETAILED ACTION
Claims 1-20 filed October 16th 2025 are pending in the current action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 13, 16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chien et al. (US2024/0355259)
Consider claim 1, where Chien discloses a display apparatus comprising: a display panel including a first screen block and a second screen block; (See Chien Fig. 8 and ¶48 where In the embodiment shown in FIG. 8, the display panel 830 is divided into a left half and a right half.) a first gate driving circuit configured to supply a scan output to first gate lines of the first screen block; (See Chien Fig. 8 and ¶48 where the gate driver 821 is disposed on the left side of the display panel 830) and a second gate driving circuit configured to supply a scan output to second gate lines of the second screen block, (See Chien Fig. 8 and ¶48 where the gate driver 822 is arranged on the right side of the display panel 830.) wherein the first screen block comprises a first high frequency region where first image data is updated at a first data refresh rate, and a first low frequency region where second image data is updated at a second data refresh rate which is less than the first data refresh rate, (See Chien Fig. 8 and ¶49 where based on the control of the control device 810 on the gate driver 821, the high frame rate area 831 of the display panel 830 has a high frame rate (e.g., 120 Hz), and the low frame rate area 832 of the display panel 830 has a low frame rate (e.g., 40 Hz).) and wherein the second screen block comprises a second high frequency region where third image data is updated at a third data refresh rate, and a second low frequency region where fourth image data is updated at a fourth data refresh rate which is less than the third data refresh rate. (See Chien Fig. 8 and ¶50 where based on the control of the control device 810 on the gate driver 822, the high frame rate area 833 of the display panel 830 has a high frame rate (e.g., 120 Hz), and the low frame rate area 834 of the display panel 830 has a low frame rate (e.g., 80 Hz).)
Consider claim 13, where Chien discloses the display apparatus of claim 1, wherein the first gate lines of the first screen block and the second gate lines of the second screen block are electrically disconnected from each other. (See Chien Fig. 8 and ¶48 where the scan lines in the left half are not electrically connected to the scan lines in the right half.)
Consider claim 16, where Chien discloses a display apparatus comprising: a display panel including a first screen block and a second screen block; (See Chien Fig. 8 and ¶48 where the gate driver 821 is disposed on the left side of the display panel 830) a first gate driving circuit configured to supply a scan output to first gate lines of the first screen block; (See Chien Fig. 8 and ¶48 where the gate driver 822 is arranged on the right side of the display panel 830.) and a second gate driving circuit configured to supply a scan output to second gate lines of the second screen block, wherein the first screen block and the second screen block are driven by the first gate driving circuit and the second gate driving circuit at independent data refresh rates. (See Chien Fig. 8 and ¶49-50 where based on the control of the control device 810 on the gate driver 821, the high frame rate area 831 of the display panel 830 has a high frame rate (e.g., 120 Hz), and the low frame rate area 832 of the display panel 830 has a low frame rate (e.g., 40 Hz). Based on the control of the control device 810 on the gate driver 822, the high frame rate area 833 of the display panel 830 has a high frame rate (e.g., 120 Hz), and the low frame rate area 834 of the display panel 830 has a low frame rate (e.g., 80 Hz).))
Consider claim 18, where Chien discloses a driving method of a display apparatus including a first screen block and a second screen block, (See Chien Fig. 8 and ¶48 where In the embodiment shown in FIG. 8, the display panel 830 is divided into a left half and a right half.) the driving method comprising: supplying a scan output to first gate lines of the first screen block; (See Chien Fig. 8 and ¶48 where the gate driver 821 is disposed on the left side of the display panel 830) and supplying a scan output to second gate lines of the second screen block, (See Chien Fig. 8 and ¶48 where the gate driver 822 is arranged on the right side of the display panel 830.) wherein the first screen block comprises a first high frequency region where first image data is updated at a first data refresh rate, and a first low frequency region where second image data is updated at a second data refresh rate which is less than the first data refresh rate, (See Chien Fig. 8 and ¶49 where based on the control of the control device 810 on the gate driver 821, the high frame rate area 831 of the display panel 830 has a high frame rate (e.g., 120 Hz), and the low frame rate area 832 of the display panel 830 has a low frame rate (e.g., 40 Hz).) and wherein the second screen block comprises a second high frequency region where third image data is updated at a third data refresh rate, and a second low frequency region where fourth image data is updated at a fourth data refresh rate which is less than the third data refresh rate. (See Chien Fig. 8 and ¶50 where based on the control of the control device 810 on the gate driver 822, the high frame rate area 833 of the display panel 830 has a high frame rate (e.g., 120 Hz), and the low frame rate area 834 of the display panel 830 has a low frame rate (e.g., 80 Hz).)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien in view of Choi et al. (US2023/0029925)
Consider claim 2, where Chien discloses the display apparatus of claim 1, wherein, in a same frame, a scan output timing corresponding to gate lines of the high frequency region is earlier than a scan output timing corresponding to gate lines of the low frequency region, (See Chien Fig. 4 and ¶42 where Based on the vertical start pulse STV and the gate clock signals GCK1˜GCK4, the gate driver 120 and the source driver 112 may completely refresh the high frame rate area (first partition) and the low frame rate area (second partition). Note that the high frame rate area is driven earlier in the frame than the low frame rate area.)
Chien teaches and a scan output timing corresponding to gate lines of the high frequency region is earlier than a scan output timing corresponding to gate lines of the low frequency region. However, Chien does not explicitly teach applying to the first and second regions. However, in an analogous field of endeavor Choi teaches first and second regions. (See Choi Fig. 3, 7 and ¶54 where As can be seen in FIG. 7, some pixel rows of the display panel active area 710 are driven using the first set of clock signals from the first clock distribution circuit 750b1, e.g., from the left side of the display panel active area 710, and driven using the second set of clock signals from the clock distribution circuit 750c2, e.g., from the right side of the display panel active area 710, which creates a horizontally blended region with some pixel rows being driven from one end using one clock signal set, and driven from the other end using another clock signal set.) Therefore, it would have been obvious for one of ordinary skill in the art that the clocks disclosed in Chien can be applied to gate driver 821 and gate driver 822 such that the other end is driven in a similar manner as taught by Choi. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using conventional sequential driving that is common in the art. (See Choi ¶53)
Consider claim 19, where Chien discloses the driving method of claim 18, wherein, in a same frame, a scan output timing corresponding to gate lines of the high frequency region is earlier than a scan output timing corresponding to gate lines of the low frequency region, (See Chien Fig. 4 and ¶42 where Based on the vertical start pulse STV and the gate clock signals GCK1˜GCK4, the gate driver 120 and the source driver 112 may completely refresh the high frame rate area (first partition) and the low frame rate area (second partition). Note that the high frame rate area is driven earlier in the frame than the low frame rate area.)
Chien teaches and a scan output timing corresponding to gate lines of the high frequency region is earlier than a scan output timing corresponding to gate lines of the low frequency region. However, Chien does not explicitly teach applying to the first and second regions. However, in an analogous field of endeavor Choi teaches first and second regions. (See Choi Fig. 3, 7 and ¶54 where As can be seen in FIG. 7, some pixel rows of the display panel active area 710 are driven using the first set of clock signals from the first clock distribution circuit 750b1, e.g., from the left side of the display panel active area 710, and driven using the second set of clock signals from the clock distribution circuit 750c2, e.g., from the right side of the display panel active area 710, which creates a horizontally blended region with some pixel rows being driven from one end using one clock signal set, and driven from the other end using another clock signal set.) Therefore, it would have been obvious for one of ordinary skill in the art that the clocks disclosed in Chien can be applied to gate driver 821 and gate driver 822 such that the other end is driven in a similar manner as taught by Choi. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using conventional sequential driving that is common in the art. (See Choi ¶53)
Claim(s) 3, 12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien in view of Choi as applied to claim 2 above, in further view of Yoon et al. (US2021/0027697)
Consider claim 3, where Chien in view of Choi teaches the display apparatus of claim 2, wherein, in a predetermined time, a number of scan output maskings on the gate lines of the first low frequency region is more than a number of scan output maskings on the gate lines of the first high frequency region, and a number of scan output maskings on the gate lines of the second low frequency region is more than a number of scan output maskings on the gate lines of the second high frequency region. (See Chien Fig. 4 and ¶35 where Thus, the first partition (high frame rate area) of the display panel 130 may be refreshed in each second selected frame. After the extra reset pulse occurs, the scanning pulse in the gate driver 120 has been cleared, so that the gate driver 120 does not scan the scan lines in the second partition (low frame rate area) of the display panel 130. Thus, based on the extra reset pulse, the second partition of the display panel 130 are not refreshed in each second selected frame, so that the frame rate (refresh rate) of the second partition of the display panel 130 may be different from the first partition of the display panel 130. Thus, the scan output is masked at t2 such that no refresh data is applied during that time period)
Chien teaches not applying the clock signals in the second half, however Chien does not explicitly state the term “masking” However, in an analogous field of endeavor Yoon teaches masking. (See Yoon Figs. 10, 11, and ¶190-195 where the timing controller 140 (see FIG. 1) may mask the clock signals CLK1 and CLK2 three times during a frame section.) Thus, it would be obvious to one of ordinary skill in the art that the non-application of the clock signals in the second frame of Chien would qualify as masking as taught by Yoon.
Consider claim 12, where Chien discloses the display apparatus of claim 1, further comprising a clock masking control circuit configured to: generate a first control signal corresponding to a scan output masking timing of the first high frequency region and a second control signal corresponding to a scan output masking timing of the first low frequency region, based on first image data to be input to the first screen block, and generate a third control signal corresponding to a scan output masking timing of the second high frequency region and a fourth control signal corresponding to a scan output masking timing of the second low frequency region, based on second image data to be input to the second screen block. (See Chien Fig. 4 and ¶35 where Thus, the first partition (high frame rate area) of the display panel 130 may be refreshed in each second selected frame. After the extra reset pulse occurs, the scanning pulse in the gate driver 120 has been cleared, so that the gate driver 120 does not scan the scan lines in the second partition (low frame rate area) of the display panel 130. Thus, based on the extra reset pulse, the second partition of the display panel 130 are not refreshed in each second selected frame, so that the frame rate (refresh rate) of the second partition of the display panel 130 may be different from the first partition of the display panel 130. Thus, the scan output is masked at t2 such that no refresh data is applied during that time period)
Chien teaches not applying the clock signals in the second half, however Chien does not explicitly state the term “masking” However, in an analogous field of endeavor Yoon teaches masking. (See Yoon Figs. 10, 11, and ¶190-195 where the timing controller 140 (see FIG. 1) may mask the clock signals CLK1 and CLK2 three times during a frame section.) Thus, it would be obvious to one of ordinary skill in the art that the non-application of the clock signals in the second frame of Chien would qualify as masking as taught by Yoon.
Consider claim 20, where Chien in view of Choi teaches the driving method of claim 19, wherein, in a predetermined time, a number of scan output maskings on the gate lines of the first low frequency region is more than a number of scan output maskings on the gate lines of the first high frequency region, and a number of scan output maskings on the gate lines of the second low frequency region is more than a number of scan output maskings on the gate lines of the second high frequency region. (See Chien Fig. 4 and ¶35 where Thus, the first partition (high frame rate area) of the display panel 130 may be refreshed in each second selected frame. After the extra reset pulse occurs, the scanning pulse in the gate driver 120 has been cleared, so that the gate driver 120 does not scan the scan lines in the second partition (low frame rate area) of the display panel 130. Thus, based on the extra reset pulse, the second partition of the display panel 130 are not refreshed in each second selected frame, so that the frame rate (refresh rate) of the second partition of the display panel 130 may be different from the first partition of the display panel 130. Thus, the scan output is masked at t2 such that no refresh data is applied during that time period)
Chien teaches not applying the clock signals in the second half, however Chien does not explicitly state the term “masking” However, in an analogous field of endeavor Yoon teaches masking. (See Yoon Figs. 10, 11, and ¶190-195 where the timing controller 140 (see FIG. 1) may mask the clock signals CLK1 and CLK2 three times during a frame section.) Thus, it would be obvious to one of ordinary skill in the art that the non-application of the clock signals in the second frame of Chien would qualify as masking as taught by Yoon.
Claim(s) 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien as applied to claim 1 above, in further view of Kim et al. (US2024/0257765)
Consider claim 4, where Chien discloses the display apparatus of claim 1, where clocks are applied to gate stages, however Chien does not explicitly teach wherein the first gate driving circuit comprises: a (4k-3).sup.th gate stage configured to generate a scan output corresponding to a first odd clock, where k is a positive integer; and a (4k-2).sup.th gate stage configured to generate a scan output corresponding to a second odd clock having a phase which differs from a phase of the first odd clock. However, in an analogous field of endeavor Kim teaches wherein the first gate driving circuit comprises: a (4k-3).sup.th gate stage configured to generate a scan output corresponding to a first odd clock, where k is a positive integer; and a (4k-2).sup.th gate stage configured to generate a scan output corresponding to a second odd clock having a phase which differs from a phase of the first odd clock. (See Kim Figs 6, 9 and ¶164 where In relation to the scan clock SCLK corresponding to each scan stage SS, for example, an odd scan clock SCLK_O1 or SCLK_O2 may be input to the odd scan stages (e.g., SS(n+1), SS(n+3), and SS(n+5)). An even scan clock SCLK_E whose phase (or timing) is different from the odd scan clocks SCLK_O1 and SCLK_O2 may be input to the even scan stages (e.g., SS(n), SS(n+2), and SS(n+4)). Thus, the SCLK_O1 is an odd clock applied to the first gate line (4k-3, where k=1) and SCLK_E has a phase difference from SCLK_O1 and is applied to the second gate line(4k-3, where k=2). The Examiner has mapped the even clock to the second odd clock as it is functionally identical to CLK2_O described in Figs. 13B, 13C and ¶121 with a difference in name only.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the clocks GCK1-4 of Chien to match the odd and even clocks of Kim to adjusting a phase timing to better match the operation of the device. Thereby, adjusting a known parameter in the art to suit the intended timing of the gate stages. (See Kim ¶164-165)
Consider claim 8, where Chien discloses the display apparatus of claim 1, where Chien discloses the display apparatus of claim 1, where clocks are applied to gate stages, however Chien does not explicitly teach wherein the second gate driving circuit comprises: a (4k-3).sup.th gate stage configured to generate a scan output corresponding to a first odd clock, where k is a positive integer; and a (4k-2).sup.th gate stage configured to generate a scan output corresponding to a second odd clock having a phase which differs from a phase of the first odd clock. However, in an analogous field of endeavor Kim teaches wherein the second gate driving circuit comprises: a (4k-3).sup.th gate stage configured to generate a scan output corresponding to a first odd clock, where k is a positive integer; and a (4k-2).sup.th gate stage configured to generate a scan output corresponding to a second odd clock having a phase which differs from a phase of the first odd clock. (See Kim Figs 6, 9 and ¶164 where In relation to the scan clock SCLK corresponding to each scan stage SS, for example, an odd scan clock SCLK_O1 or SCLK_O2 may be input to the odd scan stages (e.g., SS(n+1), SS(n+3), and SS(n+5)). An even scan clock SCLK_E whose phase (or timing) is different from the odd scan clocks SCLK_O1 and SCLK_O2 may be input to the even scan stages (e.g., SS(n), SS(n+2), and SS(n+4)). Thus, the SCLK_O1 is an odd clock applied to the first gate line (4k-3, where k=1) and SCLK_E has a phase difference from SCLK_O1 and is applied to the second gate line(4k-3, where k=2). The Examiner has mapped the even clock to the second odd clock as it is functionally identical to CLK2_O described in Figs. 13B, 13C and ¶121 with a difference in name only.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the clocks GCK1-4 of Chien to match the odd and even clocks of Kim to adjusting a phase timing to better match the operation of the device. Thereby, adjusting a known parameter in the art to suit the intended timing of the gate stages. (See Kim ¶164-165)
Claim(s) 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien as applied to claim 1 above, in further view of Zhang et al. (US2018/0286315)
Consider claim 14, where Chien discloses the display apparatus of claim 1, however Chien does not explicitly teach further comprising: a first data driving circuit configured to supply first image data to first data lines of the first screen block; and a second data driving circuit configured to supply second image data to second data lines of the second screen block, wherein the first data lines and the second data lines are electrically disconnected from each other. However, in an analogous field of endeavor Zhang teaches a first data driving circuit configured to supply first image data to first data lines of the first screen block; and a second data driving circuit configured to supply second image data to second data lines of the second screen block, wherein the first data lines and the second data lines are electrically disconnected from each other. (See Zhang Fig. 1 and ¶24-25 where the separate portions of the display are halves, and two sets of gate and source drivers display data on separate halves of the display. That is, gate drivers 106A and source drivers 107A are used to display data on the left side of display screen 115, while gate drivers 106B and source drivers 107B are used to display data on the right side of display screen 115.) Therefore, it would have been obvious for one of ordinary skill in the art that the data supplied to the left and right halves of Chien would be supplied by separate source drivers as taught by Zhang. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using a known method of supplying data to left and right halves of displays to yield the desired result.
Consider claim 17, where Chien discloses the display apparatus of claim 16, however Chien does not explicitly teach further comprising: a first data driving circuit configured to supply first image data to first data lines of the first screen block; and a second data driving circuit configured to supply second image data to second data lines of the second screen block, wherein the first data lines and the second data lines are electrically disconnected from each other. However, in an analogous field of endeavor Zhang teaches a first data driving circuit configured to supply first image data to first data lines of the first screen block; and a second data driving circuit configured to supply second image data to second data lines of the second screen block, wherein the first data lines and the second data lines are electrically disconnected from each other. (See Zhang Fig. 1 and ¶24-25 where the separate portions of the display are halves, and two sets of gate and source drivers display data on separate halves of the display. That is, gate drivers 106A and source drivers 107A are used to display data on the left side of display screen 115, while gate drivers 106B and source drivers 107B are used to display data on the right side of display screen 115.) Therefore, it would have been obvious for one of ordinary skill in the art that the data supplied to the left and right halves of Chien would be supplied by separate source drivers as taught by Zhang. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using a known method of supplying data to left and right halves of displays to yield the desired result.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien as applied to claim 1 above, in further view of Kim et al. (US2022/0068240) (hereinafter referred to as Kim2)
Consider claim 15, where Chien teaches the display apparatus of claim 1, however, Chien does not explicitly teach wherein the first screen block and the second screen block contact each other with a boundary therebetween. However, in an analogous field of endeavor Kim2 teaches wherein the first screen block and the second screen block contact each other with a boundary therebetween. (See Kim2 Fig. 2, 3A and ¶100 where there are boundary areas between left display devices and right display devices) Therefore, it would have been obvious for one of ordinary skill in the art to modify the left-right display of Chien Fig. 8 to have a boundary area as taught by Kim2. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known methods of implementing different screen blocks to yield the intended result.
Allowable Subject Matter
Claim 5-7 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: While one of ordinary skill in the art may work backwards from the claim language to modify the teachings of Chien, Yoon, and Kim to arrive at the limitations of claim 5 and 9, there is insufficient evidence within the references work forward to arrive at the claimed limitation. Thus, the combination is reliant on hindsight reasoning. Thus, claims 5 and 9 are objected to as allowable. Claims 6, 7, 10, and 11 are objected to base upon their dependence on claims 5 and 9.
Conclusion
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WILLIAM LU
Primary Examiner
Art Unit 2624
/WILLIAM LU/Primary Examiner, Art Unit 2624
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