DETAILED ACTION
Claims 1-20 filed October 20th 2025 are pending in the current action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 recites the limitation "the second control circuit" however there is no reference to a second control circuit in claim 1. There is insufficient antecedent basis for this limitation in the claim. The Examiner believes that claim 3 is intended to be dependent from claim 2. For the purposes of the art rejection below, the Examiner will treat claim 3 as dependent upon claim 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-9, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (US2021/0193025) in view of Lai et al. (US2022/0223084)
Consider claim 1, where Xu teaches a driving circuit, (See Xu Figs. 5A-D, 6) comprising a first control circuit and a third control circuit; (See Xu Figs. 5A-D, 6 and ¶149-150, 145 where Xu teaches a transistor T8 and a second node potential control circuit 3) wherein the first control circuit is respectively electrically connected to a second node, a second voltage line and a first node, and is configured to control to connect or disconnect the first node and the second voltage line under the control of a potential of the second node; (See Xu Figs. 5A-D, 6 and ¶149-150 where the gate of the eighth transistor T8 is electrically connected to the first node N1 or the fourth node N4. It should be noted that, comparing with the circuit shown in FIG. 5A, in the circuit shown in FIG. 5E, the gate connection mode of the eighth transistor varies. The manner in which the gate of the eighth transistor T8 is electrically connected to the first node N1 or the fourth node N4 may be applied to FIGS. 5B-5D. In response to that the potential of the first node N1 or the fourth node N4 is at a low level, the eighth transistor T8 is turned on to provide the signal of the second potential signal terminal VGH to the second node N2, and in response to that the first node N1 or the fourth node N4 is at a high potential, the eighth transistor T8 is turned off.) the third control circuit is respectively electrically connected to a seventh node, a sixth node, a first control node a seventh voltage line and a second clock signal line, and is configured to control to connect or disconnect the sixth node and the seventh voltage line under the control of a potential of the first control node, and control to connect or disconnect the sixth node and the second clock signal line under the control of a potential of the seventh node; (See Xu Fig. 6 and ¶144-145 where in some embodiments, as shown in FIGS. 6 and 9, the gate of the fifth transistor T5 is electrically connected to the fifth node N5, and in response to that the fifth node N5 is at a low level, the fifth transistor T5 is turned on and the signal of the second potential signal terminal VGH is provided to the first electrode of the fourth transistor T4; and in response to that the potential of the fifth node N5 is at a high level, the fifth transistor T5 is turned off. The Examiner is mapping the sixth node as the node between T4 and T5) and the second voltage line is configured to provide a high voltage signal VGH; the seventh voltage line is configured to provide the high voltage signal VGH. (See Xu Fig. 6 and ¶143, 149 where a first electrode of the fifth transistor T5 is electrically connected to the second potential signal terminal VGH, and a first electrode of the eighth transistor T8 is electrically connected to the second potential signal terminal VGH)
Xu teaches a high voltage signal VGH, however Xu does not explicitly teach a second voltage signal and a seventh voltage signal. However, in an analogous field of endeavor Lai teaches a second voltage signal and a seventh voltage signal. (See Lai ¶35 where in one embodiment of the present disclosure, the first voltage signal VGH1 and the second voltage signal VGL1 may be provided to the first control unit 10, the second control unit 20, and the third control unit 30 to ensure that the first control unit 10 and the second control unit 20 and the third control unit 30 to work with a normal manner. The third voltage signal V.sub.GH2 and the fourth voltage signal VGL2 may be provided to the fourth control unit 40 to cause the fourth control unit 40 to generate the output signal OUT. Thus, the voltage signal of the fourth control unit 40 and the voltage signals of the first control unit 10, the second control unit 20, and the third control unit 30 may be separately provided.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the pull-up voltage for the output signal of Xu by separately providing the pull-up voltage as taught by Lai. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of improving compatibility with different signals. (See Lai ¶35 where the third voltage signal VGH2 and the fourth voltage signal VGL2 may be changed to change the voltage of the output signal OUT such that the voltage of the output signal OUT of the shift register may meet the different voltage requirements of the pixel circuits for different signals. Thus, the flexibility of the voltage of the output signal OUT of the driving circuit 11 may be improved.)
Consider claim 4, where Xu in view of Lai teaches the driving circuit according to claim 1, wherein the first control circuit comprises a first transistor; a gate electrode of the first transistor is electrically connected to the second node, a first electrode of the first transistor is electrically connected to the second voltage line, and a second electrode of the first transistor is electrically connected to the first node; and the second voltage line is a second high voltage line. (See Xu Fig. 6 and ¶144-145 where in some embodiments, as shown in FIGS. 6 and 9, the gate of the fifth transistor T5 is electrically connected to the fifth node N5, and in response to that the fifth node N5 is at a low level, the fifth transistor T5 is turned on and the signal of the second potential signal terminal VGH is provided to the first electrode of the fourth transistor T4; and in response to that the potential of the fifth node N5 is at a high level, the fifth transistor T5 is turned off. The Examiner is mapping the sixth node as the node between T4 and T5)
Consider claim 5, where Xu in view of Lai teaches the driving circuit according to claim 1, further comprising a second on-off control circuit; the second on-off control circuit comprises a ninth transistor; and a gate electrode of the ninth transistor is electrically connected to a sixth voltage line, and the sixth voltage line is a first low voltage line. (See Xu Figs. 5A-D, 6 and ¶175 where a gate of the eleventh transistor T11 is electrically connected to the first potential signal terminal VGL, a first electrode of the eleventh transistor T11 is electrically connected to the output terminal of the first node potential control circuit 2, and a second electrode of the eleventh transistor T11 is electrically connected to the control terminal of the first output control circuit 6.)
Consider claim 6, where Xu in view of Lai teaches the driving circuit according to claim 5, further comprising a third node control circuit, the third node control circuit is respectively electrically connected to a first clock signal line, a fourth voltage line and a third node, and is configured to control to connect or disconnect the third node and the fourth voltage line under the control of a first clock signal provided by the first clock signal line; and the fourth voltage line is configured to provide a fourth voltage signal. (See Xu Figs. 5A-D, 6 and ¶91 where the first node potential control circuit 2 is configured to provide a first potential signal of a first potential signal terminal VGL to an input terminal of the first isolation circuit 4 under control of the signal of the first clock signal terminal CK, and provide a first clock signal of the first clock signal terminal potential CK to the input terminal of the first isolation circuit 4 under control of the signal of the input terminal of the second isolation circuit 5.)
Consider claim 7, where Xu in view of Lai teaches the driving circuit according to claim 6, wherein the third node control circuit comprises a third transistor, a first electrode of the third transistor is electrically connected to the fourth voltage line, and the fourth voltage line is a second low voltage line. (See Xu Figs. 5A-D, 6 and ¶91, 135 a gate of the third transistor T3 is electrically connected to the first clock signal terminal CK, a first electrode of the third transistor T3 is electrically connected to the first potential signal terminal VGL, and a second electrode of the third transistor T3 is electrically connected to the input terminal of the first isolation circuit 4.)
Consider claim 8, where Xu in view of Lai teaches the driving circuit according to claim 7, further comprising an output reset circuit; wherein the output reset circuit is respectively electrically connected to the second node, a driving signal terminal and a third voltage line, and is configured to control to connect or disconnect the driving signal terminal and the third voltage line under the control of the potential of the second node; the output reset circuit comprises an output reset transistor, a second electrode of the output reset transistor is connected to the third voltage line; and the third voltage line is the first low voltage line. (See Xu Figs 5A-D, 6 and ¶98, 172 where he second output circuit 10 is configured to provide the signal of the first potential signal terminal VGL to the signal output terminal OUT under control of the potential of the control terminal of the second output circuit 10, where the signal output terminal OUT is electrically connected to the light-emitting control line EM. A gate of the tenth transistor T10 is electrically connected to the output terminal of the second isolation circuit 5, a first electrode of the tenth transistor T10 is electrically connected to the first potential signal terminal VGL, and a second electrode of the tenth transistor T10 is electrically connected to the signal output terminal OUT.)
Consider claim 9, where Xu in view of Lai teaches the driving circuit according to claim 8, wherein a potential of a voltage signal provided by the first low voltage line is different from a potential of a voltage signal provided by the second low voltage line. (See Lai ¶35 where in one embodiment of the present disclosure, the first voltage signal VGH1 and the second voltage signal VGL1 may be provided to the first control unit 10, the second control unit 20, and the third control unit 30 to ensure that the first control unit 10 and the second control unit 20 and the third control unit 30 to work with a normal manner. The third voltage signal V.sub.GH2 and the fourth voltage signal VGL2 may be provided to the fourth control unit 40 to cause the fourth control unit 40 to generate the output signal OUT. Thus, the voltage signal of the fourth control unit 40 and the voltage signals of the first control unit 10, the second control unit 20, and the third control unit 30 may be separately provided.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the pull-up voltage for the output signal of Xu by separately providing the pull-up voltage as taught by Lai. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of improving compatibility with different signals. (See Lai ¶35 where the third voltage signal VGH2 and the fourth voltage signal VGL2 may be changed to change the voltage of the output signal OUT such that the voltage of the output signal OUT of the shift register may meet the different voltage requirements of the pixel circuits for different signals. Thus, the flexibility of the voltage of the output signal OUT of the driving circuit 11 may be improved.)
Consider claim 14, where Xu in view of Lai teaches the driving circuit according to claim 1, further comprising a second node control circuit; the second node control circuit is respectively electrically connected to an input terminal, a first clock signal line and the second node, and is configured to control to connect or disconnect the second node and the input terminal under the control of the first clock signal provided by the first clock signal line. (See Xu Figs. 5A-D, 6 and ¶131-132 where when the first clock signal terminal CK is at a low level, the first transistor T1 is turned on, and the signal of the input signal terminal STV is provided to the fourth node N4; when the first clock signal terminal CK is at a high level, the first transistor T1 is turned off..)
Consider claim 15, where Xu in view of Lai teaches the driving circuit according to claim 14, wherein the second node control circuit comprises an eighth transistor; a gate electrode of the eighth transistor is electrically connected to the first clock signal line, a first electrode of the eighth transistor is electrically connected to the input terminal, and a second electrode of the eighth transistor is electrically connected to the second node. (See Xu Figs. 5A-D, 6 and ¶131 where A gate of the first transistor T1 is electrically connected to the first clock signal terminal CK, and a first electrode of the first transistor T1 is electrically connected to the input signal terminal STV, and a second electrode of the first transistor T1 is electrically connected to the input terminal of the first isolation circuit 4 and the control terminal of the first node potential control circuit 2.)
Consider claim 16, where Xu teaches a display substrate, (See Xu ¶123) comprising a base substrate and a driving circuit arranged on the base substrate; (See Xu ¶65) wherein the driving circuit comprises (See Xu Figs. 5A-D, 6 and ¶149-150, 145 where Xu teaches a transistor T8 and a second node potential control circuit 3) wherein the first control circuit is respectively electrically connected to a second node, a second voltage line and a first node, and is configured to control to connect or disconnect the first node and the second voltage line under the control of a potential of the second node; (See Xu Figs. 5A-D, 6 and ¶149-150 where the gate of the eighth transistor T8 is electrically connected to the first node N1 or the fourth node N4. It should be noted that, comparing with the circuit shown in FIG. 5A, in the circuit shown in FIG. 5E, the gate connection mode of the eighth transistor varies. The manner in which the gate of the eighth transistor T8 is electrically connected to the first node N1 or the fourth node N4 may be applied to FIGS. 5B-5D. In response to that the potential of the first node N1 or the fourth node N4 is at a low level, the eighth transistor T8 is turned on to provide the signal of the second potential signal terminal VGH to the second node N2, and in response to that the first node N1 or the fourth node N4 is at a high potential, the eighth transistor T8 is turned off.) the third control circuit is respectively electrically connected to a seventh node, a sixth node, a first control node a seventh voltage line and a second clock signal line, and is configured to control to connect or disconnect the sixth node and the seventh voltage line under the control of a potential of the first control node, and control to connect or disconnect the sixth node and the second clock signal line under the control of a potential of the seventh node; (See Xu Fig. 6 and ¶144-145 where in some embodiments, as shown in FIGS. 6 and 9, the gate of the fifth transistor T5 is electrically connected to the fifth node N5, and in response to that the fifth node N5 is at a low level, the fifth transistor T5 is turned on and the signal of the second potential signal terminal VGH is provided to the first electrode of the fourth transistor T4; and in response to that the potential of the fifth node N5 is at a high level, the fifth transistor T5 is turned off. The Examiner is mapping the sixth node as the node between T4 and T5) and the second voltage line is configured to provide a high voltage signal VGH; the seventh voltage line is configured to provide the high voltage signal VGH. (See Xu Fig. 6 and ¶143, 149 where a first electrode of the fifth transistor T5 is electrically connected to the second potential signal terminal VGH, and a first electrode of the eighth transistor T8 is electrically connected to the second potential signal terminal VGH)
Xu teaches a high voltage signal VGH, however Xu does not explicitly teach a second voltage signal and a seventh voltage signal. However, in an analogous field of endeavor Lai teaches a second voltage signal and a seventh voltage signal. (See Lai ¶35 where in one embodiment of the present disclosure, the first voltage signal VGH1 and the second voltage signal VGL1 may be provided to the first control unit 10, the second control unit 20, and the third control unit 30 to ensure that the first control unit 10 and the second control unit 20 and the third control unit 30 to work with a normal manner. The third voltage signal V.sub.GH2 and the fourth voltage signal VGL2 may be provided to the fourth control unit 40 to cause the fourth control unit 40 to generate the output signal OUT. Thus, the voltage signal of the fourth control unit 40 and the voltage signals of the first control unit 10, the second control unit 20, and the third control unit 30 may be separately provided.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the pull-up voltage for the output signal of Xu by separately providing the pull-up voltage as taught by Lai. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of improving compatibility with different signals. (See Lai ¶35 where the third voltage signal VGH2 and the fourth voltage signal VGL2 may be changed to change the voltage of the output signal OUT such that the voltage of the output signal OUT of the shift register may meet the different voltage requirements of the pixel circuits for different signals. Thus, the flexibility of the voltage of the output signal OUT of the driving circuit 11 may be improved.)
Claim(s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Lai as applied to claim 1 above, and further in view of Hu et al. (US2022/0036790)
Consider claim 2, where Xu in view of Lai teaches the driving circuit according to claim 1, however, they do not explicitly teach further comprising a second control circuit; the second control circuit is respectively electrically connected to a control signal line, the second voltage line and the second node, and is configured to control to connect or disconnect the second node and the second voltage line under the control of a control signal provided by the control signal line. However, in an analogous field of endeavor Hu teaches a second control circuit; the second control circuit is respectively electrically connected to a control signal line, the second voltage line and the second node, and is configured to control to connect or disconnect the second node and the second voltage line under the control of a control signal provided by the control signal line. (See Hu Fig. 3 and ¶43 where the first reset unit 151 is electrically connected to the reset control signal input terminal CTRL, the first potential signal input terminal VGH and the first node N1, and when the first reset unit 151 is on, the signal input from the first potential signal input terminal VGH is transmitted to the first node N1. The Examiner notes that N2 is also connected to VGH via the first light emitting output unit 121) Therefore, it would have been obvious for one of ordinary skill in the art to modify the circuit of Xu by adding a reset circuit as taught by Hu. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of providing additional stability and accuracy to the circuit. (See Hu ¶49, 65 where the reset module 150 is divided into the first reset unit 151 and the second reset unit 152, so that the scanning signal and the light emitting control signal output by the scanning circuit can be more effectively controlled, and the scanning signal and the light emitting control signal output from the scanning circuit can be more stable and accurate.)
Consider claim 3, where Xu in view of Lai in view of Hu teaches the driving circuit according to claim 1, wherein the second control circuit comprises a second transistor; a gate electrode of the second transistor is electrically connected to the control signal line, a first electrode of the second transistor is electrically connected to the second voltage line, and a second electrode of the second transistor is electrically connected to the second node. (See Hu Fig. 8 and ¶63 where the first reset unit 151 includes a ninth transistor T9, and the second reset unit 152 includes a tenth transistor T10. A gate of the ninth transistor T9 is electrically connected to the reset control signal input terminal CTRL, a first pole of the ninth transistor T9 is electrically connected to the first potential signal input terminal VGH, and a second pole of the ninth transistor T9 is electrically connected to the first node N1.)
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Lai as applied to claim 1 above, and further in view of Zhang et al. (US2022/0375411)
Consider claim 10, where Xu in view of Lai teaches the driving circuit according to claim 1, however they do not explicitly teach wherein the third control circuit further comprises a thirteenth transistor; and a gate electrode of the thirteenth transistor is electrically connected to an eighth voltage line. However, in an analogous field of endeavor Zhang teaches wherein the third control circuit further comprises a thirteenth transistor; and a gate electrode of the thirteenth transistor is electrically connected to an eighth voltage line. (See Zhang Fig. 14 and ¶104 where the fifth transistor M5 may be in conduction in response to the conduction level of the second node N2, and the second cut-off level signal outputted from the second cut-off level voltage terminal VGH2 may be transmitted to the third node N3 via the fourth transistor M4 and the fifth transistor M5. The eighth transistor M8 may be in conduction in response to the conduction level of the conduction level voltage terminal VGL, and transmit the second cut-off level signal of the third node N3 to the first node N1.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the control circuit of Xu to include such a transistor for the advantage of/ benefit of transmitting improving circuit stability (See Zhang ¶84 where the voltage difference between the gate electrode and the drain electrode or the gate electrode and the source electrode of the transistor connected to the first terminal of the eighth transistor M8 may be reduced to improve the circuit stability.)
Consider claim 11, where Xu in view of Lai in view of Zhang teaches the driving circuit according to claim 10, further comprising a first on-off control circuit; wherein a control terminal of the first on-off control circuit is electrically connected to a fifth voltage line, the first on-off control circuit is configured to control to connect or disconnect the first control node and a third node under the control of a fifth voltage signal provided by the fifth voltage line; (See Xu Fig. 6 and ¶91-94 where the first node potential control circuit 2 is configured to provide a first potential signal of a first potential signal terminal VGL to an input terminal of the first isolation circuit 4 under control of the signal of the first clock signal terminal CK, and provide a first clock signal of the first clock signal terminal potential CK to the input terminal of the first isolation circuit 4 under control of the signal of the input terminal of the second isolation circuit 5.) and the first on-off control circuit comprises a seventh transistor, and a gate electrode of the seventh transistor is electrically connected to the fifth voltage line. (See Xu Fig. 6 and ¶179 where A gate of the twelfth transistor T12 is electrically connected to the first potential signal terminal VGL, a first electrode of the twelfth transistor T12 is electrically connected to the output terminal of the input circuit 1, and a second electrode of the twelfth transistor T12 is electrically connected to the control terminal of the second output circuit 10.)
Consider claim 12, where Xu in view of Lai teaches the driving circuit according to claim 11, wherein the eighth voltage line is a first low voltage line, and the fifth voltage line is the first low voltage line. (See Lai ¶35 where in one embodiment of the present disclosure, the first voltage signal VGH1 and the second voltage signal VGL1 may be provided to the first control unit 10, the second control unit 20, and the third control unit 30 to ensure that the first control unit 10 and the second control unit 20 and the third control unit 30 to work with a normal manner. The third voltage signal V.sub.GH2 and the fourth voltage signal VGL2 may be provided to the fourth control unit 40 to cause the fourth control unit 40 to generate the output signal OUT. Thus, the voltage signal of the fourth control unit 40 and the voltage signals of the first control unit 10, the second control unit 20, and the third control unit 30 may be separately provided.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the pull-up voltage for the output signal of Xu by separately providing the pull-up voltage as taught by Lai. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of improving compatibility with different signals. (See Lai ¶35 where the third voltage signal VGH2 and the fourth voltage signal VGL2 may be changed to change the voltage of the output signal OUT such that the voltage of the output signal OUT of the shift register may meet the different voltage requirements of the pixel circuits for different signals. Thus, the flexibility of the voltage of the output signal OUT of the driving circuit 11 may be improved.)
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Lai as applied to claim 1 above, and further in view of Peng et al. (US20170193960)
Consider claim 13, where Xu in view of Lai teaches the driving circuit according to claim 1, further comprising an output circuit; wherein the output circuit comprises an output transistor; a gate electrode of the output transistor is electrically connected to the first node, a first electrode of the output transistor is electrically connected to a first voltage line, and a second electrode of the output transistor is electrically connected to a driving signal terminal; the first voltage line is configured to provide a first voltage signal, and a potential of the first voltage signal is different from a potential of the second voltage signal. (See Xu Figs. 5A-D and 170 where the first output circuit 9 comprises a transistor T9 where the gate is connected to N2 and a first electrode is connected to VGH and a second electrode is connected to OUT)
Xu teaches a transistor; however Xu does not explicitly teach a width-to-length ratio of the
output transistor is less than a width-to-length ratio threshold; the width-to-length ratio threshold is
greater than or equal to 34 and less than or equal to 45. However, in an analogous field of endeavor
Peng teaches using a width-to-length ratio of 10:1. (See Peng 142 where both the fifth transistor and
the sixth transistor have a width-to-length ratio of 40:1, and the third, eighth and ninth transistors all
have a width-to-length ratio of 10:1) Therefore, it would be obvious to one of ordinary skill in the art
that using the width-to-length ratio of Peng would fall within the claimed operable range. One of
ordinary skill in the art would have been motivated to perform the modification for the advantage of/
benefit of using known ranges in the art to yield predictable results.
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance: The Examiner was referring to Fig. 16 of the applicant’s invention to map the transistors in claim 17. While Xu, Lai and Zhang teaches the various elements of the claim limitations. It would not have been obvious to arrange the elements in the manner outlined by claim 17. Claims 18-20 are allowed based upon their dependence from claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM LU whose telephone number is (571)270-1809. The examiner can normally be reached 10am-6:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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WILLIAM LU
Primary Examiner
Art Unit 2624
/WILLIAM LU/Primary Examiner, Art Unit 2624
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