DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements filed on 10/21/2025 and 06/19/2026 have been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2 and 4-6 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,2, 5, and 7 of U.S. Patent No. 12,646,481. Although the claims at issue are not identical, they are not patentably distinct from each other because claims of the present application are anticipated by claims of the US Patent No. 12,646,481.
The present application
US Patent No. 12,646,481
Claim 1: A source driver for a display unit, the source driver comprising:
a receiver terminal that receives an analog electromagnetic signal over an electromagnetic pathway that includes a series of analog levels representing a video stream;
a collector arranged to collect alternately said series of analog levels as analog video samples into a first storage array or into a second storage array, and
to output said collected analog video samples from said first storage array or from said second storage array in parallel; and
a plurality of column drivers arranged to receive alternately analog video samples from said first storage array while said collector collects into said second storage array and to receive analog video samples from said second storage array while said collector collects into said first storage array, each of said column drivers arranged to receive one of said analog video samples from said collector, said each column driver being further arranged to amplify said one of said analog video samples and to drive said one of said amplified analog video samples onto a column of a display panel of said display unit.
Claim 1: A video display unit comprising: a display panel;
a transmitter within said display unit arranged to receive a stream of digital video samples, to distribute said digital video samples into a plurality of input vectors, to convert each of said input vectors of digital video samples into a sequence of analog levels, and to transmit said sequences of analog levels to said display panel; and a plurality of source drivers,
each of said source drivers being arranged to receive one of said sequences of analog levels over a transmission medium from said transmitter and wherein each of said source drivers include a collector arranged to collect alternately said sequence of analog levels as analog video samples into a first storage array or into a second storage array, and
to output said analog video samples in parallel onto columns of said display panel, and
a plurality of column drivers arranged to receive said analog video samples in parallel from said collector, and to amplify each of said analog video samples onto said columns of said display panel, wherein said column drivers alternately receive analog video samples from said first storage array while said collector collects into said second storage array and receive analog video samples from said second storage array while said collector collects into said first storage array.
Claim 2
Claim 1
Claim 4
Claim 2
Claim 5
Claim 7
Claim 6
Claim 5
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,646,481 in view of Kurokawa et al. (US Pub. 2018/0211620 A1) and Yamazaki et al. (US Pub. 2025/0087145 A1).
Regarding claim 3; claim 1 of the US Patent No. 12,646,481 does not recite “said analog electromagnetic signal originates at a transmitter outside of said display unit, said display unit being an enclosure including said display panel, a frame and associated electronics for producing video images”.
Kurokawa teaches “said analog electromagnetic signal originates at a transmitter outside of said display unit” (Fig.1, the analog image data is transmitted from the AI encoder AIE which is located outside the display unit 11).
It would have been obvious to modify the source driver recited in claim 1 of the US Patent No. 12,646,481 to include the teaching of Kurokawa of providing an AI encoder AIE outside of a display unit for transmitting analog signal to the display unit. The motivation would have been in order to reduce the size of the display device.
Yamazaki teaches “said display unit being an enclosure including said display panel, a frame and associated electronics for producing video images” (Fig.23A, para. [0506], a display unit comprises a housing including an upper cover 6001 and a lower cover 6002, a frame 6009, an a printed circuit board 6010. The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like).
It would have been obvious to one of ordinary skill in the art to modify the display system recited in claim 1 of the US Patent no. 12,646,481 to include the teaching of Yamazaki of providing a display unit comprising a housing, a frame, and a printed circuit board for outputting a video signal. The motivation would have been in order to provide support for the display unit.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7, 10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kurokawa et al. (US Pub. 2018/0211620 A1).
Regarding claim 7; Kurokawa teaches a source driver for a display unit (a source driver SD, Fig.3), the source driver comprising:
[AltContent: textbox (Column driver)][AltContent: arrow][AltContent: rect]
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(Fig.4 of Kurokawa reproduced)
a receiver (a first analog buffer circuit AB1, Fig.4) terminal that receives an analog electromagnetic signal over an electromagnetic pathway that includes a series of analog levels representing a video stream (para. [0116,0131-0133,0116], an analog signal corresponding to image data is transmitted from an image processing portion PP to an AI encoder AIE for performing processing the image data. Then, an AI decoder AID performs processing for restoring feature extracted image data into an original image data and outputs the original image data to the source driver circuit SD. In other words, the source driver circuit would receive an analog signal corresponding to the original image data including a series of analog levels);
a collector including a plurality of sampling amplifiers (Fig.3, a collector comprises a plurality of sample-and-hold circuits SH) each arranged to sample exclusively a portion of said series of analog levels and to write said portion as analog video samples into positions into a first storage array or into a second storage array designated for said each sampling amplifier (Fig.4, para. [0014 and 0137], the sample-and-hold circuit SH is configured to receive the analog signal through the first input terminal when a signal from the shift register is transmitted to the second input terminal and is configured to hold a potential corresponding to the analog signal. The source driver comprises a first demultiplexer DMX1 and a second demultiplexer DMX2 configured to selectively store analog signals into a first sample-and-hold circuit SH[1] or a second sample-and-hold circuit SH[2]), said collector being further arranged to output said sampled analog video samples in parallel (Fig.4);
a plurality of column drivers (Fig.4, a plurality of analog buffer circuits AB2) each arranged to receive one of said analog video samples from said collector (see Fig.4), to amplify said one of said analog video samples and to drive said one of said amplified analog video samples onto a column of a display panel of said display unit (para. [0144], the analog buffer circuit AB2 amplifies the image data transmitted from the sample-and-hold circuit SH); and
control logic circuitry (a plurality of demultiplexers DMX1 and DMX2, Fig.4) arranged to enable each of said sampling amplifiers to sample said portion of said series of analog video samples (para. [0154, 0157, 0158, and 0172-0173], the plurality of demultiplexers DMX1 and DMX2 are synchronously configured to selectively enable the sample-and-hold circuits SH to receive a portion of the analog signal Psig), to enable said sampling amplifiers to write into said first storage array or into said second storage array (para. [0154, 0157, 0158, and 0172-0173], the analog signal Psig are selectively sampled and stored in each sample-and-hold circuit SH in response to a control signal Sig), and to enable said column drivers to receive said analog video samples from said first storage array or from said second storage array (see Fig.4 and para. [0154, 0157, 0158, and 0172-0173]).
Regarding claim 10; Kurokawa teaches the source driver of claim 1 as discussed above. Kurokawa further teaches said source driver does not include any digital-to-analog-converters (DACs) used to convert video samples (Fig.4, the source driver circuit SD2 does not include any digital-to-analog converter).
Regarding claim 12; Kang teaches the source driver of claim 7 as discussed above. Kang further teaches said analog levels arrive at said collector in a predetermined permutation that permits said collector to write said analog video samples into contiguous storage locations in said first storage array or in said second storage array (Fig.4, para. [0154, 0157, 0158, and 0172-0173], the plurality of demultiplexers DMX1 and DMX2 are configured to write the analog signal into odd-numbered sample-and-hold circuits and even-numbered sample-and-hold circuits. Figure 4 shows that the odd-numbered sample-and-hold circuits are associated with a first pixel row and the even-numbered sample-and-hold circuits are associated with a second pixel row. Therefore, the analog signal would be arrived at the sample-and-hold circuits in a predetermined permutation so that the analog signal would be written in the first pixel row, and then the second pixel row).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al. (US Pub. 2018/0211620 A1) in view of Kim et al. (US Pub. 2021/0398470 A1).
Regarding claim 8; Kurokawa teaches the source driver of claim 7 as discussed above. Kurokawa does not teach said analog electromagnetic signal is received from a transmitter within said display unit.
Kim teaches data signal is received from a transmitter within said display unit (Fig.1, para. [0024,0043,0088], a display device 100 comprises a timing controller TCON including a transmitter TX configured to transmit input data to a source driver).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kurokawa to include the teaching of Kim of providing a transmitter within a timing controller for transmitting input data to a source driver. Accordingly, Kurokawa as modified by Kim would render a display device comprising a timing controller including a transmitter for transmitting analog image signal to the source driver circuit. The motivation would have been in order to simplify the manufacturing process.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al. (US Pub. 2018/0211620 A1) in view of Yamazaki et al. (US Pub. 2025/0087145 A1).
Regarding claim 9; Kurokawa teaches the source driver of claim 7 as discussed above. Kurokawa further teaches said analog electromagnetic signal originates at a transmitter outside of said display unit (Fig.1, the analog image data is transmitted from the AI encoder AIE which is located outside the display unit 11).
Kurokawa does not explicitly teach said display unit being an enclosure including said display panel, a frame and associated electronics for producing video images.
Yamazaki teaches said display unit being an enclosure including said display panel, a frame and associated electronics for producing video images (Fig.23A, para. [0506], a display unit comprises a housing including an upper cover 6001 and a lower cover 6002, a frame 6009, an a printed circuit board 6010. The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kurokawa to include the teaching of Yamazaki of providing a display unit comprising a housing, a frame, and a printed circuit board for outputting a video signal. The motivation would have been in order to provide support for the display unit.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al. (US Pub. 2018/0211620 A1) in view of Hobson (US Pub. 2020/0118520 A1).
Regarding claim 11; Kurokawa teaches the source driver of claim 7 as discussed above. Kurokawa does not teach said series of analog levels includes all samples of a first color followed by all samples of a second color of a line of said display panel.
Hobson teaches input data of a first color followed by input data of a second color of a line of said display panel (para. [0012- 0014 and 0030], Hobson discloses a method for field sequential color display of a color image. One frame is divided into three subframes: a red subframe, a green subframe, and a blue subframe (see Fig.1A). In particular, the method comprises displaying a first component image using a first component color, and, separately displaying a second component image using a second component color. In other words, the input data would comprise a first series including all samples of a first color followed by all samples of a second color).
Accordingly, the display system of Kurokawa as modified by Hobson would render a field sequential method of providing a first sequence of all analog signals of a first color followed by a second sequence of all analog signals of a second color. Therefore, the combination of Kurokawa and Hobson further teaches said series of analog levels includes all samples of a first color followed by all samples of a second color of a line of said display panel.
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kurokawa to include the field sequential driving method of Hobson. The motivation would have been in order to reduce color breakup (Hobson, para. [0006]).
Allowable Subject Matter
Claims 13-24 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 13; Kurokawa et al. (US Pub. 2018/0211620 A1) teaches a source driver for a display unit, the source driver comprising: a receiver terminal that receives an analog electromagnetic signal over an electromagnetic pathway that includes a series of analog levels representing a video stream; a collector including a plurality of sampling amplifiers each arranged to sample exclusively a portion of said series of analog levels and to write said exclusive portion as analog video samples into positions in a storage array designated for said each sampling amplifier, said collector being further arranged to output said sampled analog video samples in parallel; and a plurality of column drivers each arranged to receive one of said analog video samples from said collector, to amplify said one of said analog video samples and to drive said one of said amplified analog video samples onto a column of a display panel of said display unit (similar to the analysis of claim 7 above).
However, Kurokawa does not teach that the number of said sampling amplifiers is fewer than the number of said column drivers.
Regarding claim 19; Kurokawa et al. (US Pub. 2018/0211620 A1) teaches a source driver for a display unit (a source driver circuit SD/SD1, Figs. 1 and 3), the source driver comprising:
a receiver terminal (a first analog buffer circuit AB1, Fig.3) that receives an analog electromagnetic signal over an electromagnetic pathway that includes a series of analog levels representing a video stream (para. [0116,0131-0133,0116], an analog signal corresponding to image data is transmitted from an image processing portion PP to an AI encoder AIE for performing processing the image data. Then, an AI decoder AID performs processing for restoring feature extracted image data into an original image data and outputs the original image data to the source driver circuit SD. In other words, the source driver circuit would receive an analog signal corresponding to the original image data including a series of analog levels), wherein said analog electromagnetic signal includes control signals used for synchronization (Fig.1, the image processing portion PP further transmits control signals to a timing controller TC for controlling a gate driver circuit GD and the source driver circuit SD. Para. [0121], Fig.3, the shift register SR is configured to generate signals to control a plurality of sample and hold circuits SH in response to a start pulse SP and clock signals CLK. Therefore, the analog signal received at the image processing portion PP would include control signals which are transmitted to the timing controller TC);
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(Fig.3 of Kurokawa reproduced)
a collector including a plurality of sampling amplifiers (Fig.3, a collector comprises a plurality of sample-and-hold circuits SH) each arranged to sample exclusively a portion of said series of analog levels (Fig.3, para. [0014 and 0137], the sample-and-hold circuit SH is configured to receive the analog signal through the first input terminal when a signal from the shift register is transmitted to the second input terminal and is configured to hold a potential corresponding to the analog signal) and to write said exclusive portion as analog video samples into positions in a storage array designated for said each sampling amplifier (Fig.3, the analog signal is stored in a capacitor C in each sample-and-hold circuit SH), said collector being further arranged to output said sampled analog video samples in parallel (see Fig.3), and
a plurality of column drivers each arranged to receive one of said analog video samples from said collector (see Fig.3 reproduced above, a plurality of column drivers configured to receive respective analog video sample), to amplify said one of said analog video samples and to drive said one of said amplified analog video samples onto a column of a display panel of said display unit (Fig.3, para. [0144 and 0176], the column driver comprises an analog buffer circuit AB2 configured to amplify the analog signal); and wherein said control signals used for synchronization are not driven into said columns of said display panel (Fig.3, the start pulse SP and clock signals CLK are used to control the shift register SR. The start pulse SP and clock signal CLK are not driven into the column drivers).
However, Kurokawa does not teach a control sampling amplifier dedicated to sampling said control signals.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (US Patent No. 6,166,715) discloses a display driver comprising a sample and hold circuit 240 configured to receive video signal. When a group of N pixel signals have accumulated in the sample and hold circuit 240, the N pixel signals are delivered to one of the n groups in a group block 260 under control of a controller 220. The group block 260 includes n groups in order to re-direct n groups of signals from the sample and hold circuit 240.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
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