Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/12/2026 is being
considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Independent Claim 2 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Although the claims at issue are not identical, they are not patentably distinct from each
other because both of the inventions are about access-permission table for controlling data movement accessing memory from multiple requestors.
Claim 2 of instant application
Claim 1 of US 12,455,701
An apparatus comprising: a memory to store an access-permissions table comprising a plurality of entries
An apparatus comprising: a memory to store an Inter-Domain Permissions Table (IDPT) having a plurality of entries
each entry corresponding to a target address space for data movement operations and having an authorization field usable to identify one or more requester identities authorized by the entry
wherein a single entry of the IDPT is to provide a relationship between u an access address space identifier and a plurality of submitter address space identifiers
and a data-movement accelerator coupled to the memory and configured, when processing a descriptor submitted from a requester identity,
and a hardware accelerator device to allow access to an access address space, corresponding to the access address space identifier, by one or more submitters,
determine an entry of the access-permissions table based on a handle in the descriptor,
corresponding to the plurality of requester submitter address space identifiers, respectively, based at least in part on the relationship provided by the single entry of the IDPT
validate, based on the authorization field associated with the entry, whether the requester identity is authorized by the entry, and perform direct memory access to the target address space when the validation succeeds
wherein allowing the access comprises finding the single entry within the IDPT, the single entry being capable of identifying the plurality of submitter address space identifiers including submitter address space identifiers that correspond to the one or more submitters
The limitation of claim 2 of instant application has been broadened without specifically mentioning “Inter-Domain Permissions”. Other limitations of instant application is also taught in US 12,455,701 in much broader way essentially executing same feature. The limitation of claim 2 of instant application “data-movement accelerator coupled to the memory” is taught in claim 10 of US 12,455,701 “hardware accelerator device and/or the memory”.
Claim 3 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Claim 3 of instant application
Claim 3 of US 12,455,701
The apparatus of claim 2, wherein the authorization field comprises a bitmap memory region indexed by requester identity
The apparatus of claim 1, wherein the single entry of the IDPT is to store an identifier bitmap address
Claim 3 of the instant application is dependent on Claims 2, therefore teaches all
limitations of Claims 2. Claim 3 of US 12,455,701 is dependent on Claim 1, therefore
teaches all limitations of Claim 1.
Claim 4 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Claim 4 of instant application
Claim 2 of US 12,455,701
The apparatus of claim 2, wherein the authorization field comprises a single field usable to determine a requester identity
The apparatus of claim 1, wherein each of the access address space identifiers and the plurality of submitter address space identifiers is one of: a node identifier, machine identifier, network identifier, virtual-machine identifier, or a Process Address Space Identifier (PASID)
Claim 4 of the instant application is dependent on Claims 2, therefore teaches all
limitations of Claims 2. Claim 2 of US 12,455,701 is dependent on Claim 1, therefore
teaches all limitations of Claim 1.
Claim 5 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Claim 5 of instant application
Claim 4 of US 12,455,701
The apparatus of claim 2, wherein the authorization field is associated with a data structure to store access control information associated with a plurality of requester identities
The apparatus of claim 3, wherein the identifier bitmap address is to point to an access control bitmap, wherein each bit in the access control bitmap is to indicate whether a submitter corresponding to that bit is allowed to use a corresponding IDPT entry
Claim 5 of the instant application is dependent on Claims 2, therefore teaches all
limitations of Claims 2. Claim 4 of US 12,455,701 is dependent on Claim 3 and 1, therefore teaches all limitations of Claim 1.
Claim 6 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Claim 6 of instant application
Claim 5 of US 12,455,701
The apparatus of claim 2, wherein the target address space is defined by at least one of: a base address and a window size
The apparatus of claim 1, wherein the single entry of the IDPT is to store one or more of: an identifier bitmap address, a window size, a window base, the access address space identifier, one or more of the plurality of submitter address space identifiers, a type identifier, a valid status identifier, one or more control fields, and one or more access permissions
Claim 6 of the instant application is dependent on Claims 2, therefore teaches all
limitations of Claims 2. Claim 5 of US 12,455,701 is dependent on Claim 1, therefore teaches all limitations of Claim 1.
Claim 7 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Claim 7 of instant application
Claim 2 of US 12,455,701
The apparatus of claim 2, wherein at least one of the one or more requester identities is associated with at least one of: a node identifier, a machine identifier, a network identifier, a virtual-machine identifier, or a process address space identifier (PASID)
The apparatus of claim 1, wherein each of the access address space identifiers and the plurality of submitter address space identifiers is one of: a node identifier, machine identifier, network identifier, virtual-machine identifier, or a Process Address Space Identifier (PASID)
Claim 7 of the instant application is dependent on Claims 2, therefore teaches all
limitations of Claims 2. Claim 2 of US 12,455,701 is dependent on Claim 1, therefore teaches all limitations of Claim 1.
Claim 8 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Claim 8 of instant application
Claim 7 of US 12,455,701
The apparatus of claim 3, wherein the bitmap memory region comprises a contiguous virtual address range mapped through an input/output memory management unit (IOMMU) to discontiguous physical pages in system memory
The apparatus of claim 6, wherein system software is to manage one of allocation and configuration of the virtual memory range bitmap, wherein the system software is to utilize a sparse memory mapping to support physical memory mapping for actively used portions of the virtual memory range bitmap
Claim 8 of the instant application is dependent on Claims 3 and 2, therefore teaches all
limitations of Claims 2. Claim 7 of US 12,455,701 is dependent on Claim 6 and 1, therefore teaches all limitations of Claim 1.
Claim 9 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 1 of U.S. Patent No. 12,455,701.
Claim 9 of instant application
Claim 9 of US 12,455,701
The apparatus of claim 2, wherein the memory further stores page tables to resolve address translation for cross-address-space direct memory access (DMA) to the target address space via an IOMMU or system translation lookaside buffers (TLBs)
The apparatus of claim 6, wherein the virtual memory range bitmap is to be mapped through Input/Output Memory Management Unit (IOMMU) page tables
Claim 9 of the instant application is dependent on Claims 2, therefore teaches all
limitations of Claims 2. Claim 9 of US 12,455,701 is dependent on Claim 6 and 1, therefore teaches all limitations of Claim 1.
Independent Claim 11 is rejected on the ground of nonstatutory double patenting
as being unpatentable over independent claim 16 of U.S. Patent No. 12,455,701.
Although the claims at issue are not identical, they are not patentably distinct from each
other because both of the inventions are about access-permission table for controlling data movement accessing memory from multiple requestors.
Claim 11 of instant application
Claim 16 of US 12,455,701
A method comprising: storing, in a memory, an access-permissions table including a plurality of entries
A method comprising: storing in a memory an Inter-Domain Permissions Table (IDPT) having a plurality of entries
each entry corresponding to a target address space for data movement operations and having an authorization field usable to identify one or more requester identities authorized by the entry
wherein a single entry of the IDPT provides a relationship between a-an access address space identifier and a plurality of submitter address space identifiers
receiving, at a data-movement accelerator, a descriptor referencing the entry and associated with a requester identity,
and allowing access, at a hardware accelerator device, to a-an access address space, corresponding to the access address space identifier, by one or more submitters,
corresponding to the plurality of requester submitter address space identifiers, respectively, based at least in part on the relationship provided by the single entry of the IDPT
validating, based on the authorization field, whether the requester identity is authorized by the entry; and upon successful validation, performing direct memory access between the address space of the requester identity and the target address space
wherein allowing the access comprises finding the single entry within the IDPT, the single entry being capable of identifying the plurality of submitter address space identifiers including submitter address space identifiers that correspond to the one or more submitters
The limitation of claim 11 of instant application has been broadened without specifically mentioning “Inter-Domain Permissions”. Other limitations of instant application is also taught in US 12,455,701 in much broader way essentially executing same feature. The limitation of claim 11 of instant application “data-movement accelerator coupled to the memory” is taught in claim 10 of US 12,455,701 “hardware accelerator device and/or the memory”.
Allowable Subject Matter
Claims 1-9 and 11 are allowed given that the outstanding double
patenting rejection is overcome.
Conclusion
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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