DETAILED ACTION
Reissue
The present reissue application is directed to US 11,798,742 B2 (“742 Patent”). 742 Patent issued on October 24, 2023 with claims 1-12 from application 18/092,496 filed on January 3, 2023, which is a continuation of parent application 17/118,667 filed on December 11, 2020, and claims priority to JP 2019-224654 filed on December 12, 2019.
This application was filed on October 23, 2025. Since this date is after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. Furthermore, the present application is being examined under the first inventor to file provisions of the AIA .
This application presents broadened claims, which are permitted because Applicant filed these claims and demonstrated an intent to broaden within two years of the issue date of 742 Patent.
The most recent amendment was filed on October 23, 2025. The status of the claims is:
Claims 1-12: Original
Claims 13-20: New
This is a first, non-final action.
References and Documents Cited in this Action
Park (US 2015/0124371 A1)
Hayashi (US 2005/0121772 A1)
Kuroda (US 6,370,010 B1)
Kim (US 2019/0259539 A1)
Kimura (JP 2017135239 A)
US 11,600,440 B2
Summary of Rejections and Objections in this Action
Claims 13-20 are rejected under 35 U.S.C. 112(b) as being indefinite.
Claims 1, 2, 4-9, 13, 14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Hayashi and Kuroda.
Claims 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Hayashi and Kuroda as applied to claims 1 and 13 respectively above, and further in view of Kim.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Hayashi and Kuroda as applied to claim 1 above, and further in view of Kimura.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. US 11,600,440 B2.
Summary of the Claims
742 Patent is generally directed to mounting structure of a multilayer ceramic capacitor connected to a substrate. Claims 1 and 13 are the independent claims. Claim 13 is representative:
13. A mounting structure of a multilayer ceramic capacitor comprising:
a substrate; and
a multilayer ceramic capacitor connected to the substrate via a bonding material; wherein
the multilayer ceramic capacitor includes:
a laminate including a plurality of dielectric layers and a plurality of internal electrode layers laminated together, the laminate including a first main surface and a second main surface that oppose each other in a lamination direction, a first side surface and a second side surface that oppose each other in a length direction perpendicular or substantially perpendicular to the lamination direction, and a third side surface and a fourth side surface that oppose each other in a width direction perpendicular or substantially perpendicular to the lamination direction and the length direction; and
external electrodes that are on the first main surface of the laminate and electrically connected to the internal electrode layers;
the laminate further includes a first via conductor, a second via conductor, a third via conductor, and a fourth via conductor that connect the internal electrode layers and the external electrodes, each of the via conductors including a first end surface exposed on the first main surface of the laminate;
the external electrodes include a pair of first external electrodes connected to the respective end surfaces of the first via conductor, a pair of second external electrodes connected to the respective end surfaces of the second via conductor, a pair of third external electrodes connected to the respective end surfaces of the third via conductor, and a pair of fourth external electrodes connected to the respective end surfaces of the fourth via conductor, each of the external electrodes not extending to the side surfaces of the laminate; and
a ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor being about 0.85 or more and about 1 or less.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites “the external electrodes include a pair of first external electrodes connected to the respective end surfaces of the first via conductor, a pair of second external electrodes connected to the respective end surfaces of the second via conductor, a pair of third external electrodes connected to the respective end surfaces of the third via conductor, and a pair of fourth external electrodes connected to the respective end surfaces of the fourth via conductor” in lines 20-25 of the claim. The claim is indefinite because the claim only previously recites “each of the via conductors including a first end surface exposed on the first main surface of the laminate,” not plural end surfaces. In other words, the claim does not recite that each of the first, second, third, and fourth via conductors has more than a first end surface and there is insufficient antecedent basis for “the respective end surfaces” recited in the claim.
Claims 14-20 depend directly or indirectly on claim 13 and are indefinite for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-9, 13, 14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Hayashi and Kuroda.
In the rejections below, independent claims 1 and 13 are discussed together first, then dependent claims.
Regarding independent claim 1, Park discloses a mounting structure of a multilayer ceramic capacitor comprising:
a multilayer ceramic capacitor (Figures 1-3) wherein the multilayer ceramic capacitor includes:
a laminate (i.e., ceramic body 110) including a plurality of dielectric layers 111 and a plurality of internal electrode layers 121 and 122 laminated together (paragraphs [0035]-[0039]), the laminate including a first main surface and a second main surface that oppose each other in a lamination direction, a first side surface and a second side surface that oppose each other in a length direction (i.e., direction “L” in Figure 1) perpendicular or substantially perpendicular to the lamination direction, and a third side surface and a fourth side surface that oppose each other in a width direction (i.e., direction “W” in Figure 1) perpendicular or substantially perpendicular to the lamination direction and the length direction; and
external electrodes (electrodes 131 and 132, wherein multiple elements share reference numbers 131 and 132; paragraph [0033]) that are on the main surfaces of the laminate (i.e., the top and bottom surfaces of the structure shown in Figure 1) and electrically connected to the internal electrode layers;
the laminate further includes a first via conductor, a second via conductor, a third via conductor, and a fourth via conductor (i.e., first to fourth via conductors from “a pair of first via electrodes 141” and “a pair of second via electrodes 142”; paragraph [0033]) that connect the internal electrode layers and the external electrodes, each of the via conductors penetrating the laminate in the lamination direction and including a first end surface exposed on the first main surface of the laminate and a second end surface exposed on the second main surface of the laminate (Figure 3);
the external electrodes (again, electrodes 131 and 132, wherein multiple elements share reference numbers 131 and 132; paragraph [0033]) include a pair of first external electrodes connected to the respective end surfaces of the first via conductor, a pair of second external electrodes connected to the respective end surfaces of the second via conductor, a pair of third external electrodes connected to the respective end surfaces of the third via conductor, and a pair of fourth external electrodes connected to the respective end surfaces of the fourth via conductor, each of the external electrodes not extending to the side surfaces of the laminate (Figures 1 and 2 show four electrodes 131/132 on a first main surface, and the cross-section shown in Figure 3 shows each electrode having a corresponding electrode on the second main surface connected by a corresponding via; paragraphs [0032]-[0038]).
PNG
media_image1.png
646
581
media_image1.png
Greyscale
Similarly, regarding independent claim 13, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Park discloses a mounting structure of a multilayer ceramic capacitor comprising:
a multilayer ceramic capacitor wherein the multilayer ceramic capacitor includes:
a laminate (i.e., ceramic body 110) including a plurality of dielectric layers 111 and a plurality of internal electrode layers 121 and 122 laminated together (paragraphs [0035]-[0039]), the laminate including a first main surface and a second main surface that oppose each other in a lamination direction, a first side surface and a second side surface that oppose each other in a length direction (i.e., direction “L” in Figure 1) perpendicular or substantially perpendicular to the lamination direction, and a third side surface and a fourth side surface that oppose each other in a width direction (i.e., direction “W” in Figure 1) perpendicular or substantially perpendicular to the lamination direction and the length direction; and
external electrodes (electrodes 131 and 132, wherein multiple elements share reference numbers 131 and 132; paragraph [0033]) that are on the first main surface of the laminate (i.e., the top surface of the structure shown in Figures 1) and electrically connected to the internal electrode layers;
the laminate further includes a first via conductor, a second via conductor, a third via
conductor, and a fourth via conductor (i.e., first to fourth via conductors from “a pair of first via electrodes 141” and “a pair of second via electrodes 142”; paragraph [0033]) that connect the internal electrode layers and the external electrodes, each of the via conductors including a first end surface exposed on the first main surface of the laminate (i.e., the top of Figure 3);
the external electrodes (again, electrodes 131 and 132, wherein multiple elements share reference numbers 131 and 132; paragraph [0033]) include a pair of first external electrodes connected to the respective end surfaces of the first via conductor, a pair of second external electrodes connected to the respective end surfaces of the second via conductor, a pair of third external electrodes connected to the respective end surfaces of the third via conductor, and a pair of fourth external electrodes connected to the respective end surfaces of the fourth via conductor, each of the external electrodes not extending to the side surfaces of the laminate (Figures 1 and 2 show four electrodes 131/132 on a first main surface, and the cross-section shown in Figure 3 shows each electrode having a corresponding electrode on the second main surface connected by a corresponding via; paragraphs [0032]-[0038]).
Further regarding claims 1 and 13, Park does not specifically disclose a substrate and that the multilayer ceramic capacitor is connected to the substrate via a bonding material. However, Hayashi teaches a structure that is related to the one disclosed by Park, including a multilayer ceramic capacitor 10 (Figure 8; paragraph [0152]). Hayashi further teaches that the multilayer ceramic capacitor 10 is connected to a substrate 60 via a bonding material (e.g., solder; paragraphs [0153]-[0154]). Regarding claims 1 and 13, it would have been obvious to a person of ordinary skill in the art to connect the multilayer ceramic capacitor disclosed by Park to a substrate via a bonding material as taught by Hayashi in order to advantageously connect the capacitor to other circuit elements.
Further regarding claims 1 and 13, Park discloses that a ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor is slightly less than 1, in that Park shows an exemplary embodiment with width W that is less than (but not much less than) length L (Figures 1 and 2). Park does not specifically disclose that W/L is about 0.85 or more and about 1 or less, but Park does disclose that “a shape and a dimension of the ceramic body 110 and the number of stacked dielectric layers 111 are not limited to those of this exemplary embodiment shown in the accompanying drawings” (paragraph [0036]). Furthermore, Kuroda teaches a structure that is related to the one disclosed by Park, including a multilayer ceramic capacitor (Kuroda, Figures 1-4; column 6, lines 6-12). Kuroda further teaches that the capacitor is square, i.e., the ratio W/L is about 1 (Kuroda, column 7, lines 50-57). Regarding claims 1 and 13, it would have been obvious to a person of ordinary skill in the art to provide a ratio W/L that is about 0.85 or more and about 1 or less as taught by Kuroda, in the structure taught by Park in view of Hayashi, in order to advantageously arrange the electrodes “in a balanced layout to increase the cancellation effect of magnetic flux, compared with a capacitor body having a rectangular shape” which also “further decreases the ESL value” to enable higher frequencies (Kuroda, column 7, lines 50-57 and column 1, lines 36-56). Park also discloses that having a low ESL is desirable to enable higher frequencies (Park, paragraph [0008]).
Regarding claims 2 and 14, in the mounting structure taught by Park in view of Hayashi and Kuroda, Hayashi teaches that the bonding material is solder (Hayashi, paragraphs [0153]-[0154]).
Regarding claims 4 and 16, Park in view of Hayashi and Kuroda teaches a mounting structure as discussed above with regard to claims 1 and 13 but Park is silent with respect to a value of a dimension T in the lamination direction of the multilayer ceramic capacitor. However, it would have been obvious to a person of ordinary skill in the art to provide a dimension T that is about 50 µm or greater and about 110 µm or smaller as an engineering design choice of a particular size of the multilayer ceramic capacitor. The mounting structure taught by Park in view of Hayashi and Kuroda would function similarly; the only difference between the prior art and the claims is a recitation of size. See Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). The claimed differences exist not as a result of an attempt by Applicants to solve an unknown problem but merely amount to the selection of expedients known as design choices to one of ordinary skill in the art.
Regarding claims 5 and 6, Park in view of Hayashi and Kuroda teaches a mounting structure as discussed above with regard to claim 1, including a mounting surface of the laminate that is generally flat (Park, Figures 1-3), but Park is silent with respect to a specific flatness value of a mounting surface of the laminate. However, it would have been obvious to a person of ordinary skill in the art to provide a flatness value, determined as a proportion of a total area of regions of the external electrodes within about 5 μm from a highest point on all of the external electrodes to a total area of the external electrodes, that is about 31 or more (claim 5) or less than about 100 (claim 6). The mounting structure taught by Park in view of Hayashi and Kuroda would function similarly; the only difference between the prior art and the claims is a recitation of a specific flatness value. The selection of a particular flatness value would be a matter of routine optimization of Park’s existing disclosure of a generally flat mounting surface of the laminate (Park, Figures 1-3), with predictable results. The claimed differences exist not as a result of an attempt by Applicants to solve an unknown problem but merely amount to the selection of expedients known as design choices to one of ordinary skill in the art.
Regarding claims 7, 17, and 20, Park in view of Hayashi and Kuroda teaches a mounting structure as discussed above with regard to claims 1, 13, and 16, respectively, and Park further discloses that a distance between adjacent external electrodes on the first main surface of the laminate is about 100 µm or greater (i.e. Park discloses a distance TP between adjacent external electrodes may be “0.4 mm,” or 400 µm; paragraph [0058]).
Regarding claims 8 and 19, in the mounting structure taught by Park in view of Hayashi and Kuroda, Park discloses that the distance between adjacent external electrodes on the first main surface of the laminate is less than about 600 µm (i.e. Park discloses a distance TP between adjacent external electrodes may be “0.4 mm,” or 400 µm; paragraph [0058]).
Regarding claims 9 and 18, Park in view of Hayashi and Kuroda teaches a mounting structure as discussed above with regard to claims 1 and 13 but Park is silent with respect to a diameter of each of the via conductors. However, it would have been obvious to a person of ordinary skill in the art to provide a diameter of each of the via conductors is about 30 µm or greater and about 150 µm or smaller as an engineering design choice of a particular size of the via conductors. The via conductors in the mounting structure taught by Park in view of Hayashi and Kuroda would function similarly; the only difference between the prior art and the claims is a recitation of size. See Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). The claimed differences exist not as a result of an attempt by Applicants to solve an unknown problem but merely amount to the selection of expedients known as design choices to one of ordinary skill in the art.
Claims 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Hayashi and Kuroda as applied to claims 1 and 13 respectively above, and further in view of Kim.
Regarding claims 3 and 15, Park in view of Hayashi and Kuroda teaches a mounting structure as discussed above with regard to claims 1 and 13, including a bonding material as taught by Hayashi (Hayashi, paragraphs [0153]-[0154]). Park in view of Hayashi and Kuroda does not specifically teach that the bonding material is flux. However, Kim teaches a structure that is related to the one taught by Park in view of Hayashi and Kuroda, including a multilayer ceramic capacitor 100 bonded to a board 200 with a bonding material 251 (Figures 1 and 5; paragraphs [0039], [0046], and [0074]-[0075]). Kim further teaches the bonding material is flux (paragraph [0075]). Regarding claims 3 and 15, it would have been obvious to a person of ordinary skill in the art to use flux as taught by Kim in the mounting structure taught by Park in view of Hayashi and Kuroda as an engineering design choice of a known material for effectively bonding the capacitor to additional circuitry. The claimed differences exist not as a result of an attempt by Applicants to solve an unknown problem but merely amount to the selection of expedients known as design choices to one of ordinary skill in the art.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Hayashi and Kuroda as applied to claim 1 above, and further in view of Kimura.
Since Kimura is in Japanese, please refer to the English-language machine translation mailed with this action.
Regarding claim 10, Park in view of Hayashi and Kuroda teaches a mounting structure as discussed above with regard to claim 1, wherein first main surface of the laminate is a mounting surface and the second main surface is a counter surface (e.g., in the mounting structure taught by Park in view of Hayashi and Kuroda, one main surface is a mounting surface bonded to a substrate and the other main surface is the opposite counter surface; see discussion with regard to claim 1). Park in view of Hayashi and Kuroda do not further specifically teach a silane coupling agent layer is on at least the mounting surface among the surfaces of the laminate.
However, Kimura teaches a structure that is related to the one taught by Park in view of Hayashi and Kuroda, including a multilayer ceramic capacitor 10 including laminate 14 (Figure 1). Kimura further teaches a silane coupling agent layer 34 is on at least a surface among the surfaces of the laminate (Abstract). Regarding claim 10, it would have been obvious to a person of ordinary skill in the art to include a silane coupling agent layer as taught by Kimura in the mounting structure taught by Park in view of Hayashi and Kuroda in order to advantageously protect the capacitor from water (see Kimura, “Background-Art” section).
Regarding claim 11, in the mounting structure taught by Park in view of Hayashi, Kuroda, and Kimura, Kimura does not specifically teach that a silane coupling agent concentration on the mounting surface is higher than a silane coupling agent concentration on the counter surface. However, Kimura teaches spraying the silane coupling agent wherever desired on the multilayer ceramic capacitor. It would have been obvious to a person of ordinary skill in the art to provide a silane coupling agent concentration on the mounting surface that is higher than a silane coupling agent concentration on the counter surface, in the mounting structure taught by Park in view of Hayashi, Kuroda, and Kimura, as an engineering design choice of selectively providing water resistance where it is more desirable. The claimed differences exist not as a result of an attempt by Applicants to solve an unknown problem but merely amount to the selection of expedients known as design choices to one of ordinary skill in the art.
Regarding claim 12, in the mounting structure taught by Park in view of Hayashi, Kuroda, and Kimura, Kimura further teaches that the silane coupling agent layer includes a fluorine-based silane coupling agent (see Kimura, “Background-Art” section).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. US 11,600,440 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding independent reissue claims 1 and 13, although the recited elements are not identical to the elements of claim 1 of US 11,600,440 B2, they are not patentably distinct from each other because they are of the same scope of invention with claim 1 of US 11,600,440 B2, anticipating the reissue claims. Reissue claims 1 and 13 and claim 1 of US 11,600,440 B2 are each directed to a multilayer ceramic capacitor comprising essentially similar elements, i.e., a laminate including a plurality of dielectric layers and a plurality of internal electrode layers; and external electrodes connected to the internal electrode layers; the laminate further including first to fourth via conductors penetrating the laminate; the external electrodes including pairs of first to fourth external electrodes; and a ratio of width to length being about 0.85 or more and about 1 or less. Given claim 1 of US 11,600,440 B2, it would have been obvious to create reissue claims 1 and 13 by slightly changing the wording of limitations and/or removing limitations.
Dependent reissue claims 4-12 and 16-20 recite essentially the same limitations as claims 2, 3, 5, 7, 8, 9, 10, 4, 6, 2, 5, 7, 6, and 5 respectively of US 11,600,440 B2 and are also not patentably distinct.
Dependent reissue claims 2, 3, 14, and 15 recite that the bonding material is solder or flux. Although bonding material is not recited in claims of US 11,600,440 B2, solder and flux are well known in the art as bonding materials. Given claim 1 of US 11,600,440 B2, it would have been obvious to create reissue claims 2, 3, 14, and 15 by additionally reciting solder or flux to provide a well-known material to effectively bond the capacitor to a substrate with predictable results.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which this reissue application is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/laws/interview-practice.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to Examiner Christina Leung at telephone number (571) 272-3023; the Examiner’s supervisor, SPE Patricia Engle at (571) 272-6660; or the Central Reexamination Unit at (571) 272-7705.
/CHRISTINA Y. LEUNG/Primary Examiner, Art Unit 3991
Conferees:
/DEANDRA M HUGHES/ Reexamination Specialist, Art Unit 3992
/Patricia L Engle/
SPRS, Art Unit 3992
Prosecution Insights