Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu (US 2019/0362674 A1, hereinafter “Xu”).
As to claim 1, Xu (Fig. 6) discloses a display panel (600), comprising a plurality of data lines (Fig. 2 element DL), a plurality of scan lines 9S1), and a plurality of pixel units arranged in an array (200; Para. 0060), wherein the pixel units are configured to receive scan signals from the scan lines and receive data signals from the data lines under control of the scan signals (Para. 0032), and to perform image display based on the data signals (Para. 0036), wherein
each pixel unit of the plurality of pixel units comprises a driving module (TD), an adjustment module (130), a light-emitting module (150), an initialization module (140), and a preset node (N2),
wherein the driving module (TD) is electrically connected to the adjustment module (130), the light-emitting module (150), the initialization module (140), and the preset node (N2), and
the preset node (N2) is also electrically connected to the adjustment module (130) and the initialization module (140);
the initialization module (140) is configured to initialize the preset node (N2) to control the preset node to be at an initial potential (V3; para. 0035);
the adjustment module (130) is configured to receive a power supply voltage (V1) to charge the preset node to a preset potential (Para. 0052, Vx), to adjust a threshold voltage of a driving switch transistor in the driving module to a preset value (Para. 0051-0052),
the driving module (TD) is configured to drive, based on the data signals, the light-emitting module to emit light (Para. 0054).
As to claim 2, Xu (Fig. 3) discloses the display panel of claim 1, wherein the pixel unit further comprises a first node (N1), a second node (N3), and a third node (N2), the third node is the preset node (N2), and
the driving module comprises a driving switch transistor (TD), wherein a first control end of the driving switch transistor (TD) is electrically connected to the first node (N1), a second control end of the driving switch transistor (TD, back gate) is electrically connected to the third node (N2), a first conductive end of the driving switch transistor (TD) is electrically connected to a power supply voltage end (V1), and a second conductive end of the driving switch transistor is electrically connected to the second node (N3),
when the third node (N2) is at the initial potential (V3; Para. 0046), the driving switch transistor is turned on, and the power supply voltage end is configured to charge the third node to the preset potential (Para. 0052) through the driving switch transistor (TD) and the adjustment module (T3),
thereby controlling the driving switch transistor (TD) to be turned off and adjusting the threshold voltage of the driving switch transistor to the preset value (Para. 0052).
As to claim 16, Xu (Fig. 6) discloses a display device (600), comprising a power supply module (Para. 0037) and a display panel (600) connected to the power supply module (Para. 0037), wherein the power supply module is configured to provide a driving power supply for the display panel to drive the display panel to perform image display (Para. 0031),
wherein the display panel comprises a plurality of data lines (Fig. 2 element DL), a plurality of scan lines 9S1), and a plurality of pixel units arranged in an array (200; Para. 0060), wherein the pixel units are configured to receive scan signals from the scan lines and receive data signals from the data lines under control of the scan signals (Para. 0032), and to perform image display based on the data signals (Para. 0036), wherein
each pixel unit of the plurality of pixel units comprises a driving module (TD), an adjustment module (130), a light-emitting module (150), an initialization module (140), and a preset node (N2),
wherein the driving module (TD) is electrically connected to the adjustment module (130), the light-emitting module (150), the initialization module (140), and the preset node (N2), and
the preset node (N2) is also electrically connected to the adjustment module (130) and the initialization module (140);
the initialization module (140) is configured to initialize the preset node (N2) to control the preset node to be at an initial potential (V3; para. 0035);
the adjustment module (130) is configured to receive a power supply voltage (V1) to charge the preset node to a preset potential (Para. 0052, Vx), to adjust a threshold voltage of a driving switch transistor in the driving module to a preset value (Para. 0051-0052),
the driving module (TD) is configured to drive, based on the data signals, the light-emitting module to emit light (Para. 0054).
As to claim 17, Xu (Fig. 3) discloses the display device of claim 16, wherein the pixel unit further comprises a first node (N1), a second node (N3), and a third node (N2), the third node is the preset node (N2), and
the driving module comprises a driving switch transistor (TD), wherein a first control end of the driving switch transistor (TD) is electrically connected to the first node (N1), a second control end of the driving switch transistor (TD, back gate) is electrically connected to the third node (N2), a first conductive end of the driving switch transistor (TD) is electrically connected to a power supply voltage end (V1), and a second conductive end of the driving switch transistor is electrically connected to the second node (N3),
when the third node (N2) is at the initial potential (V3; Para. 0046), the driving switch transistor is turned on, and the power supply voltage end is configured to charge the third node to the preset potential (Para. 0052) through the driving switch transistor (TD) and the adjustment module (T3),
thereby controlling the driving switch transistor (TD) to be turned off and adjusting the threshold voltage of the driving switch transistor to the preset value (Para. 0052).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-8 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xu as applied to claims 2 and 17 above, and further in view of Zhao et al. (US 2022/0139337 A1, hereinafter “Zhao”).
As to claim 3, Xu (Fig. 2) discloses the display panel of claim 2, wherein the pixel unit further comprises a first signal receiving module (110) and
the first signal receiving module (110) is electrically connected to the first node (N1) and the data line (DL), and
the second signal receiving module is electrically connected to a reference voltage end and the second node,
the first signal receiving module (110) is configured to receive an adjustment signal or the data signal (Para. 0032) from the data line and transmit the adjustment signal or the data signal to the first node (Para. 0032),
the adjustment module (130) is configured to adjust the threshold voltage of the driving switch transistor (TD) based on the adjustment signal (Para. 0052),
the driving module (TD) is configured to drive, under control of the data signal (Para. 0053-0054),
the light-emitting module (150) to emit light (Para. 0054).
Xu does not disclose a second signal receiving module,
wherein the second signal receiving module is configured to receive a reference signal from the reference voltage end to control the second node to be at the initial potential.
However, Zhao (Fig. 23) teaches a second signal receiving module (273),
wherein the second signal receiving module (273) is configured to receive a reference signal (Vref) from the reference voltage end to control the second node (node between 220 and 250) to be at the initial potential (Para. 0153).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Zhao to include a second initialization circuit in the device disclosed by Xu. The motivation would have been to achieve the reset of the light-emitting unit (Zhao; Para. 0153).
As to claim 4, Xu (Fig. 3) discloses the display panel of claim 3, wherein the pixel unit further comprises a first storage module (C1) and a second storage module (C2),
the first storage module (C1) is electrically connected between the first node (N1) and the power supply voltage end (V1), and
the second storage module (C2) is electrically connected between the third node (N2) and the power supply voltage end (V1),
the first storage module (C1) is configured to store and maintain the voltage of the first node (Para. 0054), and
the second storage module (C2) is configured to store and maintain the voltage of the third node (Para. 0054).
As to claim 5, Xu (Fig. 2) discloses the display panel of claim 4, wherein the pixel unit further comprises a light-emitting control module (120) and a fourth node (node between 120 and 150),
the light-emitting control module (120) is electrically connected to the second node (N3) and the fourth node and is electrically connected to the light-emitting module (150) through the fourth node,
wherein the light-emitting control module (120) is configured to control the second node to be electrically connected to the fourth node (para. 0033).
As to claim 6, Xu (Fig. 3) discloses the display panel of claim 5, wherein the adjustment module comprises a first switch transistor (T3), and
the initialization module comprises a second switch transistor (T4),
a control end of the first switch transistor (T3) is electrically connected to a first adjustment end (S2), a first conductive end of the first switch transistor (T3) is electrically connected to the second node (N3), and a second conductive end of the first switch transistor (T3) is electrically connected to the third node (N2),
the first switch transistor (T3) is configured to be turned on under control of the first adjustment end (S2) to control the second node (N3) to be electrically connected to the third node (N2; Para. 0034);
wherein a control end of the second switch transistor (T4) is electrically connected to a second adjustment end (RST), a first conductive end of the second switch transistor (T4) is electrically connected to a reference voltage end (V3), and a second conductive end of the second switch transistor (T4) is electrically connected to the third node (N2);
the second switch transistor (T4) is configured to be turned on under control of the second adjustment end (RST) to receive the reference signal from the reference voltage end (V3) and transmit the reference signal to the third node (N2), to control the third node to be at the initial potential (Para. 0035).
As to claim 7, Xu (Fig. 3) discloses the display panel of claim 6, wherein the first signal receiving module comprises a third switch transistor (T1), and
a control end of the third switch transistor (T1) is electrically connected to the scan line (S1), a first conductive end of the third switch transistor (T1) is electrically connected to the data line (DL), and a second conductive end of the third switch transistor (T1) is electrically connected to the first node (N1);
wherein the third switch transistor (T1) is configured to be turned on under control of the scan signal (S1) to receive the data signal or the adjustment signal from the data line (DL) and transmit the data signal or the adjustment signal to the first node (N1; Para. 0032),
And, Zhao (Fig. 23) teaches the second signal receiving module (273) comprises a fourth switch transistor (Para. 0153; Fig. 14),
a control end of the fourth switch transistor (Fig. 23 element 273) is electrically connected to the second adjustment end (Scan13), a first conductive end of the fourth switch transistor (273) is electrically connected to the reference voltage end (Vref), and a second conductive end of the fourth switch transistor (273) is electrically connected to the second node (node between 220 and 250);
the fourth switch transistor (273) is configured to be turned on under control of the second adjustment end to receive the reference signal from the reference voltage end and transmit the reference signal to the second node, to control the second node to be at the initial potential (Para. 0153-0154).
As to claim 8, Xu (Fig. 3) discloses the display panel of claim 7, wherein the first storage module comprises a first capacitor (C1),
the second storage module comprises a second capacitor (C2), and
the light-emitting control module comprises a fifth switch transistor (T2),
the first capacitor (C1) is electrically connected between the first node (N1) and the power supply voltage end (V1), and
the second capacitor (C2) is electrically connected between the third node (N2) and the power supply voltage end (V1),
the first capacitor (C1) is configured to maintain a voltage difference between the first node and the power supply voltage end (Para. 0054), and
the second capacitor (C2) is configured to maintain a voltage difference between the third node and the power supply voltage end (Para. 0054),
wherein a control end of the fifth switch transistor (T2) is electrically connected to a light-emitting control end (EM), a first conductive end of the fifth switch transistor (T2) is electrically connected to the second node (N3), and a second conductive end of the fifth switch transistor (T2) is electrically connected to the fourth node (node between T2 and D),
the fifth switch transistor (T2) is configured to be turned on under control of the light-emitting control end to control the second node to be electrically connected to the fourth node (Para. 0044).
As to claim 18, Xu (Fig. 2) discloses the display device of claim 17, wherein the pixel unit further comprises a first signal receiving module (110) and
the first signal receiving module (110) is electrically connected to the first node (N1) and the data line (DL), and
the second signal receiving module is electrically connected to a reference voltage end and the second node,
the first signal receiving module (110) is configured to receive an adjustment signal or the data signal (Para. 0032) from the data line and transmit the adjustment signal or the data signal to the first node (Para. 0032),
the adjustment module (130) is configured to adjust the threshold voltage of the driving switch transistor (TD) based on the adjustment signal (Para. 0052),
the driving module (TD) is configured to drive, under control of the data signal (Para. 0053-0054),
the light-emitting module (150) to emit light (Para. 0054).
Xu does not disclose a second signal receiving module,
wherein the second signal receiving module is configured to receive a reference signal from the reference voltage end to control the second node to be at the initial potential.
However, Zhao (Fig. 23) teaches a second signal receiving module (273),
wherein the second signal receiving module (273) is configured to receive a reference signal (Vref) from the reference voltage end to control the second node (node between 220 and 250) to be at the initial potential (Para. 0153).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Zhao to include a second initialization circuit in the device disclosed by Xu. The motivation would have been to achieve the reset of the light-emitting unit (Zhao; Para. 0153).
As to claim 19, Xu (Fig. 3) discloses the display device of claim 18, wherein the pixel unit further comprises a first storage module (C1) and a second storage module (C2),
the first storage module (C1) is electrically connected between the first node (N1) and the power supply voltage end (V1), and
the second storage module (C2) is electrically connected between the third node (N2) and the power supply voltage end (V1),
the first storage module (C1) is configured to store and maintain the voltage of the first node (Para. 0054), and
the second storage module (C2) is configured to store and maintain the voltage of the third node (Para. 0054).
As to claim 20, Xu (Fig. 2) discloses the display device of claim 19, wherein the pixel unit further comprises a light-emitting control module (120) and a fourth node (node between 120 and 150),
the light-emitting control module (120) is electrically connected to the second node (N3) and the fourth node and is electrically connected to the light-emitting module (150) through the fourth node,
wherein the light-emitting control module (120) is configured to control the second node to be electrically connected to the fourth node (para. 0033).
Allowable Subject Matter
Claims 9-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose the limitation “in a first period, the second switch transistor, the third switch transistor, the fourth switch transistor, and the fifth switch transistor are turned on, and the first switch transistor is turned off” when combined with other limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Zhang (US 10,916,197 B1) discloses a compensation circuit for threshold correction (Fig. 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPIN GYAWALI whose telephone number is (571)272-1597. The examiner can normally be reached M-F 8:00-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Will Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BIPIN GYAWALI
Primary Examiner
Art Unit 2625
/BIPIN GYAWALI/Primary Examiner, Art Unit 2625
Prosecution Insights