DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Arguments
Applicant’s arguments with respect to claim(s) are rejected under 103(a) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Response to 112:
Applicant argued in the remark that 'one-to-one mapping' - The applicant submits that this is a technical feature known in the art and described in the application, and disagrees that this is a 'term of degree'.
Examiner respectfully disagrees. The phases “one-to-one mapping” (no clear definition of mapping constraints), the boundary of the phase “one to one” is not clear because, does it mean the mapping of the encryption to decryption by a single processor or two processors? or does it mean the mapping of the signal words by words? Thus, this limitation is indefinite.
Response to 103: Applicant argued in the remark of the page 13 of the claim 1 mapping that
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Examiner respectfully disagrees. Examiner did not apply any prior arts Kliland for rejecting claim 1. The claim 1 does not have any limitation “first server’. Thus, applicant argument does not compliance with the claim 1 limitation. So, examiner cannot response the applicant augments
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1, claim recites the phases “one-to-one mapping” (no clear definition of mapping constraints), the boundary of the phase “one to one” is not clear because, does it mean the mapping of the encryption to decryption by a single processor or two processors? or does it mean the mapping of the signal words by words? Thus, this limitation is indefinite.
Claim 1 contains the trademark/trade name “IEEE”. Where a trademark or trade name is used in a claim as a limitation to identify or describe a particular material or product, the claim does not comply with the requirements of 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. See Ex parte Simpson, 218 USPQ 1020 (Bd. App. 1982). The claim scope is uncertain since the trademark or trade name cannot be used properly to identify any particular material or product. A trademark or trade name is used to identify a source of goods, and not the goods themselves. Thus, a trademark or trade name does not identify or describe the goods associated with the trademark or trade name. In the present case, the trademark/trade name is used to identify/describe this claim also recites the phase “complaint with IEEE 802.3- there is not compliance test criteria are defined. But the IEEE is registered trademark name.
and, accordingly, the identification/description is indefinite. This claim also recites the phase “complaint with IEEE 802.3- there is not compliance test criteria are defined. But the IEEE is registered trademark name.
All dependent claims are rejected based on the same rational set forth in the claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
Claim(s) 1 and 16-18 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Guthery US 2010/0235905.
As per claim 1, Guthery discloses a device comprising:
a Local Area Network (LAN) connector (fig.2,0061 Network Interface 212 is connected with local computer and LAN ) for connecting to a LAN cable that carries a first Direct Current (DC) power signal and a first serial digital data signal that comprises first multiple words (fig.2, 0061 the network interface is inherently a hardware component that enables a device to connect to a network, and whether it operates over a LAN depends on the network type and configuration and the Network Interface is wired Ethernet NICs connector and the wired Ethernet NIC in a home PC can connect to a LAN and A Network Interface Card (NIC) is powered by the computer’s internal DC power supply — typically via its PCIe slot or onboard power connection and The NIC handles serial data and is uses the serializer/de-serializer module converts the parallel data from processor into serial data for transmission over the network cable);
an Ethernet interface (0061 The network interface 212 is an Ethernet port,) that is compatible with IEEE 802.3 standard and that is coupled to the LAN connector for receiving or transmitting the first serial digital data over the LAN cable ([0061] The network interface 212 is inherently any type of communications port or adaptor that enables the reader 112 to communicate with other communication or computing devices, such as a control panel. The network interface 212 may be implemented as any type of suitable communications port, for example, a Small Computer Systems Interface (SCSI), an Ethernet port, a modem, a coaxial cable port and
An Ethernet port is a physical interface on a device that connects to an Ethernet cable (typically an RJ45 connector) to enable wired local area network (LAN) communication. It is designed to carry Ethernet data over twisted-pair or fiber-optic cables, using standards like IEEE 802.3);
a Universal Serial Bus (USB) connector for connecting to a USB cable ( 0062 fig.2, The credential interface 216 may comprise one or more interfaces is such as an Electrical contact interfaces including contact-based technologies such as USB cable ) that carries a second DC power signal and a second serial digital data signal that comprises second multiple words that are different from the first multiple words ( 0062 An electrical contact interface that carries digital signals is a physical connection point—like a connector pin or switch—used to transmit binary data (1s and 0s) between electronic devices. It handles sequences of these signals to transmit complex, multiple-word data streams for digital communication);
a USB interface that is coupled to the USB connector for receiving or transmitting the second serial digital data over the USB cable ( 0062 An electrical contact interface that carries digital signals is a physical connection point—like a connector pin or switch—used to transmit binary data (1s and 0s) between electronic devices. It handles sequences of these signals to transmit complex, multiple-word data streams for digital communication);
a first memory (fig.2, memory 208) that stores computer-executable instructions; a processor (fig.2 processor) configured to access the first memory; and
a single enclosure housing (fig.2, 0055 a reader 112) the LAN and USB connectors, the LAN and USB interfaces, the first memory, and the processor (fig.2, 0055 The reader 112 may comprise a processor 204, memory 208, a network interface 212, i.e. LAN, a credential interface 216, includes 0062 An electrical contact interface, i.e. USB interfaces, and a user interface 220.),
wherein the processor (fig.2, par 0055 processor 204) is configured to execute the computer-executable instructions ( [0056] The processor 204 is provided to execute instructions contained within memory 208. Wherein the processor can be a programmable logic device such as TPM, PLD, PLA, FPGA, PA) to encrypt and decrypt, according to an encryption scheme that uses a one-to-one mapping, between the first multiple words and the second multiple words (0056 the TPM or the FPGA to generate and store encryption keys securely. The encryption and decryption operations are performed entirely within the TPM wherein the encryption and decryption are the one-to-one in the TPM operation and Moreover, Applicant admitted that 'one-to-one mapping' - The applicant submits that this is a technical feature known in the art and described in the application, and disagrees that this is a 'term of degree' in the response of the last non-final rejection), and
wherein the device (0049 the reader 112 ) is powered only by the first DC power signal from the LAN cable received from the LAN connector( 0049 the reader 112 may be connected to a control panel through a communication network and 0061 the reader 112 to communicate with other communication or computing devices, i.e. inherently those device is powered by DC power signal, such as a control panel. The network interface 212 may be implemented as any type of suitable communications port, for example, a Small Computer Systems Interface (SCSI), an Ethernet port, a modem, a coaxial cable port and 0087 the systems and methods of this invention can be implemented as program embedded on personal computer such as an integrated circuit card applet, JAVA.RTM. or CGI script, as a resource residing on a computer workstation, as a routine embedded in a dedicated communication system or system component, or the like. The system can also be implemented by physically incorporating the system and/or method into a software and/or hardware system, such as the hardware and software systems of a communications device or system).
As per claim 16. Guthery discloses the device according to claim 1, wherein the encrypting or the decrypting comprises, or is based on, implementing one or more Boolean functions (0056] The processor 204 is provided to execute instructions contained within memory 208. Wherein the processor can be a programmable logic device such as TPM, PLD, PLA, FPGA, the FPGA performs Boolean logic function and FPGAs can perform encryption functions).
As per claim 17. Guthery discloses The device according to claim 1, discloses further comprising in the single enclosure a power supply having a power port couplable to be powered from the first DC power signal, the power supply having one or more Direct Current (DC) outputs ( fig.2, 0061 the network interface is a hardware component that enables a device to connect to a network, and whether it operates over a LAN depends on the network type and configuration and the Network Interface is wired Ethernet NICs connector and the wired Ethernet NIC in a home PC can connect to a LAN and A Network Interface Card (NIC) is powered by the computer’s internal DC power supply — typically via its PCIe slot or onboard power connection and The NIC handles serial data and is uses the serializer/de-serializer module converts the parallel data from processor into serial data for transmission over the network cable).
As per claim 18. Guthery discloses The device according to claim 17, wherein the power supply is connected to the USB connector for providing the DC second power signal(0062 fig.2, The credential interface 216 may comprise one or more interfaces is such as an Electrical contact interfaces including contact-based technologies such as USB cable).
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Guthery US 2010/0235905 in view of Platko et al US 6,282,626.
As per claim 2. Guthery discloses the device according to claim 1, the combination does not explicitly disclose wherein the first multiple words comprise first multiple address words associated with a second memory, wherein the second multiple words comprise second multiple address words associated with the second memory (emphasis added).
However, Platko discloses the combination does not explicitly disclose wherein the first multiple words comprise first multiple address words associated with a second memory, wherein the second multiple words comprise second multiple address words associated with the second memory ( col 8, lines 43-48 if the read address falls within the first logical address sub-region of the first logical address region, then transferring a block of multiple data words including the requested data from a second memory to the first memory and transferring the requested data to the processor ).
Guthery and Platko are considered to be analogous to the claimed invention because they are in the same field of encryption process.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Guthery, including the teaching of Platko and provide a single shared hardware core—for both encryption and decryption provides significant efficiency and security advantages.
Doing so would aid in a single dedicated engine accelerates encrypting sensitive information before it leaves secure processor, thereby increasing minimizes exposure to vulnerabilities in the main CPU or system memory.
Claim 3-15 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Guthery US 2010/0235905 in view of Platko et al US 6,282,626.
and Sedlak US 6,182,217.
As per claim 3. Guthery in view of Platko discloses the device according to claim 2, Guthery discloses wherein the first or second multiple words, and wherein the encrypting or the decrypting is based on, or using, re-arranging a sequence of at least two bits in at least part of the first or second multiple words (0056 the TPM or the FPGA to generate and store encryption keys securely. The encryption and decryption operations are performed entirely within the TPM wherein the encryption and decryption are the one-to-one in the TPM operation).
The combination does not explicitly disclose wherein each of bits are associated with a level of significance of encrypting.
However, Sedlak discloses wherein each of bits are associated with a level of significance of encrypting (col 3, lines 5-11 hardware encryption can be performed using an encryption unit which is designed such that the significance of individual bits of the data interchange can be changed selectively. Bits stored in the memory as LOW, for example, then appear as HIGH in the data interchange on the data bus. This can be done, for example, using an encryption unit having at least one EXOR gate).
Guthery in view of Platko and Sedlak are considered to be analogous to the claimed invention because they are in the same field of encryption process.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Guthery in view of Platko, including the teaching of Sedlak and provide a single shared hardware core—for both encryption and decryption provides significant efficiency and security advantages. Doing so would aid in a single dedicated engine accelerates encrypting sensitive information before it leaves secure processor, thereby increasing minimizes exposure to vulnerabilities in the main CPU or system memory.
As per claim 4. Guthery in view of Platko discloses The device according to claim 2, Guthery discloses wherein the encrypting or the decrypting is based on ( 0056 the TPM or the FPGA to generate and store encryption keys securely. The encryption and decryption operations are performed entirely within the TPM wherein the encryption and decryption are the one-to-one in the TPM operation), or using, but does not explicitly disclose Sedlak discloses changing a significance level of at least two bits in the words(col 3, lines 5-11 hardware encryption can be performed using an encryption unit which is designed such that the significance of individual bits of the data interchange can be changed selectively. Bits stored in the memory as LOW, for example, then appear as HIGH in the data interchange on the data bus).
Guthery in view of Platko and Sedlak are considered to be analogous to the claimed invention because they are in the same field of encryption process.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Guthery in view of Platko, including the teaching of Sedlak and provide a single shared hardware core—for both encryption and decryption provides significant efficiency and security advantages. Doing so would aid in a single dedicated engine accelerates encrypting sensitive information before it leaves secure processor, thereby increasing minimizes exposure to vulnerabilities in the main CPU or system memory.
As per claim 5. Guthery in view of Platko discloses the device according to claim 2, the combination does not explicitly disclose wherein the second memory comprises a location-addressable memory having an address space that comprises the first or the second multiple address words
However, Sedalk discloses wherein the second memory comprises a location-addressable memory having an address space that comprises the first or the second multiple address words (col 6, lines 1-7selected by means of an address decoder AD associated with the CPU. To this end, the address decoder AD is supplied with the address of the memory location currently being addressed in each case by the CPU, and the corresponding register R1 . . . Rj is selected on the basis of a table stored in the address decoder or elsewhere. The keyword SW stored in the selected register R1 . . . Rj is then used by the encryption unit VE for encryption or decryption).
Guthery and Platko and Sedlak are considered to be analogous to the claimed invention because they are in the same field of encryption process.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Guthery in view of Platko, including the teaching of Sedlak and provide a single shared hardware core—for both encryption and decryption provides significant efficiency and security advantages. Doing so would aid in a single dedicated engine accelerates encrypting sensitive information before it leaves secure processor, thereby increasing minimizes exposure to vulnerabilities in the main CPU or system memory.
As per claim 6. Guthery and Platko and Sedlak The device according to claim 5 Guthery disclose, further comprising the second memory in the single enclosure (fig.2, processor 204, i.e. single enclosure, with the memory 208).
As per claim 7. Guthery in view of Platko and Sedlak The device according to claim 5, Platko discloses wherein the second memory is based on electrostatic (col 7, lines 53-55 the requested data from a second memory to the processor), ferroelectric, magnetic, acoustic, optical, chemical, electronic, electric, or mechanical storage medium (col 1, lines 40-50 When the processor makes a request for a word of data, a block of multiple words including the desired word is requested from memory. When the block is returned, the desired word is given to the processor, and the remainder of the block is stored in a read buffer. Subsequent processor requests for data words in the block are satisfied from the read buffer, and therefore are satisfied much more quickly than if additional requests to the system memory were required).
As per claim 8. Guthery in view of Platko and Sedlak discloses the device according to claim 7, Guthery discloses wherein the second memory is file-addressable or content-addressable, or wherein the device is part of a Network-attached Storage (NAS) or a Storage Area Network (SAN) ( [0087] Moreover, the disclosed methods may be readily implemented in software that can be stored on a storage medium, executed on a programmed general-purpose computer with the cooperation of a controller and memory, a special purpose computer, a microprocessor).
As per claim 9. Guthery in view of Platko and Sedlak discloses the device according to claim 7, Guthery discloses wherein the second memory is connectable to be read from, or written to, via the USB interface or via the USB connector ([0087] Moreover, the disclosed methods may be readily implemented in software that can be stored on a storage medium, executed on a programmed general-purpose computer with the cooperation of a controller and memory, a special purpose computer, a microprocessor).
As per claim 10. Guthery in view of Platko and Sedlak discloses the device according to claim 7, Sedlak discloses wherein the second memory is a sequential accessed memory, or wherein the second memory is location-based, randomly-accessed, and can be written multiple times (col 6, lines 1-7selected by means of an address decoder AD associated with the CPU. To this end, the address decoder AD is supplied with the address of the memory location currently being addressed in each case by the CPU, and the corresponding register R1 . . . Rj is selected on the basis of a table stored in the address decoder or elsewhere. The keyword SW stored in the selected register R1 . . . Rj is then used by the encryption unit VE for encryption or decryption).
As per claim 11. Guthery in view of Platko and Sedlak discloses the device according to claim 7, Guthery discloses wherein the second memory is based on semiconductor storage medium that is a volatile memory that comprises RAM, SRAM, DRAM, TTRAM, or Z-RAM ([0087] Moreover, the disclosed methods may be readily implemented in software that can be stored on a storage medium, executed on a programmed general-purpose computer with the cooperation of a controller and memory, a special purpose computer, a microprocessor).
As per claim 12. Guthery in view of Platko and Sedlak discloses The device according to claim 7,Guthery discloses wherein the second memory is based on semiconductor storage medium that is a non-volatile memory that comprises ROM, PROM, EPROM and EEROM, or is based on Flash technology( 0057] The memory 208 generally comprises software routines facilitating, in operation, pre-determined functionality of the reader 112. The memory 208 may be implemented using various types of electronic memory generally including at least one array of non-volatile memory cells (e.g., Erasable Programmable Read Only Memory (EPROM) cells or FLASH memory cells, etc.) The memory 208 may also include at least one array of dynamic random access memory (DRAM) cells. The content of the DRAM cells may be pre-programmed and write-protected thereafter, whereas other portions of the memory may selectively be modified or erased. The memory 208 may be used for either permanent data storage or temporary data storage).
As per claim 13. Guthery in view of Platko and Sedlak discloses The device according to claim 7, Guthery discloses wherein the second memory is an SSD drive or USB ‘Thumb’ drive ( 0057] The memory 208 generally comprises software routines facilitating, in operation, pre-determined functionality of the reader 112. The memory 208 may be implemented using various types of electronic memory generally including at least one array of non-volatile memory cells (e.g., Erasable Programmable Read Only Memory (EPROM) cells or FLASH memory cells, etc.) The memory 208 may also include at least one array of dynamic random access memory (DRAM) cells. The content of the DRAM cells may be pre-programmed and write-protected thereafter, whereas other portions of the memory may selectively be modified or erased. The memory 208 may be used for either permanent data storage or temporary data storage).
As per claim 14. Guthery in view of Platko and Sedlak discloses the device according to claim 7,Guthery discloses wherein the second memory is based on non-volatile magnetic storage medium, or wherein the second memory comprises a Hard Disk Drive (HDD)( 0057] The memory 208 generally comprises software routines facilitating, in operation, pre-determined functionality of the reader 112. The memory 208 may be implemented using various types of electronic memory generally including at least one array of non-volatile memory cells (e.g., Erasable Programmable Read Only Memory (EPROM) cells or FLASH memory cells, etc.) The memory 208 may also include at least one array of dynamic random access memory (DRAM) cells. The content of the DRAM cells may be pre-programmed and write-protected thereafter, whereas other portions of the memory may selectively be modified or erased. The memory 208 may be used for either permanent data storage or temporary data storage).
As per claim 15. Guthery in view of Platko and Sedlak discloses The device according to claim 7,Guthery discloses wherein the second memory is based on an optical storage medium, wherein the second memory includes an optical disk drive, or wherein the second memory medium is CD-RW, DVD-RW, DVD+RW, DVD-RAM, or BD-RE (0057] The memory 208 generally comprises software routines facilitating, in operation, pre-determined functionality of the reader 112. The memory 208 may be implemented using various types of electronic memory generally including at least one array of non-volatile memory cells (e.g., Erasable Programmable Read Only Memory (EPROM) cells or FLASH memory cells, etc.) The memory 208 may also include at least one array of dynamic random access memory (DRAM) cells. The content of the DRAM cells may be pre-programmed and write-protected thereafter, whereas other portions of the memory may selectively be modified or erased. The memory 208 may be used for either permanent data storage or temporary data storage.).
Claims 19 and 20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Guthery US 2010/0235905 in view of Platko et al US 6,282,626.
and Glickman US 2005/0128520.
As per claim 19. Guthery and Platko discloses the device according to claim 1, the combination does not disclose wherein the LAN is based on 100BaseT/TX, 1000BaseT/TX, 10 gigabit Ethernet substantially according to IEEE Std 802.3ae-2002as standard, 40 Gigabit Ethernet, or 100 Gigabit Ethernet substantially according to IEEE P802.3ba standard.
However, Glickman discloses wherein the LAN is based on 100BaseT/TX, 1000BaseT/TX, 10 gigabit Ethernet substantially according to IEEE Std 802.3ae-2002as standard, 40 Gigabit Ethernet, or 100 Gigabit Ethernet substantially according to IEEE P802.3ba standard(0015 the data transfer device may further include or be interchanged with a wired network card, such as an IEEE 802.3 standard wired local area network (LAN) interface card, e.g. Ethernet, 100BASE-T standard (IEEE 802.3u) or fast Ethernet, IEEE 802.3z or gigabit Ethernet, and/or other suitable wired network interface. ).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Guthery and Platko, including the teaching of Glickman and provide a single shared hardware core—for both encryption and decryption provides significant efficiency and security advantages. Doing so would aid in a single dedicated engine accelerates encrypting sensitive information before it leaves secure processor, thereby improving significant efficiency and security advantages of tamper resistant techniques.
As per claim 20. Guthery and Platko discloses the device according to claim 1, the combination does not disclose wherein the encryption scheme is based on Advanced Encryption Standard (AES) 128, 192 or 256 bits.
Glickman discloses wherein the encryption scheme is based on Advanced Encryption Standard (AES) 128, 192 or 256 bits. (0021 wireless channel 22 may be protected by use of cryptosystems, systems as the Advanced Encryption Standard (AES) cryptosystem).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Guthery and Platko discloses, including the teaching of Glickman and provide a single shared hardware core—for both encryption and decryption provides significant efficiency and security advantages. Doing so would aid in a single dedicated engine accelerates encrypting sensitive information before it leaves secure processor, thereby improving significant efficiency and security advantages of tamper resistant techniques.
Claims 21-27 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Guthery US 2010/0235905 in view of Platko et al US 6,282,626 and He US 2007/0047525.
As per claim 21. Guthery in view of Platko discloses the device according to claim 1, the combination does not explicitly wherein the first DC power signal is carried over dedicated wires in the LAN cable.
He discloses wherein the first DC power signal is carried over dedicated wires in the LAN cable(0010 [0010] According to IEEE Standard 802.3af, a Power Sourcing Equipment (PSE) operating as either a Midspan or Endpoint apparatus provides DC or low frequency inline power over two pairs of a LAN cable to a remote terminal device).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Guthery in view of Platko, including the teaching of He and provide a single shared hardware core—for both encryption and decryption provides significant efficiency and security advantages. Doing so would aid in a single dedicated engine accelerates encrypting sensitive information before it leaves secure processor, thereby improving significant efficiency and security advantages of tamper resistant techniques.
As per claim 22. Guthery in view of Platko discloses The device according to claim 1, the combination does not explicitly disclose wherein the first DC power signal is carried over same wires that carry the first serial data, and wherein the device further comprising a power/data splitter arrangement having first, second and third ports, wherein only the first serial digital data signal is passed between the first and second ports, wherein only the first DC power signal is passed between the first and third ports, and wherein the first port is coupled to the LAN connector.
However, He discloses wherein the first DC power signal is carried over same wires that carry the first serial data, and wherein the device further comprising a power/data splitter arrangement having first, second and third ports, wherein only the first serial digital data signal is passed between the first and second ports, wherein only the first DC power signal is passed between the first and third ports, and wherein the first port is coupled to the LAN connector ( 0007 IEEE Standard 802.3, a cable of four twisted pairs, referred to as a LAN cable hereinafter, such as Category 5 cable or the like is used to provide a full-duplex communication link between a network device such as an Ethernet switch and terminal device such as a computer. Typically, the four twisted pairs of the LAN cable are referred to as pair 1-2, pair 3-6, pair 4-5; pair 7-8. A standard 8-conductor RJ45 plug assembled with the LAN cable is usually used for connecting with a standard 8-conductor RJ45 jack. Of variants of Ethernet protocols, 10Base-T and 100Base-TX, referred to as 10/100Base-T hereinafter, refers to transmission of Ethernet data signals at 10 Mbps (bit per second) and 100 Mbps respectively by using pair 1-2 and pair 3-6 of the LAN cable while pair 4-5 and pair 7-8 of the LAN cable are left unused. 1000Base-T refers to transmission of Ethernet data signals at 1000 Mbps by using all the four pairs of the LAN cable. And 0008] An Ethernet LAN in the early days was usually found in a shared bus topology by which multiple computers were physically hooked up to a single cable segment, sending and receiving packets to each other based on the communication protocol called "Carrier Sense Multiple Access with Collision Detection (CSMA/CD)" as specified in IEEE Standard 802.3. Today, Ethernet switches are typically used for achieving much higher data throughput with improved network reliability. An Ethernet Switch is a multi-port LAN interconnection device which operates at the data link layer (layer 2) of the network hierarchy (OSI reference model)).
As per claim 23. Guthery in view of Platko and He discloses the device according to claim 22, He discloses wherein the first DC power and first digital data signals are carried using Frequency Division Multiplexing (FDM), where the first digital data signal is carried over a frequency band above and distinct from the first DC power signal (0010 IEEE Standard 802.3af, a Power Sourcing Equipment (PSE) operating as either a Midspan or Endpoint apparatus provides DC or low frequency inline power over two pairs of a LAN cable to a remote terminal device in one of two modes).
As per claim 24. Guthery in view of Platko and He discloses the device according to claim 23, He discloses wherein the power/data splitter comprising a High Pass Filter (HPF) between the first and second ports and a Low Pass Filter (LPF) between the first and third ports (0060 a corresponding 3-port multiplexing apparatus MUX_EP 140 is used at each remote location. Multiplexing apparatus MUX_EP 140 is provided with one network I/O port for connecting to network multiplexer MUX_SW 110 over LAN cable 125 and another two network I/O ports for connecting via two patch cables to computer 150 and the IP phone 160, respectively. Such a 3-port multiplexing apparatus is commercially available, which is sometime referred to as RJ45 splitter or Ethernet splitter).
As per claim 25. Guthery in view of Platko and He discloses the device according to claim 22, He discloses wherein the power/data splitter comprising a transformer and a capacitor connected to the transformer windings, or wherein the first DC power and the first digital data signals are carried using phantom scheme(0010 IEEE Standard 802.3af, a Power Sourcing Equipment (PSE) operating as either a Midspan or Endpoint apparatus provides DC or low frequency inline power over two pairs of a LAN cable to a remote terminal device).
As per claim 26. Guthery in view of Platko and He discloses the device according to claim 22, He discloses wherein the power/data splitter comprising at least two transformers each having a center-tap connection( 0052 voltage polarity adjusting circuit 360 is implemented in which center tap 347 of the first isolation transformer 340 and center tap 357 of the second isolation transformer 350 are connected respectively with two input ends of voltage polarity adjusting circuit 360 and the two output ends of voltage polarity adjusting circuit 360 are connected to center tap 345 of transformer 340 and center tap 355 of transformer 350 respectively. Voltage polarity adjusting circuit 360 essentially includes diodes and it ensures that inline power of "Alternative A" that may be carried by pair 1-2 and pair 3-6 of patch cable 115 is applied properly between pair 4-5 and pair 7-8 of LAN cable 125 with correct voltage polarity as defined by IEEE Standard 802.3af, regardless whether or not patch cable 115 is a straight-through cable or a cross-over cable).
As per claim 27. Guthery in view of Platko and He discloses The device according to claim 26, He discloses wherein the first DC power and the first digital data signals are carried substantially according to IEEE 802.3af-2003 or IEEE 802.3at-2009 standard (0010 IEEE Standard 802.3af, a Power Sourcing Equipment (PSE) operating as either a Midspan or Endpoint apparatus provides DC or low frequency inline power over two pairs of a LAN cable to a remote terminal device).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABU S SHOLEMAN whose telephone number is (571)270-7314. The examiner can normally be reached EST: 9am-5pm.
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/ABU S SHOLEMAN/Primary Examiner, Art Unit 2496
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