DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Allowable Subject Matter
Claims 4, 7-8, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the closest related art includes Kim et al. (US 20140092144 A1) and Joo et al. (US 20200126476 A1), specifically Joo figures 1-3 and [0053-0063]. Kim and Joo, and the other prior art, however does not detail all the limitations of claim 4, particularly:
a second power supply device supplying power to the specific display module among the plurality of display modules, and the at least one processor is configured to detect whether power supplied to the first power supply device or the second power supply device is off based on an output voltage of the first power supply device or the second power supply device. Regarding claims 7 and 17, the closest related prior art is Toyozawa et al. (US 2006/0181498) and Soo et al. (KR20150005775A). The prior art does not detail the limitations of claims 7 or 17:
wherein the detection circuit includes a first resistor connected to an output terminal of the power supply device and a second resistor having one end connected to the first resistor and the other end grounded, and
wherein the at least one processor is configured to identify whether the output voltage of the power supply device is decreased to reach the predetermined voltage based on an output terminal voltage between the first resistor and the second resistor.
Regarding claim 8, the closest related prior art is Toyozawa et al. (US 2006/0181498) and Soo et al. (KR20150005775A). The prior art does not detail the limitations of claim 8:
The device as claimed in claim 5, wherein the detection circuit includes a first detection circuit connected to a first power supply device, a second detection circuit connected to the second power supply device, and a logic circuit connected to a first output terminal of the first detection circuit and a second output terminal of the second detection circuit, wherein the logic circuit is implemented as an OR gate for outputting a low signal in case that a voltage of the first output terminal is low and a voltage of the second output terminal is low, and wherein the at least one processor is configured to identify that power supplied to the power supply device is off in case that the low signal is output from the logic circuit.
Note to applicant: Two Prior art rejections Applied
To expedite prosecution, independent claims 1, 11, and 20 are rejected twice below in view of two different primary prior art references.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
First rejection in view of Kim et al. and Joshi et al.
Claims 1, 11, and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over applicant IDS cited Kim et al. (US 20140092144 A1) in view of Joshi et al. (US 20170084246 A1).
Regarding claims 1, 11, and 20, Kim teaches a driving method of a display device ([0023], “Fig. 1, organic light emitting display”) and a non-transitory computer-readable medium storing a computer instruction that causes an electronic device to perform an operation in case of being executed by a processor (Fig. 9, [0074], see the internal register 113 of the timing controller 11) of a display device, comprising:
a display panel including a plurality of light emitting elements (Fig. 1, [0025], display panel 10 and pixels P, “Each of the pixels P may be formed as a circuit consisting of an OLED”);
at least one driver for driving the plurality of light emitting elements (Fig. 1, [0023], “a panel driving circuit for writing data to the display panel 10.” [0024] “The panel driving circuit comprises a data driving circuit 12, a gate driving circuit 13”);
a power supply device (Fig. 1, [0023], “a power supply unit 20 for generating power required to drive the panel driving circuit.” [0029] provides detail of power supply unit 20); and
at least one processor (Figs. 1 and 9-10, [0026], timing controller 11) configured to identify off sequence information of the at least one driver in case of detecting power supplied to the power supply device as being off based on an output voltage of the power supply device (Figs. 11-12, [0081-0082]) and
sequentially control a plurality of signals transmitted to the at least one driver to be in a low state based on the identified off sequence information before a voltage for driving the display panel is shut down (Figs. 11-12, [0081-0082]).
Kim is not relied upon for teaching identify off sequence information of the at least one driver in case of detecting power supplied to the power supply device as being off based on an output voltage of a power detection line connected to an output terminal of the power supply device, the off sequence information defining an order of blocking a plurality of signals transmitted to the at least one driver, and
sequentially control the plurality of signals transmitted to the at least one driver to be in a low state based on the order defined by the identified off sequence information before a voltage for driving the display panel is shut down.
Joshi teaches a display device (Fig. 1, [0002-0003]) comprising:
a display panel including a plurality of light emitting elements (Fig. 1, [0003]);
at least one driver for driving the plurality of light emitting elements (Fig. 1, [0062], processing means 5 connected to general processing unit 6);
a power supply device (Fig. 1, [0063], DC power supply 7 connected to AC power source 8); and
at least one processor (Fig. 1, [0062], processing means 5 connected to general processing unit 6) configured to:
identify off sequence information of the at least one driver in case of detecting power supplied to the power supply device as being off based on an output voltage of a power detection line connected to an output terminal of the power supply device (([0001, 0009], “a power sequencer control circuit for controlling the power on or off operation of the local power units.” [0026], “A first signal or “Standby” signal on a first conductor is used to signal that a DC power supply providing power to a display unit must be disconnected from the AC power source.” [0027], The first signal can be a voltage signal. [0083], “detection of zero crossing”), the off sequence information defining an order of blocking a plurality of signals transmitted to the at least one driver ([0083], “Once the state of relay 9 has been changed, the processing means 11 generate a pulse with help of a current driver to open the relay 16 or 17 that was closed for detection of zero crossing”), and
sequentially control the plurality of signals transmitted to the at least one driver to be in a low state based on the order defined by the identified off sequence information before a voltage for driving the display panel is shut down ([0026-0027], a signal that a DC power supply providing power to a display unit must be disconnected from the AC power source can be a sequence of signals or pulses or waves or a single pulse. Also see [0033], “the DC power supplies can be powered up or down by a power sequencer control circuit”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention to modify Kim with Joshi to provide a power sequencer control circuit for controlling the power on or off operation as Joshi’s circuit provides an advantage of minimal power dissipation during power up and power down (Joshi, [0010, 0014-0015]).
Second rejection in view of Toyozawa et al. and Joshi et al.
Claims 1, 9-11, and 18-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over applicant IDS cited Toyozawa et al. (US 2006/0181498) in view of Joshi et al. (US 20170084246 A1).
Regarding claims 1, 11, and 20, Toyozawa teaches a driving method of a display device (Title, [0019], Fig. 1, display device 0) and a non-transitory computer-readable medium storing a computer instruction that causes an electronic device to perform an operation in case of being executed by a processor (Fig. 9, [0074], see the internal register 113 of the timing controller 11) of a display device, comprising:
a display panel including a plurality of light emitting elements (Fig. 1, [0020], display area 2 has a matrix of pixels each pixel including a liquid crystal element for controlling light emission);
at least one driver for driving the plurality of light emitting elements (Fig. 1, [0022], “a peripheral circuit unit includes, for example, a vertical driver 3, a horizontal driver 4, a COM driver 5, a CS driver 6.” [0026] “The horizontal driver 4 writes the gradated analog signal voltages to the liquid crystal element LC according to image information supplied from the side of the electronic device proper.”);
a power supply device (Fig. 1, [0025], “DC/DC converter 7 converts a primary power supply voltage supplied from the electronic device proper via the FPC 11 into a secondary power supply voltage in accordance with a specification for the panel (display device 0).”); and
at least one processor (Figs. 1, [0026], interface 8, “receives control signals such as a clock signal, a synchronizing signal, an image signal and the like supplied from the set side via the FPC 11. The level shifter L/S shifts levels of the control signals (external control signals) sent from the set side to generate control signals (internal control signals) conforming to specifications for circuit operation within the display device”) configured to identify off sequence information of the at least one driver in case of detecting power supplied to the power supply device as being off based on an output voltage of the power supply device (Figs. 2B, 3B, 6-7, and 9 show an off sequence of a elements within a peripheral circuit. See corresponding specification [0027-0028, 0031, 0039, 0041, 0047, 0049] which describe and disclose these limitations); and
sequentially control a plurality of signals transmitted to the at least one driver to be in a low state based on the identified off sequence information before a voltage for driving the display panel is shut down (See Figs. 2B, 3B, 6-7, and 9, and corresponding specification [0028, 0031, 0039, 0041, 0047, 0049] describing an off sequence of elements within a peripheral circuit wherein a plurality of signals are transmitted to a peripheral circuit to be in a low state. See, for example, figs. 6 and 9 wherein Panel Input signals such as DATA and Panel Internal signals are Low or All L. Note [0004, 0049] teaches, “at a time of shifting off the power” of the display panel).
Toyozawa is not relied upon for teaching identify off sequence information of the at least one driver in case of detecting power supplied to the power supply device as being off based on an output voltage of a power detection line connected to an output terminal of the power supply device, the off sequence information defining an order of blocking a plurality of signals transmitted to the at least one driver, and
sequentially control the plurality of signals transmitted to the at least one driver to be in a low state based on the order defined by the identified off sequence information before a voltage for driving the display panel is shut down.
Joshi teaches a display device (Fig. 1, [0002-0003]) comprising:
a display panel including a plurality of light emitting elements (Fig. 1, [0003]);
at least one driver for driving the plurality of light emitting elements (Fig. 1, [0062], processing means 5 connected to general processing unit 6);
a power supply device (Fig. 1, [0063], DC power supply 7 connected to AC power source 8); and
at least one processor (Fig. 1, [0062], processing means 5 connected to general processing unit 6) configured to;
identify off sequence information of the at least one driver in case of detecting power supplied to the power supply device as being off based on an output voltage of a power detection line connected to an output terminal of the power supply device (([0001, 0009], “a power sequencer control circuit for controlling the power on or off operation of the local power units.” [0026], “A first signal or “Standby” signal on a first conductor is used to signal that a DC power supply providing power to a display unit must be disconnected from the AC power source.” [0027], The first signal can be a voltage signal. [0083], “detection of zero crossing”), the off sequence information defining an order of blocking a plurality of signals transmitted to the at least one driver ([0083], “Once the state of relay 9 has been changed, the processing means 11 generate a pulse with help of a current driver to open the relay 16 or 17 that was closed for detection of zero crossing”), and
sequentially control the plurality of signals transmitted to the at least one driver to be in a low state based on the order defined by the identified off sequence information before a voltage for driving the display panel is shut down ([0026-0027], a signal that a DC power supply providing power to a display unit must be disconnected from the AC power source can be a sequence of signals or pulses or waves or a single pulse. Also see [0033], “the DC power supplies can be powered up or down by a power sequencer control circuit”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention to modify Toyozawa with Joshi to provide a power sequencer control circuit for controlling the power on or off operation as Joshi’s circuit provides an advantage of minimal power dissipation during power up and power down (Joshi, [0010, 0014-0015]).
Regarding claims 9 and 18, Toyozawa teaches wherein the at least one processor is configured to sequentially control a reset signal and at least one power signal, transmitted to the at least one driver, to be in the low state based on the identified off sequence information (See Figs. 2B, 3B, 6-7, and 9, and corresponding specification [0028, 0031, 0039, 0041, 0047, 0049] describing an off sequence which includes controlling a Reset signal RST, and a Power supply VDD signal to a low or off state during shut off. [0028], “In the off sequence (B), for turning off the display by the set side,… the reset signal RST is changed from a high to a low,…and finally the VDD falls. Thereby the VDD becomes a ground potential”).
Regarding claims 10 and 19, Toyozawa teaches the device as claimed in claim 1, wherein the at least one processor is configured to sequentially control the plurality of signals among a reset signal, at least one power signal, at least one sync signal, and at least one clock signal, transmitted to the at least one driver, to be in the low state based on the identified off sequence information (See Figs. 2B, 3B, 6-7, and 9, and corresponding specification [0028, 0031, 0039, 0041, 0047, 0049] describing an off sequence which includes controlling a Reset signal RST, Clock MCK, HSYNC, VSYNC and a Power supply VDD signal transition to a low or off state during shut off. [0028], “In the off sequence (B), for turning off the display by the set side,… the reset signal RST is changed from a high to a low,…and finally the VDD falls. Thereby the VDD becomes a ground potential”).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over applicant IDS cited Kim et al. (US 20140092144 A1) in view of Joshi et al. (US 20170084246 A1), as applied to claim 1, and further in view of Soo et al. (KR20150005775A. Note, examiner maps to attached Espacenet English translation).
Regarding claims 2 and 12, Kim and Joshi are not relied upon for teaching the claim limitations.
Soo teaches a device wherein at least one processor is configured to identify whether an alternating current, AC, power supplied through the power supply device is off by detecting a power line through which a direct current, DC, voltage is output from the power supply device (Figs. 1-3 and [0022], disclose a system wherein AC power is supplied to a DC power main line. [0025], “A detection unit 400 including a plurality of detection sensors 400a-400n respectively detecting voltage or current signals in a DC line to which an AC power source generated by the AC generation unit 300 is applied.” [0028-0030] teaches a detection unit detects an applied waveform on a power line. Examiner notes this means detection unit is capable of detecting when a power supply is off as the detection unit can detect when there is or is not a signal currently on the power line).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Kim and Joshi with Soo to include a detection unit which detects signals on a power line as Soo teaches this allows a system to determine an abnormal or fault state on the main line of a DC power system (Soo, [0007, 0022]).
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over applicant IDS cited Kim et al. (US 20140092144 A1) in view of Joshi et al. (US 20170084246 A1), as applied to claim 1, and further in view of Ahn et al. (US 20210326092 A1).
Regarding claims 3 and 13, Kim and Joshi are not relied upon for teaching the claim limitations.
Ahn teaches a device wherein a display panel is a modular display panel including the plurality of display modules ([0052], Fig. 1A, “a display apparatus 100 according to an embodiment may include four display modules 131 to 134.” [0116], “in FIG. 5, the modular display apparatus 1000 includes a display apparatus 100, a display apparatus A 100-A, and a display apparatus B 100-B”), and wherein the at least one driver includes the plurality of drivers corresponding to the plurality of display modules (Figs. 4-5 see processor 140 which includes a plurality of processors 140 each corresponding to a respective display module 100).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Kim and Joshi with Ahn such that Kim’s driving method is implemented in a modular display system as Ahn teaches a modular display system allows for a plurality of displays to be driven in concert to provide a large screen (Ahn, [0003]).
Claims 5-6, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over applicant IDS cited Toyozawa et al. (US 2006/0181498) in view of Joshi et al. (US 20170084246 A1), as applied to claim 1 above, and further in view of Soo et al. (KR20150005775A).
Regarding claims 5 and 14, Toyozawa teaches wherein the at least one processor or display device for outputting an identified off sequence signal to the at least one driver in case that the output voltage of the power supply device is decreased to reach a predetermined voltage as power supplied from the power supply device is off (See figs. 2B, 3B, 6, and 9, and corresponding specification [0028-0029, 0031-0032, 0039, 0041, 0046] which show and teach an off sequence B that corresponds to the claim limitations including sending off signals which decrease a voltage such as Vdd to an off state).
Toyozawa does not explicitly teach a processor further includes a detection circuit.
Soo teaches a detection circuit which detects the output voltage of the power supply device (Figs. 1-3 and [0022], disclose a system wherein AC power is supplied to a DC power main line. [0025], “A detection unit 400 including a plurality of detection sensors 400a-400n respectively detecting voltage or current signals in a DC line to which an AC power source generated by the AC generation unit 300 is applied.” [0028-0030] teaches a detection unit detects an applied waveform on a power line).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Toyozawa and Joshi with Soo such that a processor further includes a detection circuit as Soo teaches this allows a system to determine an abnormal or fault state on the main line of a DC power system (Soo, [0007, 0022]).
Regarding claims 6 and 16, Toyozawa is not relied upon for teaching the claim limitations.
Soo teaches wherein the detection circuit is connected to a power detection line terminal for detecting the output voltage of the power supply device ([0025], “A detection unit 400 including a plurality of detection sensors 400a-400n respectively detecting voltage or current signals in a DC line to which an AC power source generated by the AC generation unit 300 is applied.”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Toyozawa and Joshi with Soo such that a processor further includes a detection circuit connected to a power detection line terminal for detecting the output voltage of the power supply device as Soo teaches this allows a system to determine an abnormal or fault state on the main line of a DC power system (Soo, [0007, 0022]).
Response to Arguments
Applicants’ arguments filed September 3, 2026, are directed towards the amended subject matter. As detailed in the rejections above, the combination of Kim and Joshi and Toyozawa and Joshi teach each and all claim limitations as currently presented.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20240312430 A1, Shigeta [0006-0007] teaches a power off detection circuit for use in a display.
US 20220208057 A1, You et al. [0073] teaches a power off sequence of a plurality of displays
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN P BRITTINGHAM whose telephone number is (571)270-7865. The examiner can normally be reached Monday-Thursday, 10 AM - 6 PM, EST.
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/NATHAN P BRITTINGHAM/Primary Examiner, Art Unit 2629
