DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al., US Patent Publication 2020/0111420.
Regarding independent claim 1, Yang et al. teaches a display device (depicted in figure 1), comprising:
a display panel (display device 10 with pixel array 100 of figure 1 as given in paragraph 0019) configured to display an image (as given in paragraphs 0019-0020);
a gate driver (scan driver 110 of figure 1 as given in paragraph 0019) connected to gate lines (S0 to Sn of figure 1 as given in paragraph 0020) of the display panel (as all depicted in figure 1); and
a data driver (data driver 130 of figure 1 as given in paragraph 0019) connected to data lines (D1 to Dm of figure 1 as given in paragraph 0020) of the display panel (as all depicted in figure 1),
wherein the display panel is configured to operate in a period during which a display data voltage is stored based on three scan signals sequentially applied through three scan lines included in one gate line during one horizontal time, and a source node is initialized based on an initialization data voltage (paragraphs 0019-0032 and 0068-0077 explain that the display panel stores data voltages in display pixels according to three gate signals CD1-CD4, Sk during one horizontal time, and a source node (any of N1, the node connecting T4/T7 of figure 3 as given in paragraph 0071) is initialized based on an initialization data voltage as given in paragraphs 0050 and 0053).
Regarding claim 2, Yang et al. teaches the display device of claim 1, wherein the display panel includes a first subpixel (PXL1 of figure 1) for storing the display data voltage (received via data line Dja) and initializing the source node (node connecting T4/T7) based on the initialization data voltage (Vint), and
wherein the display data voltage is a data voltage applied through a first data line connected to the first subpixel, and the initialization data voltage includes a data voltage applied through a second data line connected to a second subpixel adjacent to the first subpixel (paragraphs 0019-0067 and figures 1 and 3 show that the initialization data voltage Vint is connected to adjacent subpixels).
Regarding claim 3, Yang et al. teaches the display device of claim 1, wherein the display panel includes a first pixel including four subpixels connected to second and third scan lines among the three scan lines, and a second pixel including four subpixels connected to a first scan line and a second scan lines among the three scan lines (figures 1-3 show that the plurality of subpixels located in a row are connected to the same gate lines S1/E1 and plural rows are connected driven by different gate lines, e.g. S2/E2).
Regarding claim 4, Yang et al. teaches the display device (as depicted in figures 1 and 3 and described in paragraphs 0019-0067) of claim 3, wherein the first pixel includes a first subpixel (first column, third row of figure 1) connected to the second scan line (S2) and connected to a first data line (D1b) and a third data line (Vint), a second subpixel (second column, third row of figure 1) connected to the second scan line (S2) and connected to a second data line (D2b) and a fourth data line (Vint), a third subpixel (first column, second to last row of figure 1) connected to the third scan line (Sn-1) and connected to the third data line (Vint) and the first data line (D1b), and a fourth subpixel (second column, second to last row of figure 1) connected to the third scan line (Sn-1) and connected to the fourth data line (Vint) and the second data line (D2b).
Regarding claim 5, Yang et al. teaches the display device of claim 4, wherein the first subpixel (first column, third row of figure 1) stores the display data voltage (as given in paragraph 0056) applied through the first data line (D1b) in a capacitor (Cst of figure 3) and initializes a source node based on the initialization data voltage applied through the third data line (Vint),
wherein the second subpixel (second column, third row of figure 1) stores the display data voltage (as given in paragraph 0056) applied through the second data line (S2) in a capacitor (Cst) and initializes a source node based on the initialization data voltage applied through the fourth data line (Vint),
wherein the third subpixel (first column, second to last row of figure 1) stores the display data voltage (as given in paragraph 0056) applied through the third data line (Vint) in a capacitor (Cst) and initializes a source node based on the initialization data voltage applied through the first data line (D1b), and
wherein the fourth subpixel (second column, second to last row of figure 1) stores the display data voltage (as given in paragraph 0056) applied through the fourth data line (Vint) in a capacitor (Cst) and initializes a source node based on the initialization data voltage applied through the second data line (D2b).
Regarding claim 6, Yang et al. teaches the display device (as depicted in figures 1 and 3 and described in paragraphs 0019-0067) of claim 3, wherein the second pixel includes a first subpixel (first column, third row of figure 1) connected to the first scan line (S2) and connected to a first data line (D1b) and a third data line (Vint), a second subpixel (second column, third row of figure 1) connected to the first scan line (S2) and connected to a second data line (D2b) and a fourth data line (Vint), a third subpixel (first column, second to last row of figure 1) connected to the second scan line (Sn-1) and connected to the third data line (Vint) and the first data line (D1b), and a fourth subpixel (second column, second to last row of figure 1) connected to the second scan line (Sn-1) and connected to the fourth data line (Vint) and the second data line (D2b).
Regarding independent claim 8, Yang et al. teaches a method of driving a display device, comprising:
applying a first scan signal through a first scan line (Sn-1) included in one gate line and driving a first subpixel (first column, second to last row of figure 1) and a second subpixel (second column, second to last row of figure 1) included in a second pixel;
applying a second scan signal through a second scan line (S2) included in the gate line and driving a first subpixel (first column, third row of figure 1) and a second subpixel (second column, third row of figure 1) included in a first pixel and a third subpixel (first column, third row of figure 1) and a fourth subpixel (second column, third row of figure 1) included in the second pixel; and
applying a third scan signal through a third scan line (Sn-1) included in the gate line and driving a third subpixel (first column, second to last row of figure 1) and a fourth subpixel (second column, second to last row of figure 1) included in the first pixel,
wherein the first pixel and the second pixel store a display data voltage based on the first scan signal, the second scan signal, and the third scan signal sequentially applied for one horizontal time and initialize a source node based on an initialization data voltage (figures 1, 3, and 4 and paragraphs 0044-0077 explain that the rows of subpixels shown in figure 1 are scanned sequentially and initialized based on scan signals Sk to Sk+3).
Regarding claim 9, Yang et al. teaches the method of claim 8, wherein the display data voltage is a data voltage applied through a first data line, and the initialization data voltage includes a data voltage applied through a second data line adjacent to the first data line (paragraphs 0019-0067 and figures 1 and 3 show that the initialization data voltage Vint is connected to adjacent subpixels with adjacent data lines).
Regarding claim 10, Yang et al. teaches the method (as depicted in figures 1 and 3 and described in paragraphs 0019-0067) of claim 8, wherein the first pixel includes a first subpixel (first column, second to last row of figure 1) connected to the second scan line (Sn-1) and connected to a first data line (Vint) and a third data line (Vint), a second subpixel (second column, second to last row of figure 1) connected to the second scan line (Sn-1) and connected to a second data line (D2b) and a fourth data line (Vint), a third subpixel (first column, third row of figure 1) connected to the third scan line (S2) and connected to the third data line (D1b) and the first data line (Vint), and a fourth subpixel (second column, third last row of figure 1) connected to the third scan line (S2) and connected to the fourth data line (Vint) and the second data line (D2b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., US Patent Publication 2020/0111420 in view of Hwang et al., US Patent Publication 2022/0036813.
Regarding claim 7, Yang et al. teaches the display device of claim 1.
Yang et al. does not explicitly teach wherein the display panel includes:
a red subpixel and a green subpixel configured to start operation during a first period of time for which a first scan signal is applied;
a red subpixel, a green subpixel, a blue subpixel, and a white subpixel configured to start operation during a second period of time for which a second scan signal is applied; and
a blue subpixel and a white subpixel configured to start operation during a third period of time for which a third scan signal is applied.
Hwang et al. teaches in figures 12-14 and paragraphs 0099-0112 wherein the display panel includes:
a red subpixel and a green subpixel configured to start operation during a first period of time for which a first scan signal is applied (paragraph 0108 shows that the first gate line provides a first scan signals for pixels P1 and P3 that are shown in figure 14 to be red and blue subpixels. However, using red and green instead of red and blue would be an obvious matter of rearrangement of parts. In reJapikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950));
a red subpixel, a green subpixel, a blue subpixel, and a white subpixel configured to start operation during a second period of time for which a second scan signal is applied (paragraph 0109 shows that the second gate line provides a second scan signals for pixels P1 and P3 that are shown in figure 14 to be one of each color subpixels); and
a blue subpixel and a white subpixel configured to start operation during a third period of time for which a third scan signal is applied (paragraph 0110 shows that the third gate line provides a third scan signals for pixels P2 and P4 that are shown in figure 14 to be white and green subpixels. However, using blue and white instead of white and green would be an obvious matter of rearrangement of parts. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use the color display taught by Hwang et al. as the display in the system of Yang et al. The rationale to combine would be to provide a color display using RGBW that reduces manufacturing costs (paragraphs 0003-0004 of Hwang et al.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The closest prior is made of record in the attached notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARUL H GUPTA whose telephone number is (571)272-5260. The examiner can normally be reached Monday through Friday, from 10 AM to 7 PM.
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/PARUL H GUPTA/Primary Examiner, Art Unit 2627
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