DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
1. Claim(s) 1-2, 4-10, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xue (US 2021/0327349).
As to claim 1, Xue teaches a display device comprising:
a display panel having a plurality of sub-pixels thereon ([0049] large size active-matrix organic light-emitting diode (AMOLED) display panels);
at least one gate driver including a logic unit (a pull-up control unit 100 + a first pull-down maintenance unit 140 + an inverting unit 150 + a first pull-down unit 160, fig. 1), a first output unit (T21 + a third pull-down maintenance unit 190, fig. 1) configured to output a first scan signal (a second control signal RD(n), fig. 1), and a second output unit (a first pull-up unit 120 + a second pull-down maintenance unit 170, fig. 1) configured to output a second scan signal (a first control signal WR(n), fig. 1); and
a plurality of gate-low line connected to the at least one gate driver (VGL1 and VGL2, fig. 1);
wherein the plurality of gate-low lines (VGL1 and VGL2, fig. 1) is connected to the logic unit, first output unit, and the second output unit (see fig. 1), and
wherein the first output unit (T21 + a third pull-down maintenance unit 190, fig. 1) and the second output unit (a first pull-up unit 120 + a second pull-down maintenance unit 170, fig.1) are coupled to share the logic unit (a pull-up control unit 100 + a first pull-down maintenance unit 140 + an inverting unit 150 + a first pull-down unit 160, fig. 1) to output the first scan signal (a second control signal RD(n), fig. 1) and the second scan signal (a first control signal WR(n), fig. 1),
wherein the at least one gate driver includes a Q node (Q(n), fig. 1) and a QB node (QB(n), fig. 1),
wherein the first output unit comprises:
a first transistor (T21, fig. 1) having a gate electrode connected to the Q node (Q(n), fig. 1) and a drain electrode connected to a first output terminal where the first scan signal is output (a second control signal RD(n), fig. 1); and
a second transistor (T41, fig. 1) having a gate electrode connected to the QB node (QB(n), fig. 1) and a drain electrode connected to the first output terminal (a second control signal RD(n), fig. 1),
wherein the second output units comprises:
a sixth transistor (T23, fig. 1) having a gate electrode connected to the first transistor (T21, fig. 1) and a drain electrode connected to a second output terminal where the second scan signal is configured to be output (a first control signal WR(n), fig. 1); and
a seventh transistor (T43, fig. 1) having a drain electrode connected to the second output terminal (a first control signal WR(n), fig. 1), and
wherein among the plurality of gate-low lines, a gate-low line connected to the logic unit (VGL1, fig. 1) and a gate-low line connected to the first output unit are configured (VGL2, fig. 1) to output gate-low voltages of different levels (see fig. 1).
As to claim 2, Xue teaches the display device, wherein the plurality of gate-low lines includes a first gate-low line (VGL1, fig. 1) and a second gate-low line (VGL2, fig. 1), the logic unit is connected to the first gate-low line (VGL1, fig. 1), and the first output unit (T21 + a third pull-down maintenance unit 190, fig. 1) is connected to the second gate-low line (VGL2, fig. 1).
As to claim 4, Xue teaches the display device, wherein the first output unit (T21 + a third pull-down maintenance unit 190, fig. 1) and the second output unit (a first pull-up unit 120 + a second pull-down maintenance unit 170, fig. 1) are coupled to share the Q node (Q(n), fig. 1) and the QB node (QB(n), fig. 1).
As to claim 5, Xue teaches the display device, wherein the first transistor (T21, fig. 1) is configured to output a first level voltage (VGH, fig. 1) to the first output terminal (a second control signal RD(n), fig. 1), and the second transistor (T41, fig. 1) is configured to output a second level voltage (VGL2, fig. 1) to the first output terminal (a second control signal RD(n), fig. 1).
As to claim 6, Xue teaches the display device, wherein the logic unit further comprises a fifth transistor (T54, fig. 1) configured to transmit the second level (VGL1, fig. 1) voltage to the QB node (QB(n), fig. 1).
As to claim 7, Xue teaches the display device, wherein the at least one gate driver comprises a plurality of stages ([0027] The GOA circuit includes a plurality of cascaded GOA circuit sharing units), wherein each of the plurality of stages comprises a respective one of the first output unit (T21 + a third pull-down maintenance unit 190, fig. 1, [0027]), a respective one of the second output unit (a first pull-up unit 120 + a second pull-down maintenance unit 170, fig.1, [0027]), and a respective one of the logic unit (a pull-up control unit 100 + a first pull-down maintenance unit 140 + an inverting unit 150 + a first pull-down unit 160, fig. 1).
As to claim 8, Xue teaches the display device, wherein the respective logic unit of a stage among the plurality of stages is configured to transmit a first scan signal (Cout(n-1), fig. 1) output from a previous stage among the plurality of stages to the respective first output unit of the stage based on a clock signal (CK1, fig. 1).
As to claim 9, Xue teaches the display device, wherein the respective logic unit of a stage further comprises a third transistor (T11 and T12, fig. 1) configured to be turned on by a clock signal (CK1, fig. 1), and connects the respective first output terminal of a previous stage (Cout(n-1), fig. 1) among the plurality of stages and the Q node of the stage (Q(n), fig. 1).
As to claim 10, Xue teaches the display device, wherein the sixth transistor (T23, fig. 1) is configured to output a first level voltage to the second output terminal (CK2, fig. 1, and the seventh transistor (T43, fig. 1) is configured to output a second level voltage to the second output terminal (VGL1, fig. 1).
As to claim 15, Xue teaches the display device, wherein a pulse length of the first scan signal is different from a pulse length of the second scan signal (see WR(n) and RD(n) in fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 3, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xue (US 2021/0327349) in view of Lee et al (US 2021/0407427).
As to claim 3, Xue does not teach the QN node as claimed.
However, Lee teaches the display device, wherein the at least one gate driver further includes a QN node (N10, fig. 11), and a gate electrode of the seventh transistor is connected to the QN node (MT23, fig. 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Xue to teach, the QN node, as suggested by Lee. The motivation would have been in order to improve the display quality and reduce power consumption ([0005], [0007]).
As to claim 16, Xue does not teach n-type transistor as claimed.
However, Lee teaches the display device, each of the plurality of sub-pixels comprises at least one n-type transistor (T3, and T4, fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Xue to teach, n-type transistor, as suggested by Lee. The motivation would have been in order to improve the display quality and reduce power consumption ([0005], [0007]).
As to claim 17, Xue in view of Lee teach the display device, wherein the at least one n-type transistor (Lee: T3, fig. 3) is configured to be controlled by the first scan signal (Lee: GCj, fig. 3).
As to claim 18, Xue in view of Lee teach the display device, wherein the at least one n-type transistor (Lee: T4, fig. 3) is configured to be controlled by the second scan signal (Lee: Glj, fig. 3).
As to claim 19, Xue in view of Lee teach the display device, each of the plurality of sub pixels comprises: a driving transistor (Lee: T1, fig. 3) having a gate electrode connected to a first node (Lee: fig. 3 illustrates that the gate of T1 coupled to an electrode of T3, T4 and Cst), a source electrode connected to a second node (Lee: an electrode of T5, fig. 3), and a drain electrode connected to a third node (Lee: an electrode of T6, fig. 3); a first pixel transistor (Lee: T2, fig. 3) connected between the second node and a data line (Lee: DLi, fig. 3); and a second pixel transistor connected to the first node (Lee: T4, fig. 3).
As to claim 20, Xue in view of Lee teach the display device, the second pixel transistor (Lee: T4, fig. 3) is configured to transmit a first initialization voltage (Lee: VINT1, fig. 3) to the driving transistor (T1, fig. 3).
Allowable Subject Matter
3. Claims 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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