DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are present for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities: No Summary in the Specification. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, , 15, 16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Muro et al (US 2010/0299565), hereinafter as Muro, in view of Zhao et al (US 2022/0179762), hereinafter as Zhao.
RE claims 1 and 15, Muro discloses the invention substantially as claimed.
Muro discloses that a disk device (see figure 1 and sections [0028], [0033], [0034], [0037]; i.e., the disk array apparatus 100) comprising: a nonvolatile memory including a storage area including multiple access units and a management information storage area in which defect management information is stored (see figures 1&3 and sections [0091], [0094], [0097], [0104], [0107], [0110], [0117], [0147]-[0149]; i.e., the nonvolatile memory 115 including multiple access units, such as memory chips 301/302/303/304, and a management information storage area, such as the invalidity management table 218 in which the bad sector information of the nonvolatile memory 115 being stored, or in which defect management information is stored), each of the multiple access units being smaller than a defect management unit managed by the defect management information in the storage area (see figures 3&4 and sections [0110], [0112], [0147]-[0150]; i.e., each of the memory chips 301/302/303/304, for example, memory chip 301 comprising of Banks 305/306, wherein as the invalidity management table 218 can be stored within/across more than two Banks, thus each of the memory chips 301/302/303/304 can be regarded as smaller than the invalidity management table 218).
However, Muro does not specifically disclose that a controller accessible to the nonvolatile memory, the controller being considered to execute alternative processing by re-assigning data to another access unit and rewriting data originally assigned to a defective access unit among the multiple access units.
Zhao teaches that a nonvolatile storage system 100 comprising of nonvolatile memory 104 and a controller 102 to accessible to the nonvolatile memory 104, and the controller 102 being configured to execute alternative processing by re-assigning/backup data to backup block 210 and rewriting/backup data originally assigned to a defective access unit 206, among the multiple access units 206/210 (see figures 1&2 and sections [0017], [0019], [0021], [0023], [0025], [0026], [0031], [0039]). The motivation of Zhao is to eliminate the risk of data loss due to program errors (see section [0008]).
Muro and Zhao are combinable because they are from the same field of endeavor. It would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to modify Muro by including the teaching from Zhao in order to eliminate the risk of data loss due to program errors.
RE claim 2, Muro in view of Zhao disclose that wherein the defect management unit includes a block, and the access unit includes a page (see Zhao, figure 2 and section [0021]; i.e., block 206, page 208).
RE claims 3 and 18, Muro in view of Zhao disclose that wherein the controller is configured to execute the alternative processing in response to occurrence of power supply cutoff (see Muro, figure 1 and section [0041]; i.e., the control circuit 111 to execute the alternative processing to occurrence of power cutoff).
RE claim 4, Muro in view of Zhao disclose that wherein the controller generates or updates, according to the execution of the alternative processing, alternative management information in which an address of a defective access unit where a write error has been detected and an address of an access unit substituted for the address of the defective access unit are associated with respect to address of one or more defective access units (see Zhao, section [0025]; i.e., the mapping table linking the backup table and the defective table is managed by controller 102 and updated dynamically).
RE claims 5 and 20, Muro in view of Zhao disclose that wherein the controller stores the generated or updated alternative management information in the management information storage area and makes the generated or updated alternative management information nonvolatile (see Muro, section [0107]; i.e., updating the invalidity management table 218).
RE claim 6, Muro in view of Zhao disclose that wherein the controller is configured to issue a write command to the nonvolatile memory for each of the access units (see Zhao, figure 2; i.e., controller 102).
RE claim 7, Muro in view of Zhao disclose that a host interface connectable to a host, wherein in a case where a write request including address-designation concerning the multiple access units is received in the host interface from the host, the controller issues multiple write commands corresponding to the multiple access units to the nonvolatile memory in response to the write request (see Zhao, figures 1&2; i.e., host connected to the nonvolatile storage system 100 through host interface, the controller 102 issues write commands to nonvolatile memory 104).
RE claim 8, Muro in view of Zhao disclose that wherein in a case where the write request is received, the controller divides write data included in the write request into multiple pieces of partial data each having an access unit size and issues the multiple write commands corresponding to the multiple pieces of partial data to the nonvolatile memory (see Zhao, figure 2; i.e., nonvolatile memory 104 contains data in size of blocks 206/210, and pages 208/212).
RE claim 16, Muro in view of Zhao disclose that wherein the determining includes, in a case where a response time of a write command including address-designating of the first access unit exceeds a threshold, determining that the second access unit is a defective access unit (see Muro, sections [0065], [0094], [0099], [0102], [0105], [0113]).
Allowable Subject Matter
Claims 9-14, 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sharon et al (US 2017/0249207)
Chu et al (US 2008/0130156)
Chen (USPN 8,417,869)
Malonzo (USPN 8,959,416)
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/FRED TZENG/ Primary Examiner, Art Unit 2625
FFT
September 29, 2026
