DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9, and 17 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by [Lee; Jae Young et al., US 20230215375 A1].
Regarding claim 1:
Lee discloses:
1. A gate driver (300) [Lee: Fig.1: gate driver 130], comprising:
a plurality of stages (STG1 to STG5) [Lee: Fig.13: stages STG1, STG2m STG3, STG4, ... STGm] which are cascaded to each other [Lee: Fig.13: stages STG1, STG2m STG3, STG4, ... STGm; ¶ 0059: “circuits included in second to M-th stages STG2 to STGm may be configured in the same manner as the first stage STG1 … respectively connected to the second horizontal line 2nd to the M-th horizontal line mth and output signals thereto”; Examiner: Lee’s gate driver 130 is a shift register (Fig.13) of plural identical stages STG1-STGm, each tied to a successive horizontal line. The first stage STG1 is initiated by the start signal VST (¶ 0067) and the serially-arranged stages are sequenced by the multi-phase clockbus GCLKS (¶ 0053: “at least 10 phases”) to activate in turn and scan successive gate lines GL1-GLm. A shift register of serially-arranged stages scanning successive lines is “cascaded to each other” under the broadest reasonable interpretation (BRI); the claim recites no stage-to-carry hand-off.] and configured to output a plurality of gate signals (GS1 to GS5) [Lee: Fig.13: gate signals GL1, GL2, GL3, GL4 ... GLm] based on (i) an input signal (VST) [Lee: Fig.14: start signal line VST], (ii) a reset signal (QRST) [Lee: Fig.14: reset signal line QRST], (iii) at least one clock signal among first, second, third and fourth clock signals [Lee: Fig.15: clock signals CLK1, CLK2, CLK3 and CLK4], (iv) a first power source (VGH) [Lee: Fig.14: gate high voltage line VGH], and (v) a second power source (VGL) [Lee: Fig.14: gate low voltage line VGL] which has a voltage level lower than the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; Examiner: VGL represent a low voltage and VGH a high voltage, VGL is lower than VGL.],
wherein a first stage [Lee: Fig.13: first stage STG1], among the plurality of stages (STG1 to STG5) [Lee: Fig.13: stages STG1, STG2m STG3, STG4, ... STGm], includes:
a first node controller circuit (310) [Lee: Fig.14: first transistor T1, second transistor T2, third transistor T3] configured to control a voltage of a first node (Q1) [Lee: Fig.14: node QN] based on the input signal (VST) [Lee: Fig.14: start signal line VST; ¶ 0067: “The first transistor T1 may have a gate electrode connected to the start signal line VST and a first electrode connected to the gate low voltage line VGL”], the first clock signal (CLK1) [Lee: ¶ 0067: “ The second transistor T2 may have a gate electrode connected to the fourth clock signal line CLK4 … and a second electrode connected to a QN node QN”; Examiner: Lee’s CLK4 reads on the claimed first clock – the clock ordinals are nominal designations within the four-clock set, no inter-clock phase relationship being recited in claim 1.], the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0067: “The third transistor T3 may … a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QN node QN”], and a voltage of a second node (QB) [Lee: Fig.14: node QBN; ¶ 0067: “The third transistor T3 may have a gate electrode connected to a QB node QBN (an inverting node operating opposite to the QN node)”];
a second node controller circuit (320) [Lee: Fig.14: fourth transistor T4, fifth transistor T5, eighth transistor T8] configured to control a voltage of the second node (QB) [Lee: Fig.14: node QBN; ¶ 0076: “The QBN node QBN can be charged with the gate low voltage by the gate low voltage transferred through the fourth transistor T4”] based on the input signal [Lee: ¶ 0068: “The fifth transistor T5 may have a gate electrode connected to the start signal line VST … and a second electrode connected to the QB node QBN”], the fourth clock signal (CLK4) [Lee: ¶ 0068: “The fourth transistor T4 may have a gate electrode connected to the third clock signal line CLK3 … and a second electrode connected to the QB node QBN”; Examiner: Lee’s CLK3 reads on the claimed fourth clock – distinct from the first/second clocks used by the first node controller (CLK4) and output (CLK1)], the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0069: “The eighth transistor T8 may have a gate electrode connected to the QN node QN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QB node QBN”], and the second power source (VGL) [Lee: Fig.14: gate low voltage line VGL; ¶ 0068: “ The fourth transistor T4 may have … a first electrode connected to the gate low voltage line VGL”];
an output circuit (330) [Lee: Fig.14: sixth transistor T6_1, seventh transistor T7_1, output capacitor CQ1] configured to selectively output the second clock signal (CLK2) [Lee: Fig.15: G1 output; ¶ 0074: “ the low voltage of the first clock signal Clk1 can be output through the output terminal G10 via the turned on sixth transistor T6_1”; ¶ 0069: “a first electrode connected to the first clock signal line CLK1”; Examiner: Lee’s CLK1 reads on the claimed second clock] or a voltage of the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0076: “the gate high voltage … can be output through the output terminal G10 via the turned on seventh transistor T7_1”; ¶ 0069: “a first electrode connected to the gate high voltage line VGH”], based on a voltage of a third node (Q2) [Lee: Fig.14: gate of TG_1 at the second electrode of TBV: ¶ 0069: “The sixth transistor T6_1 may have a gate electrode connected to the second electrode of the stabilization transistor TBV”; Examiner: The node at TBV’s second electrode (the T6_1 gate) is a node distinct from the first node QN – it reads on the claimed third node, and the output pull-up is gated by it.] and the voltage of the second node (QB) [Lee: Fig.14: node QBN; ¶ 0069: “The seventh transistor T7_1 may have a gate electrode connected to the QB node QBN”];
and a bridge voltage transistor (Tbv) [Lee: Fig.14: stabilization transistor TBV”] connected between the first node (Q1) [Lee: Fig.14: node QN; ¶ 0068: “The stabilization transistor TBV may have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to the QN node QN”] and the third node (Q2) [Lee: Fig.14: gate of TG_1 at the second electrode of TBV: ¶ 0068: “and a second electrode connected to the gate electrode of the sixth transistor T6_1; Examiner: TBV is connected between the first node (QN) and the third node (the TG_1 gate), reading on the claimed bridge voltage transistor between the first and third nodes.].
Regarding claim 2:
Lee discloses:
2. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 1,
wherein a voltage of the second power source (VGL) [Lee: Fig.14: gate low voltage line VGL] is supplied to a gate electrode of the bridge voltage transistor (Tbv) [Lee: Fig.14: stabilization transistor TBV”; ¶ 0068: “The stabilization transistor TBV may have a gate electrode connected to the gate low voltage line VGL”].
Regarding claim 3:
Lee discloses:
3. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 2,
wherein the bridge voltage transistor (Tbv) [Lee: Fig.14: stabilization transistor TBV”] is configured to maintain a turned-on state [Lee: ¶ 0072: “The stabilization transistor TBV can be turned on in response to a gate low voltage at a low voltage applied through the gate low voltage line VGL”; Examiner: Because TBV is a p-type and its gate is tied to the constant gate low voltage VGL, TBV is necessarily held in the on state at all times.].
Regarding claim 4:
Lee discloses:
4. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 1,
wherein the voltage of the first node (Q1) [Lee: Fig.14: node QN] and the voltage of the third node (Q2) [Lee: Fig.14: gate of TG_1 at the second electrode of TBV: ¶ 0069: “The sixth transistor T6_1 may have a gate electrode connected to the second electrode of the stabilization transistor TBV”] have a same voltage level [Lee: Fig.14: TBV bridging QN and the T7_1 gate node; ¶ 0073: “the sixth transistor T6_1 can be turned on by the gate low voltage transmitted through the stabilization transistor TBV”; Examiner: TBV is maintained on (claim 3) and connects the first node QN to the third node at the T6_1 gate, so the QN voltage is transmitted through TBV to the third node and the two nodes are held at the same level.].
Regarding claim 6:
Lee discloses:
6. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 1,
wherein the second node controller circuit (320) [Lee: Fig.14: fourth transistor T4, fifth transistor T5, eighth transistor T8] includes: a third transistor (T3) [Lee: Fig.14: T4] which is connected between (i) a second power input terminal to which a voltage of the second power source (VGL) [Lee: Fig.14: gate low voltage line VGL] is supplied [Lee: Fig.14; ¶ 0068: “a first electrode connected to the gate low voltage line VGL”] and (ii) the second node (QB) [Lee: Fig.14: node QBN; ¶ 0068: “a second electrode connected to the QB node QBN”], and includes a gate electrode connected to a fifth input terminal to which the fourth clock signal (CLK4) is supplied [Lee: Fig.14; ¶ 0068: “The fourth transistor T4 may have a gate electrode connected to the third clock signal line CLK3”];
and a fourth transistor (T4) [Lee: Fig.14: T5] which is connected between (i) a first power input terminal to which the voltage of the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0068: “The fifth transistor T5 may have…a first electrode connected to the gate high voltage line VGH”] is supplied and (ii) the second node (QB) [Lee: Fig.14: node QBN; ¶ 0068: “The fifth transistor T5 may have… a second electrode connected to the QB node QBN”], and includes a gate electrode connected to a first input terminal to which the input signal is supplied [Lee: Fig.14; ¶ 0068: “The fifth transistor T5 may have a gate electrode connected to the start signal line VST”].
Regarding claim 7:
Lee discloses:
7. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 6,
wherein the second node controller circuit (320) [Lee: Fig.14: fourth transistor T4, fifth transistor T5, eighth transistor T8] further includes a seventh transistor (T7) [Lee: Fig.14: T8] which is connected between (i) the first power input terminal [Lee: Fig.14; ¶ 0069: “a first electrode connected to the gate high voltage line VGH”] and (ii) the second node (QB) [Lee: Fig.14: node QBN; ¶ 0069: “a second electrode connected to the QB node QBN”], and includes a gate electrode connected to the first node (Q1) [Lee: Fig.14: node QN; ¶ 0069: “The eighth transistor T8 may have a gate electrode connected to the QN node QN”].
Regarding claim 8:
Lee discloses:
8. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 1,
wherein the output circuit (330) [Lee: Fig.14: sixth transistor T6_1, seventh transistor T7_1, output capacitor CQ1] includes: a fifth transistor (T5) [Lee: Fig.14: sixth transistor T6_1] which is connected between (i) a fourth input terminal to which the second clock signal (CLK2) is supplied [Lee: Fig.14; ¶ 0069: “a first electrode connected to the first clock signal line CLK1”] and (ii) an output terminal from which a gate signal among the plurality of gate signals (GS1 to GS5) [Lee: Fig.13: gate signals GL1, GL2, GL3, GL4 ... GLm] is output [Lee: Fig.14; ¶ 0069: “and a second electrode connected to an output terminal G10”; ¶ 0074: “the low voltage of the first clock signal Clk1 can be output through the output terminal G10 via the turned on sixth transistor T6_1”], and includes a gate electrode connected to the third node (Q2) [Lee: Fig.14: gate of TG_1 at the second electrode of TBV: ¶ 0069: “The sixth transistor T6_1 may have a gate electrode connected to the second electrode of the stabilization transistor TBV”];
and a sixth transistor (T6) [Lee: Fig.14: T7_1] which is connected between (i) a first power input terminal to which the voltage of the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH] is supplied [Lee: Fig.14; ¶ 0069: “a first electrode connected to the gate high voltage line VGH”] and (ii) the output terminal [Lee: Fig.14; ¶ 0069: “a second electrode connected to the output terminal G10”], and includes a gate electrode connected to the second node (QB) [Lee: Fig.14: node QBN; ¶ 0069: “The seventh transistor T7_1 may have a gate electrode connected to the QB node QBN”].
Regarding claim 9:
Lee discloses:
9. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 8,
wherein the first stage further includes: a first capacitor (C1) [Lee: Fig.14: output capacitor CQ1] connected between the third node (Q2) [Lee: Fig.14: gate of TG_1 at the second electrode of TBV: ¶ 0069: “The sixth transistor T6_1 may have a gate electrode connected to the second electrode of the stabilization transistor TBV”; ¶ 0071: “The output capacitor CQ1 may have a first electrode connected to the gate electrode of the sixth transistor T6_1”] and the output terminal [Lee: Fig.14; ¶ 0071: “; ¶ 0071: “and a second electrode connected to the output terminal G10"”];
and a second capacitor (C2) [Lee: Fig.14: node capacitor CQB] connected between the second node (QB) [Lee: Fig.14: node QBN; ¶ 0071: “The node capacitor CQB … a second electrode connected to the QB node QBN”] and the first power input terminal [Lee: Fig.14; ¶ 0071: “The node capacitor CQB may have a first electrode connected to the gate high voltage line VGH”].
Regarding claim 17:
Lee discloses:
17. A display device (1000) [Lee: Fig.1; ¶ 0027: “FIG. 1 is a block diagram schematically showing a light emitting display device”], comprising:
a display panel (100) [Lee: Fig.1: display panel 150] which includes a plurality of pixels (PX) [Lee: Fig.1: sub-pixel SP];
and a gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 1,
wherein the plurality of gate signals (GS1 to GS5) [Lee: Fig.1: gate signals GL1, GL2, GL3, GL4 ... GLm] are output to the plurality of pixels (PX) [Lee: Fig.1: sub-pixel SP].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Lee; Jae Young et al., US 20230215375 A1] in view of [Seo; Jeongrim, US 20220208109 A1].
Regarding claim 10:
Lee discloses:
10. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 1,
wherein the first stage further includes: a reset circuit (340) [Lee: Fig.14: T9] configured to control the voltage of the first node (Q1) [Lee: Fig.14: node QN; ¶ 0071: “The ninth transistor T9 may have a gate electrode connected to the reset signal line QRST, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QN node QN”] and the voltage of the second node (QB) based on the reset signal (QRST) [Lee: Fig.14: reset signal line QRST; ¶ 0071: “ a gate electrode connected to the reset signal line QRST”], the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0071: “a first electrode connected to the gate high voltage line VGH”], and the second power source (VGL).
However, Lee does not expressly disclose:
the reset circuit controlling the voltage of the second node (QB) based on the reset signal and the second power source.
Seo discloses:
the reset circuit (340) [Seo: Fig.7: QB node stabilizer 510] controlling the voltage of the second node (QB) [Seo: Fig.7: QB] based on the reset signal [Seo: Fig.7: RESET] and the second power source [Seo: Fig.7: GVSS3; ¶ 0167: “The second transistor T52 and the third transistor T53 are connected to and disposed between the QB node and the third low-potential voltage line for delivering the third low-potential voltage GVSS3”; ¶ 0168: “The second transistor T52 and the third transistor T53 discharge the QB node to the third low-potential voltage GVSS3 level in response to an input of the reset signal … he second transistor T52 can be turned on based on an input of the reset signal RESET”; Examiner: Seo’s transistor T52, gated by the reset signal, connects GVSS3 (second power source) and drives it there on reset, which is the reset path Lee lacks. Seo also resets the first node to the high rail on reset (¶ 0126: the line selector ”charges the Q node to a first high-potential voltage GVDD1 level … in response to an input of the reset signal RESET”), confirming a reset of both nodes by the reset signal.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add to Lee a reset transistor connecting the second power source (VGL) to the second node (QBN) and gated by the reset signal (QRST), as Seo teaches at ¶ 0168. Because Lee already uses QRST to reset its first node through T9 (¶ 0071) and Seo applies the reset signal to both nodes (¶ 0123, 0168), extending Lee’s existing reset signal to the second node is the predictable use of a known technique to improve a similar device in the same way among analogous GIP gate driver stages. The result is predictable because the added transistor works by the same mechanism as Lee’s existing T9, driving QBN to VGL on reset just as T9 drives QN to VGH, with no change to Lee’s principle of operation.
Regarding claim 11:
Lee discloses:
11. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 10,
wherein the reset circuit (340) includes: a first reset transistor (Trst1) [Lee: Fig.14: T9] which is connected between (i) a first power input terminal to which the voltage of the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH] is supplied [Lee: Fig.14; ¶ 0071: “a first electrode connected to the gate high voltage line VGH”] and (ii) the first node (Q1) [Lee: Fig.14: node QN; ¶ 0071: “ a second electrode connected to the QN node QN”], and includes a gate electrode connected to a second input terminal to which the reset signal (QRST) [Lee: Fig.14: reset signal line QRST] is supplied [Lee: Fig.14¶ 0071: “The ninth transistor T9 may have a gate electrode connected to the reset signal line QRST”];
and a second reset transistor which is connected between (i) a second power input terminal to which a voltage of the second power source (VGL) is supplied and (ii) the second node (QB), and includes a gate electrode connected to the second input terminal.
However, Lee does not expressly disclose:
and a second reset transistor which is connected between (i) a second power input terminal to which a voltage of the second power source (VGL) is supplied and (ii) the second node (QB), and includes a gate electrode connected to the second input terminal.
Seo discloses:
and a second reset transistor (Trst2 [Seo: ¶ 0164: “The QB node stabilizer 510 includes first to third transistors T51 to T53”] which is connected between (i) a second power input terminal to which a voltage of the second power source (VGL) is supplied [Seo: Fig.7: GVSS3] and (ii) the second node (QB) [Seo: Fig.7:QB], and includes a gate electrode connected to the second input terminal [Seo: Fig.7: RESET; ¶ 0168: “The second transistor T52 can be turned on based on an input of the reset signal RESET”].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add to Lee’s reset circuit a second reset transistor connecting the second power source (VGL) to the second node (QBN) and gated by the reset signal, as Seo teaches at ¶ 0168. Lee already provides a first reset transistor (T9) that drives the first node to VGH on reset, and Seo applies the reset signal to both nodes (¶ 0126, 0168), so providing the corresponding second reset transistor on Lee’s second node is the use of a known technique to improve a similar device in the same way. The result is predictable, because the added transistor works by the same mechanism as Lee’s T9, driving QBN to VGL on reset, with no change to Lee’s principle of operation.
Regarding claim 12:
Lee discloses:
12. A gate driver (300) [Lee: Fig.1: gate driver 130], comprising:
a plurality of stages (STG1 to STG5) [Lee: Fig.13: stages STG1, STG2m STG3, STG4, ... STGm] which are cascaded to each other [Lee: Fig.13: stages STG1, STG2m STG3, STG4, ... STGm; ¶ 0059: “circuits included in second to M-th stages STG2 to STGm may be configured in the same manner as the first stage STG1 … respectively connected to the second horizontal line 2nd to the M-th horizontal line mth and output signals thereto”; Examiner: Lee’s gate driver 130 is a shift register (Fig.13) of plural identical stages STG1-STGm, each tied to a successive horizontal line. The first stage STG1 is initiated by the start signal VST (¶ 0067) and the serially-arranged stages are sequenced by the multi-phase clockbus GCLKS (¶ 0053: “at least 10 phases”) to activate in turn and scan successive gate lines GL1-GLm. A shift register of serially-arranged stages scanning successive lines is “cascaded to each other” under the broadest reasonable interpretation (BRI); the claim recites no stage-to-carry hand-off.] and configured to output a plurality of gate signals (GS1 to GS5) [Lee: Fig.13: gate signals GL1, GL2, GL3, GL4 ... GLm] based on (i) an input signal (VST) [Lee: Fig.14: start signal line VST], (ii) a reset signal (QRST) [Lee: Fig.14: reset signal line QRST], (iii) at least one clock signal among first, second, third and fourth clock signals (CLK4) [Lee: Fig.15: clock signals CLK1, CLK2, CLK3 and CLK4], (iv) a first power source (VGH) [Lee: Fig.14: gate high voltage line VGH], and (v) a second power source (VGL) [Lee: Fig.14: gate low voltage line VGL] which has a voltage level lower than the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; Examiner: VGL represent a low voltage and VGH a high voltage, VGL is lower than VGL.],
wherein a first stage [Lee: Fig.13: first stage STG1], among the plurality of stages (STG1 to STG5) [Lee: Fig.13: stages STG1, STG2m STG3, STG4, ... STGm], includes:
a first node controller circuit (310) [Lee: Fig.14: first transistor T1, second transistor T2, third transistor T3] configured to control a voltage of a first node (Q1) [Lee: Fig.14: node QN] based on the input signal (VST) [Lee: Fig.14: start signal line VST; ¶ 0067: “The first transistor T1 may have a gate electrode connected to the start signal line VST and a first electrode connected to the gate low voltage line VGL”], the first clock signal (CLK1) [Lee: ¶ 0067: “ The second transistor T2 may have a gate electrode connected to the fourth clock signal line CLK4 … and a second electrode connected to a QN node QN”; Examiner: Lee’s CLK4 reads on the claimed first clock – the clock ordinals are nominal designations within the four-clock set, no inter-clock phase relationship being recited in claim 1.], the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0067: “The third transistor T3 may … a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QN node QN”], and a voltage of a second node (QB) [Lee: Fig.14: node QBN; ¶ 0067: “The third transistor T3 may have a gate electrode connected to a QB node QBN (an inverting node operating opposite to the QN node)”];
a second node controller circuit (320) [Lee: Fig.14: fourth transistor T4, fifth transistor T5, eighth transistor T8] configured to control the voltage of the second node (QB) [Lee: Fig.14: node QBN; ¶ 0076: “The QBN node QBN can be charged with the gate low voltage by the gate low voltage transferred through the fourth transistor T4”] based on the input signal [Lee: ¶ 0068: “The fifth transistor T5 may have a gate electrode connected to the start signal line VST … and a second electrode connected to the QB node QBN”], the fourth clock signal (CLK4) [Lee: ¶ 0068: “The fourth transistor T4 may have a gate electrode connected to the third clock signal line CLK3 … and a second electrode connected to the QB node QBN”; Examiner: Lee’s CLK3 reads on the claimed fourth clock – distinct from the first/second clocks used by the first node controller (CLK4) and output (CLK1)], the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0069: “The eighth transistor T8 may have a gate electrode connected to the QN node QN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QB node QBN”], and the second power source (VGL) [Lee: Fig.14: gate low voltage line VGL; ¶ 0068: “ The fourth transistor T4 may have … a first electrode connected to the gate low voltage line VGL”];
an output circuit (330) [Lee: Fig.14: sixth transistor T6_1, seventh transistor T7_1, output capacitor CQ1] configured to selectively output the second clock signal (CLK2) [Lee: Fig.15: G1 output; ¶ 0074: “ the low voltage of the first clock signal Clk1 can be output through the output terminal G10 via the turned on sixth transistor T6_1”; ¶ 0069: “a first electrode connected to the first clock signal line CLK1”; Examiner: Lee’s CLK1 reads on the claimed second clock] or a voltage of the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0076: “the gate high voltage … can be output through the output terminal G10 via the turned on seventh transistor T7_1”; ¶ 0069: “a first electrode connected to the gate high voltage line VGH”], based on a voltage of a third node (Q2) [Lee: Fig.14: gate of TG_1 at the second electrode of TBV: ¶ 0069: “The sixth transistor T6_1 may have a gate electrode connected to the second electrode of the stabilization transistor TBV”; Examiner: The node at TBV’s second electrode (the T6_1 gate) is a node distinct from the first node QN – it reads on the claimed third node, and the output pull-up is gated by it.] and the voltage of the second node (QB) [Lee: Fig.14: node QBN; ¶ 0069: “The seventh transistor T7_1 may have a gate electrode connected to the QB node QBN”];
and a reset circuit (340) [Lee: Fig.14: T9] configured to control the voltage of the first node (Q1) [Lee: Fig.14: node QN; ¶ 0071: “The ninth transistor T9 may have a gate electrode connected to the reset signal line QRST, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QN node QN”] based on the reset signal (QRST) [Lee: Fig.14: reset signal line QRST; ¶ 0071: “ a gate electrode connected to the reset signal line QRST”], the first power source (VGH) [Lee: Fig.14: gate high voltage line VGH; ¶ 0071: “a first electrode connected to the gate high voltage line VGH”],
However, Lee does not expressly disclose:
the reset circuit controlling the voltage of the second node (QB) based on the reset signal and the second power source.
Seo discloses:
the reset circuit (340) [Seo: Fig.7: QB node stabilizer 510] controlling the voltage of the second node (QB) [Seo: Fig.7: QB] based on the reset signal [Seo: Fig.7: RESET] and the second power source [Seo: Fig.7: GVSS3; ¶ 0167: “The second transistor T52 and the third transistor T53 are connected to and disposed between the QB node and the third low-potential voltage line for delivering the third low-potential voltage GVSS3”; ¶ 0168: “The second transistor T52 and the third transistor T53 discharge the QB node to the third low-potential voltage GVSS3 level in response to an input of the reset signal … he second transistor T52 can be turned on based on an input of the reset signal RESET”; Examiner: Seo’s transistor T52, gated by the reset signal, connects GVSS3 (second power source) and drives it there on reset, which is the reset path Lee lacks. Seo also resets the first node to the high rail on reset (¶ 0126: the line selector ”charges the Q node to a first high-potential voltage GVDD1 level … in response to an input of the reset signal RESET”), confirming a reset of both nodes by the reset signal.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add to Lee a reset transistor connecting the second power source (VGL) to the second node (QBN) and gated by the reset signal (QRST), as Seo teaches at ¶ 0168. Because Lee already uses QRST to reset its first node through T9 (¶ 0071) and Seo applies the reset signal to both nodes (¶ 0123, 0168), extending Lee’s existing reset signal to the second node is the predictable use of a known technique to improve a similar device in the same way among analogous GIP gate driver stages. The result is predictable because the added transistor works by the same mechanism as Lee’s existing T9, driving QBN to VGL on reset just as T9 drives QN to VGH, with no change to Lee’s principle of operation.
Regarding claim 13:
The limitations of claim 13 have been addressed in the discussion of claim 11 above.
Regarding claim 14:
The limitations of claim 14 have been addressed in the discussion of claim 4 above.
Regarding claim 15:
Lee in view of Seo discloses:
15. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 12,
wherein the first stage further includes: a bridge voltage transistor (Tbv) [Lee: Fig.14: stabilization transistor TBV”] which is connected between the first node (Q1) [Lee: Fig.14: node QN] and the third node (Q2) [Lee: Fig.14: gate of TG_1 at the second electrode of TBV: ¶ 0069: “The sixth transistor T6_1 may have a gate electrode connected to the second electrode of the stabilization transistor TBV”] and includes a gate electrode connected to a second power input terminal to which a voltage of the second power source (VGL) [Lee: Fig.14: gate low voltage line VGL] is supplied [Lee: Fig.14; ¶ 0068: “The stabilization transistor TBV may have a gate electrode connected to the gate low voltage line VGL”].
Regarding claim 16:
Lee in view of Seo discloses:
16. The gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 15,
wherein the bridge voltage transistor (Tbv) [Lee: Fig.14: stabilization transistor TBV”] is configured to maintain a turned-on state [Lee: ¶ 0072: “The stabilization transistor TBV can be turned on in response to a gate low voltage at a low voltage applied through the gate low voltage line VGL”; Examiner: Because TBV is a p-type and its gate is tied to the constant gate low voltage VGL, TBV is necessarily held in the on state at all times.].
Regarding claim 18:
Lee in view of Seo discloses:
18. A display device (1000) [Lee: Fig.1; ¶ 0027: “FIG. 1 is a block diagram schematically showing a light emitting display device”], comprising:
a display panel (100) [Lee: Fig.1: display panel 150] which includes a plurality of pixels (PX) [Lee: Fig.1: sub-pixel SP];
and a gate driver (300) [Lee: Fig.1: gate driver 130] according to claim 12,
wherein the plurality of gate signals (GS1 to GS5) [Lee: Fig.13: gate signals GL1, GL2, GL3, GL4 ... GLm] are output to the plurality of pixels (PX) [Lee: Fig.1: sub-pixel SP; ¶ 0031: “The gate driver 130 may supply gate signals to sub-pixels included in the display panel 150 through gate lines GL1 to GLm”].
Allowable Subject Matter
Claim(s) 5 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the first node controller circuit (310) includes a first transistor which is connected between (i) a first input terminal to which the input signal is supplied and (ii) the first node (Q1), and includes a gate electrode connected to a third input terminal to which the first clock signal (CLK1) is supplied”, in combination with the other recited claim features.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[Lee; Minho et al., US 20190172397 A1] discloses:
“A gate driver and a display device including the same are disclosed. The gate driver includes a plurality of stages. Each stage includes a transistor T6 outputting an emission signal of a gate-on voltage to a node Na while a node Q is activated, a transistor T7 outputting the emission signal of a gate-off voltage to the node Na while a node QB is activated, a Q controller controlling a voltage of the node Q depending on a clock signal ECLK1 and a clock signal ECLK2 that are in antiphase, and a voltage of a node Q′, a QB controller controlling a voltage of the node QB depending on the clock signal ECLK1, the voltage of the node Q, and the voltage of the node Q′, and a capacitor CQ connected between an input terminal of the clock signal ECLK1 and the node Q,” as recited in the abstract.
Inquiry
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/KOOSHA SHARIFI-TAFRESHI/Primary Examiner, Art Unit 2628
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