DETAILED ACTION
Allowable Subject Matter
The indicated allowability of claims 2-3, 6-8, 11 and 14-15 are withdrawn in view of the newly discovered reference(s). Rejections based on the newly cited reference(s) follow.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 5, 9 and 13objected to because of the following informalities:
Claim 5 recites “a data voltage supplied through the data line is stored in the first circuit part.” Claim 1, from which claim 5 depends, already recites “a data voltage.” The second recitation of “a data voltage” should refer back to the data voltage of claim 1. The Examiner suggests amending the phrase to read “the data voltage supplied through the data line is stored in the first circuit part.”
Claim 9 recites “light is emitted from the light emitting device by a current supplied from the driving transistor through the emission transistor.” Claim 1, from which claim 9 depends, already recites “a current flowing through the light emitting device.” The second recitation of “a current” should refer back to the current of claim 1. The Examiner suggests amending the phrase to read “light is emitted from the light emitting device by the current, the current being supplied from the driving transistor through the emission transistor.”
Claim 13 recites “the data voltage supplied through the data line is greater than 0.” The value is recited without a unit. The Examiner suggest amending the phrase to read “greater than 0 V.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 7-11, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Dong; Tian et al.; US 20220189401 A1].
Regarding claim 1:
Dong discloses:
1. (Currently Amended) A light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”], comprising:
a light emitting device (ED) [Dong: Fig. 3: light emitting device OLED] configured to emit light [Dong: ¶ 0002: “a light emitting device is driven to emit light by a current generated by a driving transistor in a saturated state”];
and a pixel driving circuit (PDC) [Dong: Fig. 3: pixel circuit] configured to drive the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED; ¶ 0040: “The driving transistor DTFT is configured to output a corresponding driving current in response to the control of the first and second control voltages, so as to drive the light emitting device OLED”],
wherein the pixel driving circuit (PDC) [Dong: Fig. 3: pixel circuit] comprises:
a first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2; Examiner: This group of elements is construed as the claimed first circuit part.] including a driving transistor (Tdr) [Dong: Fig. 3: driving transistor DTFT], the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] connected to a data line (DL) [Dong: Fig. 3: data line DATA; ¶ 0045: “a first electrode of the second transistor T2 is coupled to the data line DATA”] and connected to a first driving voltage line (1DVL) [Dong: Fig. 3: reference voltage terminal PVref; ¶ 0044: “a first electrode of the first transistor T1 is coupled to the reference voltage terminal PVref”; Examiner: The terminal that carries the reference voltage to the pixel circuit is a voltage line under the broadest reasonable interpretation (BRI).] to which a first driving voltage (Va) [Dong: ¶ 0038: “Vref is the reference voltage”] is for being supplied [Dong: ¶ 0036: “a reference voltage supplied by the reference voltage terminal PVref”];
a second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4] connected to the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED; ¶ 0064: “the second electrode of the fourth transistor T4 is coupled to the first electrode of the light emitting device OLED in the pixel circuit shown in FIG. 3”] and connected to a second driving voltage line (2DVL) [Dong: Fig. 3: reset voltage terminal PVinit; ¶ 0048: “a first electrode of the fourth transistor T4 is coupled to a reset voltage terminal PVinit”] to which a second driving voltage (Vb) [Dong: Fig. 3: ¶ 0051: “reset voltage Vinit”] is for being supplied [Dong: ¶ 0051: “a reset voltage Vinit supplied by the reset voltage terminal PVinit”];
and an emission transistor (T6) [Dong: Fig. 3: fifth transistor T5] connected between the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] and the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4; ¶ 0047: “a first electrode of the fifth transistor T5 is coupled to the second electrode of the driving transistor DTFT, and a second electrode of the fifth transistor T5 is coupled to the first electrode of the light emitting device OLED”; Examiner: T5 lies between the second electrode of DTFT, which belongs to the first circuit part, and the first electrode of the OLED, to which T4 is coupled.],
wherein a current flowing through the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED; ¶ 0058: “A current loop is formed from the first power terminal to the second power terminal via the third transistor T3, the driving transistor DTFT, the fifth transistor T5 and the light emitting device OLED”] is controlled by a data voltage (Vdata) and the first driving voltage (Va) [Dong: ¶ 0041: “ a calculation formula of a driving current I of the driving transistor DTFT when operating in a saturation region is as follows: I=k′(Vg−Vs−Vth)2=k′[(1−k)(Vdata−Vref)]2”; Examiner: The driving current is set by the data voltage Vdata and the reference voltage Vref supplied on PVref.].
Regarding claim 3:
Dong discloses:
3. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
wherein, during an initialization period (A) [Dong: Fig.4: reset preparation stage P1], the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] and the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4] are electrically connected by the emission transistor (T6) [Dong: Fig. 3: fifth transistor T5; ¶ 0067: “The first transistor T1, the fourth transistor T4 and the fifth transistor T5 are turned on”], and
the driving transistor (Tdr) [Dong: Fig.3: DTFT] and the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED] are initialized by the second driving voltage (Vb) [Dong: ¶ 0067: “the reset voltage terminal PVinit charges the second electrode of the driving transistor DTFT through the fourth transistor T4 and the fifth transistor T5”; ¶ 0064: “the reset circuit 4 can reset the second electrode of the driving transistor DTFT and can also reset the first electrode of the light emitting device OLED”].
Regarding claim 4:
Dong discloses:
4. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
wherein, during a threshold voltage sensing period (B) [Dong: threshold acquisition stage P2], the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] and the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4] are electrically separated by the emission transistor (T6) [Dong: Fig. 3: fifth transistor T5; ¶ 0069: “invalid voltages are supplied to the second control signal line SCAN2 and the fifth control signal line SCAN5”; Examiner: The invalid voltages on SCAN5 turns T5 off.], and a threshold voltage of the driving transistor (Tdr) [Dong: Fig.3: DTFT] is stored in the first circuit part (1CU) [Dong: Fig. 3: first capacitor C1 between nodes G and S; ¶ 0070: “acquisition of the threshold voltage is performed in this stage”; ¶ 0054: “the second electrode (the node S) of the driving transistor DTFT is charged to (Vref−Vth)”; Examiner: With node G at Vref and node S at Vref-Vth, C1 holds Vth.].
Regarding claim 5:
Dong discloses:
5. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
wherein, during a data writing period (C) [Dong: Fig.4: data writing stage P3], the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] and the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4] are electrically separated by the emission transistor (T6) [Dong: Fig. 3: fifth transistor T5; ¶ 0072: “invalid voltages are supplied to the first control signal line SCAN1, the third control signal line SCAN3, the fourth control signal line SCAN4 and the fifth control signal line SCAN5”], and
a data voltage (Vdata) supplied through the data line (DL) [Dong: Fig. 3: data line DATA] is stored in the first circuit part (1CU) [Dong: Fig. 3: node G and capacitors C1, C2; ¶ 0056: “The data line DATA writes the data voltage Vdata to the control electrode of the driving transistor DTFT through the second transistor T2”; ¶ 0073: “writing of the data voltage and adjustment of the voltage at the second electrode of the driving transistor DTFT are completed in this stage”].
Regarding claim 7:
Dong discloses:
7. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
wherein, during a reset period (D) [Dong: Fig.4: reset preparation stage P1; ¶ 0066: “in the reset preparation stage P1, effective voltages are supplied to the first control signal line SCAN1, the fourth control signal line SCAN4 and the fifth control signal line SCAN5”; Examiner: The claim does not specify when in a frame the reset period occurs, and a stage in which the circuit is reset is a reset period under the BRI.], the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] and the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4] are electrically connected by the emission transistor (T6) [Dong: Fig. 3: fifth transistor T5; ¶ 0067: “The first transistor T1, the fourth transistor T4 and the fifth transistor T5 are turned on”], and
the driving transistor (Tdr) [Dong: Fig.3: DTFT] and the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED] are initialized by the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4; ¶ 0064: “the reset circuit 4 can reset the second electrode of the driving transistor DTFT and can also reset the first electrode of the light emitting device OLED”].
Regarding claim 8:
Dong discloses:
8. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 7,
wherein, during the reset period (D) [Dong: Fig.4: reset preparation stage P1], the driving transistor (Tdr) [Dong: Fig.3: DTFT] and the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED] are initialized by the second driving voltage (Vb) [Dong: ¶ 0067: “the reset voltage terminal PVinit charges the second electrode of the driving transistor DTFT through the fourth transistor T4 and the fifth transistor T5”; Examiner: The fourth transistor T4 is coupled to the first electrode of the OLED in Fig.3, so the reset voltage from PVinit is applied to the OLED as well.].
Regarding claim 9:
Dong discloses:
9. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
wherein, during a light emission period (E) [Dong: Fig.4: light emission stage P4], the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] and the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4] are electrically connected by the emission transistor (T6) [Dong: Fig. 3: fifth transistor T5; ¶ 0074: “effective voltages are supplied to the third control signal line SCAN3 and the fifth control signal line SCAN5”], and
light is emitted from the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED] by a current supplied from the driving transistor (Tdr) [Dong: Fig.3: DTFT] through the emission transistor (T6) [Dong: Fig. 3: fifth transistor T5; ¶ 0075: “The third transistor T3, the driving transistor DTFT, the fifth transistor T5 and the light emitting device OLED are located in a same current path”].
Regarding claim 10:
Dong discloses:
10. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
wherein the pixel driving circuit (PDC) [Dong: Fig. 3: pixel circuit] further comprises an auxiliary emission transistor (T7) [Dong: Fig. 3: third transistor T3; ¶ 0058: “A current loop is formed from the first power terminal to the second power terminal via the third transistor T3, the driving transistor DTFT, the fifth transistor T5 and the light emitting device OLED”; Examiner: T3 is on in the light emission stage and carries the emission current.] connected between a first voltage supply line (PLA) supplied with a first voltage [Dong: Fig.3: first power terminal PVDD; ¶ 0061: “VDD is the power supply voltage supplied by the first power terminal”] and the driving transistor (Tdr) [Dong: Fig.3: DTFT].
Regarding claim 11:
Dong discloses:
11. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 10,
wherein the auxiliary emission transistor (T7) [Dong: Fig. 3: third transistor T3] is turned off during an initialization period (A) [Dong: Fig.4: reset preparation stage P1; ¶ 0068: “Whether an effective voltage is supplied to the third control signal line SCAN3 affects nothing in this stage, and thus is not limited”; Examiner: Dong discloses two alternative for P1, an effective voltage on SCAN3 or an invalid one, and the invalid voltage turns T3 off.] in which the driving transistor (Tdr) [Dong: Fig.3: DTFT] and the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED] are initialized by the second driving voltage (Vb) [Dong: ¶ 0067: “the reset voltage terminal PVinit charges the second electrode of the driving transistor DTFT through the fourth transistor T4 and the fifth transistor T5”].
Regarding claim 16:
Dong discloses:
16. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
wherein the second circuit part (2CU) [Dong: Fig. 3: reset circuit 4 including fourth transistor T4] comprises:
a fifth transistor (T5) [Dong: Fig.3: fourth transistor T4] connected between the second driving voltage line (2DVL) [Dong: Fig. 3: reset voltage terminal PVinit] and a first terminal of the light emitting device (ED) [Dong: Fig. 3: first electrode of light emitting device OLED; ¶ 0064: “the second electrode of the fourth transistor T4 is coupled to the first electrode of the light emitting device OLED in the pixel circuit shown in FIG. 3”];
and a third capacitor connected between the first terminal of the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED] and a second terminal of the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED],
wherein the emission transistor (T6) [Dong: Fig. 3: fifth transistor T5] is connected between the first circuit part (1CU) [Dong: Fig. 3: driving transistor DTFT, first transistor T1, second transistor T2, first capacitor C1 and second capacitor C2] and the first terminal of the light emitting device (ED) [Dong: Fig. 3: light emitting device OLED].
Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Son; Ki Min et al.; US 20240257749 A1].
Regarding claim 14:
Son discloses:
14. (Currently Amended) A light emitting display apparatus [Son: ¶ 0056: “the display device”], comprising:
a light emitting device (ED) [Son: Fig.6: light emitting element EL] configured to emit light [Son: ¶ 0121: “The light emitting element EL may be emitted according to the current from the driving element DT during the emission period EMIS after the boosting period BOOST”];
and a pixel driving circuit (PDC) [Son: Fig.6: pixel circuit] configured to drive the light emitting device (ED) [Son: Fig.6: light emitting element EL; ¶ 0110: “ the pixel circuit includes a light emitting element EL, a driving element DT driving the light emitting element EL”],
wherein the pixel driving circuit (PDC) [Son: Fig.6: pixel circuit] comprises:
a first circuit part (1CU) [Son: Fig. 6: driving element DT, first switch element T01, third switch element T03, fourth switch element T04, first capacitor Cst and second capacitor Ca; Examiner: This group of elements is construed as the claimed first circuit part.] including a driving transistor (Tdr) [Son: Fig.6: driving element DT], the first circuit part (1CU) [Son: Fig. 6: driving element DT, first switch element T01, third switch element T03, fourth switch element T04, first capacitor Cst and second capacitor Ca] connected to a data line (DL) [Son: Fig.6: data line DL; ¶ 0132: “The third switch element T03 is connected between the data line DL, to which the data voltage Vdata of the pixel data is applied, and the second node DTG”] and connected to a first driving voltage line (1DVL) [Son: Fig.6: third constant voltage line PL3; ¶ 0133: “The fourth switch element T04 is connected between the third constant voltage line PL3, to which the initialization voltage Vinit is applied, and the second node DTG”] to which a first driving voltage (Va) [Son: Fig.6: initialization voltage Vinit] is for being supplied [Son: ¶ 0133: “the third constant voltage line PL3, to which the initialization voltage Vinit is applied”];
a second circuit part (2CU) [Son: Fig. 6: fifth switch element T05] connected to the light emitting device (ED) [Son: Fig. 6: light emitting element EL; ¶ 0123: “The anode electrode of the light emitting element EL may be connected to the fourth node n4”] and connected to a second driving voltage line (2DVL) [Son: Fig.6: fourth constant voltage line PL4; ¶ 0134: “The fifth switch element T05 is connected between the fourth constant voltage line PL4, to which the reference voltage Vref is applied, and the fourth node n4”] to which a second driving voltage (Vb) [Son: Fig.6: reference voltage Vref] is for being supplied [Son: ¶ 0134: “the fourth constant voltage line PL4, to which the reference voltage Vref is applied”];
and an emission transistor (T6) [Son: Fig.6: second switch element T02] connected between the first circuit part (1CU) [Son: Fig. 6: driving element DT, first switch element T01, third switch element T03, fourth switch element T04, first capacitor Cst and second capacitor Ca] and the second circuit part (2CU) [Son: Fig. 6: fifth switch element T05; ¶ 0131: “The second switch element T02 is connected between the third node DTS and the fourth node n4 and is turned on based on the gate-on voltage VGH of the second EM signal EM2”; Examiner: The third node DTS is the second electrode of the driving element DT, and the fourth node n4 is the node to which T05 is connected.], and
wherein the light emitting device (ED) [Son: Fig.6: light emitting element EL] is initialized by the second circuit part (2CU) [Son: Fig.6: fifth switch element T05; ¶ 0134: “When the fifth switch element T05 is turned on, the reference voltage Vref is applied to the fourth node n4”; Examiner: Setting the anode node n4 to the reference voltage Vref through T05 initializes the light emitting element.] during an initialization period (A) [Son: Fig.7: initialization period INI] in which the driving transistor (Tdr) [Son: Fig.6: driving element DT] is initialized [Son: Fig.7: SENSE at VGH in period INI; ¶ 0120: “A voltage of the third scan signal SENSE is the gate-on voltage VGH during the initialization period INI, the sensing period SEN, the data writing period WR, and the anode reset period AR, and is the gate-off voltage VGL during the emission period EMIS”; ¶ 0121: “During the initialization period INI, the initialization voltage Vinit is applied to a second node DTG and the reference voltage Vref is applied to a third node DTS to initialize the capacitor Cst and a gate-source voltage Vgs of the driving element DT”],
during a threshold voltage sensing period (B) [Son: Fig. 7: sensing period SEN] in which a threshold voltage of the driving transistor (Tdr) [Son: Fig. 6: driving element DT] is sensed [Son: Fig. 7: SENSE at VGH in period SEN; ¶ 0121: “During the sensing period SEN, a threshold voltage Vth of the driving element DT is sampled and stored in the first capacitor Cst”],
during a data writing period (C) [Son: Fig. 7: data writing period WR] in which a data voltage (Vdata) is supplied through the data line (DL) [Son: Fig. 6: data line DL; Fig.7: SENSE at VGH in period WR; ¶ 0118: “A voltage of the first scan signal SCAN is generated as a pulse of the gate-on voltage VGH synchronized with the data voltage Vdata of the pixel data during the data writing period WR”], and
during a reset period (D) [Son: Fig.7: anode reset period AR] between the data writing period (C) [Son: Fig. 7: data writing period WR] and a light emission period (E) [Son: Fig. 7: emission period EMIS] in which light is emitted [Son: Fig. 7: SENSE at VGH in period AR, which lies between periods WR and EMIS; ¶ 0115: “The pixel circuit disposed in each of the sub-pixels may be driven in the following order: the initialization period INI, the sensing period SEN, the data writing period WR, the anode reset period AR, and the emission period EMIS”; ¶ 0121: “During the anode reset period AR, the reference voltage Vref is applied to the third node DTS and a fourth node n4”; Examiner: The anode reset period AR is the claimed reset period, and the emission period EMIS is the claimed light emission period.].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Dong; Tian et al.; US 20220189401 A1] in view of [Zhu; Renyuan et al.; US 20170278457 A1].
Regarding claim 6:
Dong discloses:
6. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 5,
However, Dong does not expressly disclose:
wherein, during the data writing period (C), the light emitting device (ED) is initialized by the second circuit part (2CU).
Zhu discloses:
wherein, during the data writing period (C) [Zhu: Fig.3B: second phase P2; ¶ 0074: “in a threshold detecting phase, the third transistor is turned on in response to the signal input to the gate of the third transistor and transmits the data signal voltage to the organic light-emitting pixel driving circuit”; Examiner: The phase in which the data signal voltage is transmitted into the pixel circiot is a data writing period.], the light emitting device (ED) [Zhu: Fig.3A: light-emitting element EL] is initialized by the second circuit part (2CU) [Zhu: Fig.3A: transistor T1 between first initialization signal line V1 and the anode of EL; ¶ 0071: “the driving circuit may always reset the anode of the light-emitting element EL in the first phase P1, second phase P2 and third phase P3”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Dong to keep its reset transistor T4 on during the data writing stage, so that the anode of the OLED is held at the reset voltage in every stage before emission as taught by Zhu (¶ 0071), in order to ensure that the light emitting element does not emit light in those stages, which is the benefit Zhu states (¶ 0071). Dong already holds T4 on through its first two stages and turns its emission transistor T5 off in the data writing stage (¶ 0072), so T4 is isolated from the driving transistor in that stage and extending its on time would not disturb the data writing. The modification changes only the timing of an existing control signal, and the result would have been predictable.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Dong; Tian et al.; US 20220189401 A1] in view of [Hong; Soonhwan et al.; US 20200152130 A1].
Regarding claim 12:
Dong discloses:
12. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 1,
However, Dong does not expressly disclose:
wherein the second driving voltage (Vb) is lower than an anode voltage that causes the light emitting device (ED) to emit light.
Dong discloses:
wherein the second driving voltage (Vb) is lower than an anode voltage that causes the light emitting device (ED) [Hong: Fig.4: OLED] to emit light [Hong: ¶ 0054: “The sixth transistor T6 applies the initialization voltage Vini to the anode of the OLED in response to the (n-2)-th scan signal SCAN(n-2)”; ¶ 0054: “The initialization voltage Vini is selected within a voltage range sufficiently lower than the operation voltage of the OLED and can be set to be equal to or lower than the low potential voltage ELVSS”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to set the reset voltage that Dong applies to the first electrode of its OLED lower than the operation voltage of the OLED, as taught by Hong (¶ 0054), so that the OLED does not emit light while the reset voltage is applied to its anode. Dong applies its reset voltage directly to the OLED’s first electrode and does not state its level relative to the OLED’s emission voltage, so one of ordinary skill had to select it. Hong shows the level used for the same anode initialization operation, and applying that level changes nothing else in Dong’s circuit, so the results would have been predictable.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Dong; Tian et al.; US 20220189401 A1] in view of [Kang et al., “An a-IGZO TFT-Based AMOLED Pixel Circuit Employing Stable Mobility Compensation Suppressing Degradation of Detected VTH,” IEEE Journal of the Electron Devices Society, vol. 12, pp. 7-13, published November 10, 2023; herein “Kang”].
Regarding claim 13:
Dong discloses:
13. (Original) The light emitting display apparatus [Dong: ¶ 0085: “a display device, including the above display substrate”] of claim 5,
wherein the data voltage (Vdata) supplied through the data line (DL) [Dong: Fig. 3: data line DATA; ¶ 0059: “The data line DATA writes the data voltage Vdata to the control electrode of the driving transistor DTFT through the second transistor T2”]
However, Dong does not expressly disclose:
wherein the data voltage (Vdata) supplied through the data line (DL) is greater than 0.
Kang discloses:
wherein the data voltage (Vdata) supplied through the data line (DL) [Kang: Fig.1(a): DATA line] is greater than 0 [Kang: p.9: “VDATA ranges from 1 V to 10 V”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to supply data voltages greater than 0 in Dong, as in Kang (p. 9). Dong’s transistors maybe N-type (¶ 0082) and Dong teaches that the data voltage has a lower limit that rises with the reference voltage (¶ 0061), but Dong gives no values, so one of ordinary skill had to select a data voltage range. Kang shows that a positive data voltage range was known, working choice for an N-type oxide transistor OLED pixel circuit whose driving transistor gate is likewise initialized by a reference voltage. Using that range in Dong is selection of a known operating range for the same purpose, with the predictable result or normal grayscale driving.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Kang et al., “An a-IGZO TFT-Based AMOLED Pixel Circuit Employing Stable Mobility Compensation Suppressing Degradation of Detected VTH,” IEEE Journal of the Electron Devices Society, vol. 12, pp. 7-13, published November 10, 2003; herein “Kang”] in view of [Zhu; Renyuan et al.; US 20170278457 A1].
Regarding claim 15:
Kang discloses:
15. (Currently Amended) A light emitting display apparatus [Kang: Fig.1(a): “Proposed 7T2C AMOLED pixel circuit structure”], comprising:
a light emitting device (ED) [Kang: Fig.1(a): OLED] configured to emit light [Kang: p. 9: “the DRT flows a constant data current to the OLED”];
and a pixel driving circuit (PDC) [Kang: Fig.1(a): pixel circuit of DRT, T1 to T6, C1 and C2; p.8: “The proposed pixel circuit consists of six switching TFTs (T1-T6)”] configured to drive the light emitting device (ED) [Kang: Fig.1(a): OLED],
wherein the pixel driving circuit (PDC) [Kang: Fig.1(a): pixel circuit of DRT, T1 to T6, C1 and C2] comprises: a first circuit part (1CU) [Kang: Fig.1(a): DRT, T1 to T5, C1 an C2] including a driving transistor (Tdr) [Kang: Fig.1(A): DRT], the first circuit part (1CU) [Kang: Fig.1(a): DRT, T1 to T5, C1 an C2] connected to a data line (DL) [Kang: Fig.1(a): DATA line, connected at T2] and connected to a first driving voltage line (1DVL) to which a first driving voltage (Va) is for being supplied [Kang: Fig.1(a): supply terminal of T4; Fig.10(a): GND line; p.8: “the voltage of nodes A, B, and C is initialized to VREF, 0 V, and 0 V, respectively”; Examiner: The terminal of T4 opposite Node C is the GND line of Fig.10(a), which supplies the 0 V to which Node C is set when T4 is on.];
and an emission transistor (T6) [Kang: Fig.1(a): T6, gate EM[N]] connected between the first circuit part (1CU) [Kang: Fig.1(a): Node C of the first circuit part]
wherein the first circuit part (1CU) [Kang: Fig.1(a): DRT, T1 to T5, C1 an C2] comprises:
the driving transistor (Tdr) [Kang: Fig.1(a): DRT] including a first terminal [Kang: Fig.1(a): upper terminal of DRT] connected to a first voltage supply line (PLA) [Kang: Fig.1(a): ELVDD; Examiner: The upper terminal of DRT is connected to ELVDD through T5, and the specification defines “connected” to include connection through an intervening element (PGPUB ¶ 0035).];
a first transistor (T1) [Kang: Fig.1(a): T2] including a first terminal [Kang: Fig.1(a): terminal of T2 on the DATA line] connected to the data line (DL) [Kang: Fig.1(a): DATA line];
a first capacitor (C1) [Kang: Fig.1(a): C1] connected between a gate of the driving transistor (Tdr) [Kang: Fig.1(a): Node A, gate of DRT] and a second terminal of the first transistor (T1) [Kang: Fig.1(a): Node B, terminal of T2 opposite the DATA line];
a second transistor (T2) [Kang: Fig.1(a): T1] connected between a reference voltage supply line (RVL) [Kang: Fig.1(a): REF line] and the gate of the driving transistor (Tdr) [Kang: Fig.1(a): Node A, gate of DRT];
a third transistor (T3) [Kang: Fig.1(a): T3] connected between the second terminal of the first transistor (T1) [Kang: Fig.1(a): Node B] and a second terminal of the driving transistor (Tdr) [Kang: Fig.1(a): Node C, lower terminal of DRT];
a second capacitor (C2) [Kang: Fig.1(a): C2] connected between the second terminal of the first transistor (T1) [Kang: Fig.1(a): Node B] and the second terminal of the driving transistor (Tdr) [Kang: Fig.1(a): Node C];
and a fourth transistor (T4) [Kang: Fig.1(a): T4] connected between the first driving voltage line (1DVL) [Kang: Fig.1(a): supply terminal of T4; Fig.10(a): GND line] and the second terminal of the driving transistor (Tdr) [Kang: Fig.1(a): Node C], and
wherein the emission transistor (T6) [Kang: Fig.1(a): T6] is connected between the second terminal of the driving transistor (Tdr) [Kang: Fig.1(a): Node C; p. 9: “T6 is turned on and node C is connected to the anode of the OLED”]
However, Kang does not expressly disclose:
a second circuit part connected to the light emitting device and connected to a second driving voltage line to which a second driving voltage is for being supplied;
an emission transistor connected between the first circuit part and the second circuit part;
the emission transistor is connected between the second terminal of the driving transistor and the second circuit part.
Zhu discloses:
a second circuit part (2CU) [Zhu: Fig. 3A: transistor T1] connected to the light emitting device (ED) [Zhu: Fig.3A: anode of light-emitting element EL] and connected to a second driving voltage line (2DVL) to which a second driving voltage is for being supplied [Zhu: Fig.3A: first initialization signal line V1; ¶ 0071: “the driving circuit may always reset the anode of the light-emitting element EL in the first phase P1, second phase P2 and third phase P3”; Examiner: T1 applies the voltage on V1 to the anode to reset it.];
an emission transistor (T6) [Zhu: Fig.3A: seventh transistor T7] connected between the first circuit part (1CU) [Zhu: Fig.3A: driving transistor DT and the elements on its source node N1] and the second circuit part (2CU) [Zhu: Fig.3A: transistor T1 at the anode];
the emission transistor (T6) [Zhu: Fig.3A: seventh transistor T7] is connected between the second terminal of the driving transistor (Tdr) [Zhu: Fig.3A: node N1, source of DT] and the second circuit part (2CU) [Zhu: Fig.3A: transistor T1 at the anode].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kang to include the anode reset transistor and initialization signal line of Zhu, connected to the anode of Kang’s OLED on the anode side the emission transistor T6, in order to reset the anode during the non-emission phases and ensure that the light emitting element does not emit light in those phases, as taught by Zhu (¶ 0071). Kang’s T6 is off from the reset stage through the mobility compensation stage (p. 8), so Kang’s anode is isolated and is not otherwise reset in those stages. Zhu places its reset transistor at the same location, on the anode side of an emission transistor between the driving transistor’s source and the anode. The added transistor would therefore perform in Kang the same function it performs in Zhu, Kang’s elements would operate unchanged because T6 isolates them from the anode during those stages, and the result would have been predictable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[Yuan; Changlong et al., US 20250104641 A1] discloses:
“A pixel circuit, a pixel driving method and a display device. The pixel circuit includes a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a data writing circuit, and a compensation control circuit. The data writing circuit controls writing of a data voltage on a data line into a data writing node under control of a scanning signal. The compensation control circuit controls whether a second node is connected with or disconnected from a compensation node under control of a first reset signal. The compensation node is electrically connected to a third node, and/or, the compensation node is electrically connected to a second terminal of the driving circuit. The present disclosure can achieve high-frequency driving under the premise of sufficient compensating for the threshold voltage of the driving transistor included in the driving circuit,” as recited in the abstract.
Inquiry
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/KOOSHA SHARIFI-TAFRESHI/Primary Examiner, Art Unit 2628
