Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Claim(s) 1-25 is/are pending in the application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted October 30, 2025, June 22, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 13-17, 12-22 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gui et al, U.S. Patent Publication No. 20240420644.
Consider claim 1, Gui teaches a display device (see Gui figure 2, element 14) comprising:
a pixel circuit configured to drive a light emitting element (see Gui figure 2, element 22, detailed in figure 3); and
a scan driving circuit configured to supply a scan signal to the pixel circuit (see Gui figure 2, element 34 and paragraphs 0032-0036 where Gate driver circuitry 34 (sometimes referred to as horizontal line control circuitry or row driver circuitry) may be implemented as part of an integrated circuit and/or may be implemented using thin-film transistor circuitry. Horizontal/row control lines G in display 14 may carry gate line signals (scan line control signals), emission enable control signals, and/or other horizontal control signals for controlling the pixels of each row. There may be any suitable number of horizontal control signals per row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.). Gate driver circuitry 34 may include multiple gate driver circuits (e.g., gate drivers 100-1, 100-2, and so on) connected in a chain. For example, each gate driver may be configured to generate one or more scan signals and/or carry signals that are fed forward to a succeeding gate driver in the chain and/or that are fed back to a preceding gate driver in the chain),
wherein the scan driving circuit includes: a logic portion configured to receive a plurality of clock signals and output a logic signal through a logic output terminal (see Gui figure 10A, element 300); and
an inverter configured to receive the logic signal and output the scan signal with a phase of the logic signal inverted through a gate output terminal (see Gui figure 10A, element 302),
wherein the inverter includes a first inverter transistor (see Gui figure 10A, element 310) and a second inverter transistor (see Gui figure 10A, element 312),
the first inverter transistor being an n-type transistor and the second inverter transistor being a p-type transistor (see Gui paragraph 0076 where subcircuit 302 may include an n-type semiconducting oxide transistor 310 and a p-type silicon transistor 312 coupled in series between power supply lines 306 and 308),
wherein a gate electrode of the first inverter transistor and a gate electrode of the second inverter transistor are both connected to the logic output terminal of the logic portion (see Gui figure 10A, element Z, CARRY(n) is connected to gate electrode of both 310 and 312),
wherein the first inverter transistor and the second inverter transistor are both connected to the gate output terminal (see Gui figure 10A, element OUT(n) and
wherein the first inverter transistor includes an oxide semiconductor (see Gui paragraph 0076 where n-type semiconducting oxide transistor 310 is disclosed).
Consider claim 2, Gui teaches all the limitations of claim 1 and further teaches 2. wherein the logic portion is further configured to: supply the logic signal having a gate high voltage to the gate electrode of the first inverter transistor and the logic signal having a gate low voltage to the gate electrode of the first inverter transistor (see Gui figure 10B element CARRY(n), OUT(n)),
wherein a period during which the gate high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor is longer than a period during which the gate low voltage of the logic signal is supplied to the gate electrode of the first inverter transistor (see Gui figure 10B element CARRY(n), OUT(n)).
Consider claim 3, Gui teaches all the limitations of claim 1 and further teaches wherein the second inverter transistor is a low temperature polysilicon (LTPS) transistor (see Gui paragraph 0035 where “silicon transistor” can refer to and be defined herein as a thin-film transistor having a polysilicon channel region deposited using a low temperature process sometimes referred to as LTPS or low-temperature polysilicon and paragraph 0076 where p-type silicon transistor 312 is disclosed).
Consider claim 4, Gui teaches all the limitations of claim 1 and further teaches wherein the first inverter transistor includes a gate electrode connected to the logic output terminal of the logic portion (see Gui figure 10A, element Z, 310),
a first end configured to receive a gate low voltage (see Gui figure 10A, element VGL), and
a second end connected to the gate output terminal (see Gui figure 10A, element OUT(n)), and
wherein the second inverter transistor includes a gate electrode connected to the logic output terminal of the logic portion (see Gui figure 10A, element Z, 312),
a first end configured to receive a gate high voltage (see Gui figure 10A, element VGH), and
a second end connected to the gate output terminal (see Gui figure 10A, element OUT(n)i).
Consider claim 5, Gui teaches all the limitations of claim 1 and further teaches wherein the first inverter transistor is configured to be turned on by the logic signal having a gate high voltage to output the scan signal having a gate low voltage to the gate output terminal (see Gui paragraph 0076, 0080 and figure 10B, CARRY(n), OUT(n) where when CARRY is high, OUT is low by virtue of turning on the n-type transistor 310), and
wherein the second inverter transistor is configured to be turned on by the logic signal having a gate low voltage to output the scan signal having the gate high voltage to the gate output terminal (see Gui paragraph 0076, 0080 and figure 10B, CARRY(n), OUT(n) where when CARRY is low, OUT is high by virtue of turning on the p-type transistor 312).
Consider claim 6, Gui teaches all the limitations of claim 1 and further teaches wherein the logic portion includes a plurality of logic transistors (see Gui figure 10A, element 314, 316, 318, 320, 322, 324, 326, 328), and
wherein the plurality of logic transistors include one or more low temperature polysilicon (LTPS) transistors (see Gui paragraph 0078 where silicon transistors 314, 316, 318, 320, 322, 324, 326, and 328 (e.g., p-type LTPS transistors) are disclosed).
Consider claim 7, Gui teaches all the limitations of claim 1 and further teaches wherein the logic portion includes: a first logic transistor having a gate electrode connected to a Q-node (see Gui figure 10A, element 314, Q), a first end configured to receive a first clock signal (see Gui figure 10A, element CLK1), and a second end connected to the logic output terminal (see Gui figure 10A, element Z);
a second logic transistor having a gate electrode connected to a QB-node (see Gui figure 10A, element 316, QB), a first end configured to receive a gate high voltage (see Gui figure 10A, element VGH), and a second end connected to the logic output terminal (see Gui figure 10A, element Z);
a third logic transistor having a gate electrode configured to receive a second clock signal (see Gui figure 10A, element 320, CLK2), a first end configured to receive a start signal (see Gui figure 10A, element CARRY(n-1)), and a second end connected to the Q-node (see Gui figure 10A, element Q2 connected to Q via 318 a p-type transistor with a VGL gate voltage);
a fourth logic transistor having a gate electrode connected to the Q-node (see Gui figure 10A, element 326, Q2 connected to Q via 318 a p-type transistor with a VGL gate voltage), a first end configured to receive the second clock signal (see Gui figure 10A, element CLK2), and a second end connected to the QB-node (see Gui figure 10A, element QB);
a fifth logic transistor having a gate electrode configured to receive the second clock signal (see Gui figure 10A, element 328, CLK2), a first end configured to receive a gate low voltage (see Gui figure 10A, element VGL), and a second end connected to the QB-node (see Gui figure 10A, element QB);
a sixth logic transistor having a gate electrode connected to the QB-node (see Gui figure 10A, element 324, QB), a first end configured to receive a gate high voltage (see Gui figure 10A, element VGH), and a second end configured to output the gate high voltage(see Gui figure 10A, element 324 where when turned on will output VGL);
a seventh logic transistor having a gate electrode configured to receive the first clock signal (see Gui figure 10A, element 322, CLK1), a first end connected to the sixth logic transistor (see Gui figure 10A, element 324), and a second end connected to the Q-node (see Gui figure 10A, element Q2 connected to Q via 318 a p-type transistor with a VGL gate voltage);
a first capacitor having a first end connected to the Q-node (see Gui figure 10A, element CQ, Q), and a second end connected to the logic output terminal (see Gui figure 10A, element Z); and
a second capacitor having a first end connected to the QB-node (see Gui figure 10A, element CQB), and a second end configured to receive the gate high voltage (see Gui figure 10A, element VGH).
Consider claim 8, Gui teaches all the limitations of claim 7 and further teaches wherein the logic portion further includes: an eighth logic transistor having a gate electrode configured to receive the gate low voltage (see Gui figure 10A, element 318, VGL), the eight logic transistor being connected between the gate electrode of the first logic transistor and the second end of the third logic transistor (see Gui figure 10A, element 314, 318, Q2, Q, 320).
Consider claim 9, Gui teaches all the limitations of claim 7 and further teaches wherein in a first period, the start signal and the second clock signal have a logic low voltage, and the first clock signal has a logic high voltage (see Gui figure 10B reproduced below, element CARRY(n-1), CLK2, CLK1, P1),
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wherein in a second period after the first period, the first clock signal has a logic low voltage, and the second clock signal has a logic high voltage (see Gui figure 10B, reproduced above, element CLK2, CLK1),
wherein in a third period after the second period, the second clock signal has a logic low voltage, and the first clock signal and the start signal have a logic high voltage (see Gui figure 10B reproduced above, element CLK2, CLK1, CARRY(n), P3), and
wherein in a fourth period after the third period, the first clock signal has a logic low voltage, and the second clock signal has a logic high voltage (see Gui figure 10B reproduced above, CLK1, CLK2, P4).
Consider claim 13, Shin teaches a scan driving circuit (see Shin figure 1, element 110 and paragraphs 0052-0053 where scan driver 110 may sequentially supply the scan signals to the scan lines S11 to S1n. When the scan signals are sequentially supplied to the scan lines S11 to S1n, the pixels PXL may be sequentially selected in the unit of a horizontal line) comprising:
a logic portion configured to receive a plurality of clock signals and output a logic signal through a logic output terminal (see Shin figure 3, element 210 detailed in figure 6 where figure 6, elements CLK1, CLK2, So, 211) to supply a scan signal to a pixel circuit (see Shin figure 1, element PXL, detailed in figure 2); and
an inverter configured to receive the logic signal and output the scan signal with a phase of the logic signal inverted through a gate output terminal (see Shin figure 3, element 220 detailed in figure 4),
wherein the inverter includes a first inverter transistor (see Shin figure 4, element M2) and a second inverter transistor (see Shin figure 4, element M1),
the first inverter transistor being an n-type transistor and the second inverter transistor being a p-type transistor (see Shin paragraphs 0113-0133 specifically for example paragraph 0114 where a first transistor M1 and a second transistor M2 which are complementarily operated and figure 4 where M1 and M2 are illustrated as p-type and n-type transistors respectively), and
the first inverter transistor and the second inverter transistor are both connected to the gate output terminal (see Shin figure 3, element 210, So, 220, figure 4, element M1, M2, So is input to gate electrode of both), and
wherein the first inverter transistor includes an oxide semiconductor (see Shin paragraphs 0113-0133 specifically for example paragraph 0129 where the inverter 220 of the present invention includes the oxide semiconductor transistor M2 having a small leakage current).
Shin is silent regarding driving circuit unit being a logic portion. In a related field of endeavor, Cheng teaches that a driving circuit includes a shift register is widely employed digital logic circuit (see Cheng paragraph 0004) so as to provide scan driving signals to a display. One of ordinary skill would have found it obvious that Shin’s teaching of a driving circuit to sequentially output signals to generate scan signals as corresponding to a logic circuit in view of Cheng’s teaching that a shift register is a digital logic circuit.
Claims 14-17 recite similar claim limitations as claims 2-5, and thus are rejected under similar rational as claims 2-5 detail above.
Consider claim 21, Shin teaches a scan driving circuit (see Shin figure 1, element 110 and paragraphs 0052-0053 where scan driver 110 may sequentially supply the scan signals to the scan lines S11 to S1n. When the scan signals are sequentially supplied to the scan lines S11 to S1n, the pixels PXL may be sequentially selected in the unit of a horizontal line) comprising:
a logic portion configured to receive a plurality of clock signals and output a logic signal through a logic output terminal (see Shin figure 3, element 210 detailed in figure 6 where figure 6, elements CLK1, CLK2, So, 211); and
an inverter configured to receive the logic signal and output the scan signal with a phase of the logic signal inverted through a gate output terminal (see Shin figure 3, element 220 detailed in figure 4),
wherein the inverter includes a first inverter transistor (see Shin figure 4, element M2) and a second inverter transistor (see Shin figure 4, element M1),
the first inverter transistor being an n-type transistor and the second inverter transistor being a p-type transistor (see Shin paragraphs 0113-0133 specifically for example paragraph 0114 where a first transistor M1 and a second transistor M2 which are complementarily operated and figure 4 where M1 and M2 are illustrated as p-type and n-type transistors respectively).
Shin is silent regarding driving circuit unit being a logic portion. In a related field of endeavor, Cheng teaches that a driving circuit includes a shift register is widely employed digital logic circuit (see Cheng paragraph 0004) so as to provide scan driving signals to a display. One of ordinary skill would have found it obvious that Shin’s teaching of a driving circuit to sequentially output signals to generate scan signals as corresponding to a logic circuit in view of Cheng’s teaching that a shift register is a digital logic circuit.
Consider claim 22, Shin as modified by Cheng teaches all the limitations of claim 21 and further teaches wherein the first inverter transistor is an oxide thin film transistor (see Shin paragraphs 0113-0133 specifically for example paragraph 0129 where the inverter 220 of the present invention includes the oxide semiconductor transistor M2 having a small leakage current), and
the second inverter transistor is a low temperature polysilicon (LTPS) thin film transistor (see Shin paragraph 0117 where first transistor M1 may be formed of a P-type polysilicon transistor and paragraph 0077 where polysilicon transistor may be set with low temperature polysilicon).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 13, 15-17, 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al, U.S. Patent Publication No. 20180190204 in view of Cheng et al, U.S. Patent Publication No. 20100045657.
Consider claim 1, Shin teaches a display device (see Shin figure 1, element 10) comprising:
a pixel circuit configured to drive a light emitting element (see Shin figure 1, element PXL, detailed in figure 2); and
a scan driving circuit configured to supply a scan signal to the pixel circuit (see Shin figure 1, element 110 and paragraphs 0052-0053 where scan driver 110 may sequentially supply the scan signals to the scan lines S11 to S1n. When the scan signals are sequentially supplied to the scan lines S11 to S1n, the pixels PXL may be sequentially selected in the unit of a horizontal line),
wherein the scan driving circuit includes: a logic portion configured to receive a plurality of clock signals and output a logic signal through a logic output terminal (see Shin figure 3, element 210 detailed in figure 6 where figure 6, elements CLK1, CLK2, So, 211); and
an inverter configured to receive the logic signal and output the scan signal with a phase of the logic signal inverted through a gate output terminal (see Shin figure 3, element 220 detailed in figure 4),
wherein the inverter includes a first inverter transistor (see Shin figure 4, element M2) and a second inverter transistor (see Shin figure 4, element M1),
the first inverter transistor being an n-type transistor and the second inverter transistor being a p-type transistor (see Shin paragraphs 0113-0133 specifically for example paragraph 0114 where a first transistor M1 and a second transistor M2 which are complementarily operated and figure 4 where M1 and M2 are illustrated as p-type and n-type transistors respectively),
wherein a gate electrode of the first inverter transistor and a gate electrode of the second inverter transistor are both connected to the logic output terminal of the logic portion (see Shin figure 3, element 210, So, 220, figure 4, element M1, M2, So is input to gate electrode of both),
wherein the first inverter transistor and the second inverter transistor are both connected to the gate output terminal (see Shin figure 4, element M1, M2, Nc, S1i), and
wherein the first inverter transistor includes an oxide semiconductor (see Shin paragraphs 0113-0133 specifically for example paragraph 0129 where the inverter 220 of the present invention includes the oxide semiconductor transistor M2 having a small leakage current).
Shin is silent regarding driving circuit unit being a logic portion. In a related field of endeavor, Cheng teaches that a driving circuit includes a shift register is widely employed digital logic circuit (see Cheng paragraph 0004) so as to provide scan driving signals to a display. One of ordinary skill would have found it obvious that Shin’s teaching of a driving circuit to sequentially output signals to generate scan signals as corresponding to a logic circuit in view of Cheng’s teaching that a shift register is a digital logic circuit.
Consider claim 3, Shin as modified by Cheng teaches all the limitations of claim 1 and further teaches wherein the second inverter transistor is a low temperature polysilicon (LTPS) transistor (see Shin paragraph 0117 where first transistor M1 may be formed of a P-type polysilicon transistor and paragraph 0077 where polysilicon transistor may be set with low temperature polysilicon).
Consider claim 4, Shin as modified by Cheng teaches all the limitations of claim 1 and further teaches wherein the first inverter transistor includes a gate electrode connected to the logic output terminal of the logic portion (see Shin figure 4, element 211, M2),
a first end configured to receive a gate low voltage (see Shin figure 4, element VGL), and
a second end connected to the gate output terminal (see Shin figure 4, element Nc, S1i), and
wherein the second inverter transistor includes a gate electrode connected to the logic output terminal of the logic portion (see Shin figure 4, element 211, M1),
a first end configured to receive a gate high voltage (see Shin figure 4, element VGH), and
a second end connected to the gate output terminal (see Shin figure 4, element Nc, S1i).
Consider claim 5, Shin as modified by Cheng teaches all the limitations of claim 1 and further teaches wherein the first inverter transistor is configured to be turned on by the logic signal having a gate high voltage to output the scan signal having a gate low voltage to the gate output terminal (see Shin paragraph 0124-0127 where second transistor M2 may be turned on and the low level voltage of the second driving power source VGL may be applied to the common node Nc and in order to turn on the N-type oxide semiconductor transistor, the scan signal including the high level pulse is required), and
wherein the second inverter transistor is configured to be turned on by the logic signal having a gate low voltage to output the scan signal having the gate high voltage to the gate output terminal (see Shin paragraph 0123 where when the output signal So including a pulse of a low level is supplied, the first transistor M1 may be turned on, and thus, the high level voltage of the first driving power source VGH may be applied to the common node Nc).
Consider claim 6, Shin as modified by Cheng teaches all the limitations of claim 1 and further teaches wherein the logic portion includes a plurality of logic transistors (see Shin figure 6 where 210 includes P1-P8 transistors), and
wherein the plurality of logic transistors include one or more low temperature polysilicon (LTPS) transistors (see Shin paragraphs 0077).
Consider claim 13, Shin teaches a scan driving circuit (see Shin figure 1, element 110 and paragraphs 0052-0053 where scan driver 110 may sequentially supply the scan signals to the scan lines S11 to S1n. When the scan signals are sequentially supplied to the scan lines S11 to S1n, the pixels PXL may be sequentially selected in the unit of a horizontal line) comprising:
a logic portion configured to receive a plurality of clock signals and output a logic signal through a logic output terminal (see Shin figure 3, element 210 detailed in figure 6 where figure 6, elements CLK1, CLK2, So, 211) to supply a scan signal to a pixel circuit (see Shin figure 1, element PXL, detailed in figure 2); and
an inverter configured to receive the logic signal and output the scan signal with a phase of the logic signal inverted through a gate output terminal (see Shin figure 3, element 220 detailed in figure 4),
wherein the inverter includes a first inverter transistor (see Shin figure 4, element M2) and a second inverter transistor (see Shin figure 4, element M1),
the first inverter transistor being an n-type transistor and the second inverter transistor being a p-type transistor (see Shin paragraphs 0113-0133 specifically for example paragraph 0114 where a first transistor M1 and a second transistor M2 which are complementarily operated and figure 4 where M1 and M2 are illustrated as p-type and n-type transistors respectively), and
the first inverter transistor and the second inverter transistor are both connected to the gate output terminal (see Shin figure 3, element 210, So, 220, figure 4, element M1, M2, So is input to gate electrode of both), and
wherein the first inverter transistor includes an oxide semiconductor (see Shin paragraphs 0113-0133 specifically for example paragraph 0129 where the inverter 220 of the present invention includes the oxide semiconductor transistor M2 having a small leakage current).
Shin is silent regarding driving circuit unit being a logic portion. In a related field of endeavor, Cheng teaches that a driving circuit includes a shift register is widely employed digital logic circuit (see Cheng paragraph 0004) so as to provide scan driving signals to a display. One of ordinary skill would have found it obvious that Shin’s teaching of a driving circuit to sequentially output signals to generate scan signals as corresponding to a logic circuit in view of Cheng’s teaching that a shift register is a digital logic circuit.
Claims 14-17 recite similar claim limitations as claims 2-5, and thus are rejected under similar rational as claims 2-5 detail above.
Consider claim 21, Shin teaches a scan driving circuit (see Shin figure 1, element 110 and paragraphs 0052-0053 where scan driver 110 may sequentially supply the scan signals to the scan lines S11 to S1n. When the scan signals are sequentially supplied to the scan lines S11 to S1n, the pixels PXL may be sequentially selected in the unit of a horizontal line) comprising:
a logic portion configured to receive a plurality of clock signals and output a logic signal through a logic output terminal (see Shin figure 3, element 210 detailed in figure 6 where figure 6, elements CLK1, CLK2, So, 211); and
an inverter configured to receive the logic signal and output the scan signal with a phase of the logic signal inverted through a gate output terminal (see Shin figure 3, element 220 detailed in figure 4),
wherein the inverter includes a first inverter transistor (see Shin figure 4, element M2) and a second inverter transistor (see Shin figure 4, element M1),
the first inverter transistor being an n-type transistor and the second inverter transistor being a p-type transistor (see Shin paragraphs 0113-0133 specifically for example paragraph 0114 where a first transistor M1 and a second transistor M2 which are complementarily operated and figure 4 where M1 and M2 are illustrated as p-type and n-type transistors respectively).
Shin is silent regarding driving circuit unit being a logic portion. In a related field of endeavor, Cheng teaches that a driving circuit includes a shift register is widely employed digital logic circuit (see Cheng paragraph 0004) so as to provide scan driving signals to a display. One of ordinary skill would have found it obvious that Shin’s teaching of a driving circuit to sequentially output signals to generate scan signals as corresponding to a logic circuit in view of Cheng’s teaching that a shift register is a digital logic circuit.
Consider claim 22, Shin as modified by Cheng teaches all the limitations of claim 21 and further teaches wherein the first inverter transistor is an oxide thin film transistor (see Shin paragraphs 0113-0133 specifically for example paragraph 0129 where the inverter 220 of the present invention includes the oxide semiconductor transistor M2 having a small leakage current), and
the second inverter transistor is a low temperature polysilicon (LTPS) thin film transistor (see Shin paragraph 0117 where first transistor M1 may be formed of a P-type polysilicon transistor and paragraph 0077 where polysilicon transistor may be set with low temperature polysilicon).
Claim(s) 2, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al, U.S. Patent Publication No. 20180190204 and Cheng et al, U.S. Patent Publication No. 20100045657 in view of Ka et al, U.S. Patent Publication No. 20180006099.
Consider claim 2, Shin as modified by Cheng teaches all the limitations of claim 1 and further teaches wherein the logic portion is further configured to: supply the logic signal having a gate high voltage to the gate electrode of the first inverter transistor and the logic signal having a gate low voltage to the gate electrode of the first inverter transistor (see Shin figure 4, element So which includes a high signal portion and a low signal portion provided to gate of M2),
Shin is silent regarding wherein a period during which the gate high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor is longer than a period during which the gate low voltage of the logic signal is supplied to the gate electrode of the first inverter transistor.
Shin teaches a pixel circuit having an n-type transistor connected to a scan line and a data line (see Shin figure 2, element T2, S1i and paragraphs 0085-0086) so as to provide a scan signal for providing a data to a pixel.
In a related field of endeavor, Ka teaches a pixel circuit having an n-type transistor connected to a scan line and a data line (see Ka figure 5, element M2, S2i and paragraphs 0089-0093) so as to provide a scan signal for providing a data to a pixel where waveforms for the pixel of figure 5 are illustrated in figure 6 (see Ka figure 6, element S2i). Contrasted with the wave forms of figure 3A-B for the pixel circuit of figure 2 of Ka, it can be seen that S1i has a low signal during an on period of transistor M2 in figure 2 having a p-type transistor whereas figure 6 has a high signal during an on period of transistor M2 of figure 5.
One of ordinary skill would have found it obvious that a period during which the gate high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor is longer than a period during which the gate low voltage of the logic signal is supplied to the gate electrode of the first inverter transistor so as to output an appropriate signal to turn on Shin’s n-type transistor T2 to supply a data at an appropriate timing as disclosed by Ka.
Claim 14 recites similar claim limitations as claim 2, and thus is rejected under similar rational as claim 2 detail above.
Allowable Subject Matter
Claims 10-12, 18-20, 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The claimed invention recites
Claim 10 “ The display device according to claim 1, wherein the first inverter transistor includes a bottom electrode, the gate electrode of the first inverter transistor and the bottom electrode being positioned on opposite sides of the oxide semiconductor, and wherein the display device further comprises: a first switch having a first end connected to the gate electrode of the first inverter transistor and a second end connected to the bottom electrode; and a second switch having a first end connected in common to both of the bottom electrode and the first switch, and a second end configured to receive a constant voltage. ”
Claims 18, 23 recite similar allowable subject matter. Claims 11-12, 19-20, 24-25 are allowable by virtue of being dependent upon a claim reciting allowable subject matter.
The following prior arts are representative of the state of the prior art:
Gui et al, U.S. Patent Publication No. 20240420644 (figure 10A-10B)
Kitazawa, U.S. Patent Publication No. 20080036706 (figure 6
Shin et al, U.S. Patent Publication No. 20180190204 (figures 4-6)
Zhao, U.S. Patent Publication No. 20170162153 (figure 2)
Hong et al, U.S. Patent Publication No. 11443674 (figure 4, 7)
Kim, U.S. Patent Publication No. 20240090264 (figure 4)
The prior arts cited fails to fairly teach or suggest the combined features of the invention including wherein the display device further comprises: a first switch having a first end connected to the gate electrode of the first inverter transistor and a second end connected to the bottom electrode; and a second switch having a first end connected in common to both of the bottom electrode and the first switch, and a second end configured to receive a constant voltage.
These features find support at least at figure 9 of Applicant’s original specification.
As such, modification of the prior art of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art would have made the necessary modifications to the prior art of record to encompass the limitations set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 10-12, 18-20, 23-25 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims..
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al, U.S. Patent Publication No. 20020027545 (see paragraphs 004, 0016), Kim et al, U.S. Patent Publication No. 20150263722 (gate driver and display device), Yang et al, U.S. Patent Publication No. 20210118375 (display device), Liu et al, U.S. Patent Publication No. 20240282266 (drive control circuit)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dorothy H Harris whose telephone number is (571)270-7539. The examiner can normally be reached Monday - Friday 8am - 4pm.
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/Dorothy Harris/Primary Examiner, Art Unit 2625
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