DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In particular, claims 1, 13, and 20 recite “the application program is switched to a background.” It is unclear what that limitation entails since the claims do not clearly state how the application program is receding to a background posture and in relation to what the application program is considered switched to a “background.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 12, 13, 20 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by CN 115525404 (hereinafter CN404, Relying on the most Relevant Portion of the Attached PE2E English Document).
Regarding claim 1, CN404 discloses a memory processing method, applied to a memory processing apparatus [Description: in the electronic device, each process of the application comprises a memory distributor, the process obtains the memory needed by the operation from the OS], wherein the method comprises: receiving a first command from an application program [Description: in the electronic device, each process of the application comprises a memory distributor, the process obtains the memory needed by the operation from the OS], wherein the first command indicates to release a first physical memory of the application program [Description: sending the memory release command], the first command is sent when the application program is switched to a background [Description: application is switched to the background operation], and the application program and a hardware device share the first physical memory [Description: the embodiment of the application comprising a memory and one or more processors]; and releasing the first physical memory [Description: sending the memory release command].
Regarding claim 8, CN404 discloses the method according to claim 1, wherein the memory processing apparatus comprises a memory reclamation driver module and a physical memory management module [Description: in the electronic device, each process of the application comprises a memory distributor, the process obtains the memory needed by the operation from the OS]; wherein receiving the first command from the application program comprises: receiving, by the memory reclamation driver module, the first command from the application program [Description: in the electronic device, each process of the application comprises a memory distributor, the process obtains the memory needed by the operation from the OS]; and wherein the releasing the first physical memory comprises: sending, by the memory reclamation driver module, a second command to the physical memory management module, wherein the second command indicates to release the first physical memory; and releasing, by the physical memory management module, the first physical memory [Description: sending memory release command to release memory occupied by the process].
Regarding claim 12, CN404 discloses the method according to claim 1, wherein the memory processing apparatus is located in the kernel space of an electronic device [Background].
Regarding claim 13, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claim 20, the rationale in the rejection of claim 1 is herein incorporated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 115525404 and CN112015669 (hereinafter CN669 Relying on the most Relevant Portions of the Attached PE2E English Translation).
Regarding claim 2, CN404 discloses the method according to claim 1, wherein before releasing the first physical memory [Description: sending the memory release command],
CN404 does not explicitly disclose physical address is mapped to virtual address.
CN669, however, discloses the method further comprises: modifying the first physical address to which the first virtual address is mapped in a first page table that comprises a mapping relationship between a first physical address and a first virtual address [FIG. 1-6; Contents of Invention Section, paragraph 10-15], wherein the first physical address is a physical address of the first physical memory, and the first virtual address is a virtual address in a virtual address space of the application program [FIG. 1-6; Contents of Invention Section, paragraph 10-15]; and modifying the first physical address to which the second virtual address is mapped in a second page table that comprises a mapping relationship between the first physical address and a second virtual address, wherein the second virtual address is a virtual address in a virtual address space of the hardware device [FIG. 1-6; Contents of Invention Section, paragraph 10-15].
It would have been obvious to one of ordinary skill in the art to have physical address being mapped to virtual address in order to reduce the performance interference between the virtual machine and other processes between the virtual machine and the host OS (Description).
Regarding claim 3, CN669 discloses the method according to claim 2, wherein the modifying the first physical address to which the first virtual address is mapped in the first page table comprises: modifying the first physical address to a preset physical address [FIG. 1-6; Contents of Invention Section, paragraph 10-15]; and wherein the modifying the first physical address to which the second virtual address is mapped in the second page table comprises: modifying the first physical address to the preset physical address [FIG. 1-6; Contents of Invention Section, paragraph 10-15].
Regarding claim 4, CN404 discloses the method according to claim 2, wherein the method further comprises: receiving a fourth command from the application program, wherein the fourth command indicates to reallocate a shared physical memory to the application program and the hardware device, and the fourth command is sent when the application program starts to be switched from the background to a foreground [Description Section];
CN669 further discloses allocating a shared second physical memory to the application program and the hardware device, wherein a physical address of the second physical memory is a second physical address [FIG. 1-6; Description]; modifying the physical address to which the first virtual address is mapped in the first page table to the second physical address; and modifying the physical address to which the second virtual address is mapped in the second page table to the second physical address [FIG. 1-6; Description].
Regarding claim 5, CN669 discloses the method according to claim 2, wherein before releasing the first physical memory, the method further comprises: modifying the first physical address to which the third virtual address is mapped in a third page table that comprises a mapping relationship between the first physical address and a third virtual address, wherein the third virtual address is a virtual address of a service driver in a kernel space [FIG. 1-6; Description]; and wherein after allocating the shared second physical memory to the application program and the hardware device, the method further comprises: modifying the physical address to which the third virtual address is mapped in the third page table to the second physical address [FIG. 1-6; Description].
Regarding claim 6, CN669 discloses the method according to claim 2, wherein the first command comprises an identifier of the first physical memory [FIG. 1].
Regarding claim 7, CN404 discloses the method according to claim 6, wherein the identifier of the first physical memory is an identifier of a buffer configured to record information about the first physical memory [Description].
Regarding claim 14, the rationale in the rejection of claim 2 is herein incorporated.
Regarding claim 15, the rationale in the rejection of claim 4 is herein incorporated.
Regarding claim 16, the rationale in the rejection of claim 5 is herein incorporated.
Regarding claim 17, the rationale in the rejection of claim 7 is herein incorporated.
Regarding claim 18, the rationale in the rejection of claim 7 is herein incorporated.
Allowable Subject Matter
Claims 9-11 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Note that claim 10 is not allowable on its own merit but by virtue of being dependent from claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Warkentin et al. (US 2019/0012179) discloses active page tables having been switched from first page tables to the second page tables and fetching instruction from second location in the physical memory using second virtual address mapped to a machine address.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
