DETAILED ACTION
This is a first office action in response to application 19/379,338 filed 11/04/2025, in which claims 1-20 are presented for examination. Currently claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 10-14, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al. U.S. Patent Application Publication No. 2026/0011306 A1 hereinafter Ono and further in view of Zhu et al. U.S. Patent Application Publication No. 2022/0344425 A1 hereinafter Zhu.
Consider Claim 1:
Ono discloses a pixel circuit comprising: (Ono, See Abstract.)
a light-emitting element; (Ono, [0050-0065], See Fig. 5A item 26.)
a compensation circuit configured to supply current to the light-emitting element; and (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
… a switch transistor connected …between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, (Ono, [0059], “Anode reset transistor Tar may have a first source-drain terminal coupled to the anode terminal of diode 26 (sometimes referred to as the anode electrode), a second source-drain terminal configured to receive an anode reset voltage via an anode reset voltage line (e.g., a column line carrying anode reset voltage Var), and a gate terminal configured to receive a third scan control signal SCAN3. Diode 26 has a cathode terminal (sometimes referred to as the cathode electrode) coupled to the ELVSS ground power supply line 102 (sometimes referred to as a common power supply line).”)
wherein, when …the switch transistor are turned on, the voltage of the anode electrode of the light-emitting element is reset to the anode reset voltage. (Ono, [0050-0065], [0060], “The anode reset voltage Var can be driven by an associated anode reset voltage driver 112. The anode reset voltage line on which Var is provided can have an associated path resistance R.sub.VAR. The ELVSS ground voltage can be driven by an associated ground voltage driver 114. The ground voltage line on which ELVSS is provided can have an associated ground path resistance R.sub.ELVSS. Voltage drivers 112 and 114 can optionally be implemented as part of a power management circuit 110 separate from the array of pixels 22. In the example of FIG. 5A, the ELVSS ground power supply line 102 can be coupled to cathode terminal 104 of diode 26 through a conductive via structure (e.g., a laser drilling contact having an associated contact resistance R.sub.LD). The cathode terminal 104 of one or more display pixels 22 can be implemented as a cathode layer that overlaps one or more pixels 22 and having an associated cathode resistance R.sub.CAT.”)
Ono while teaching to provides a reset function at the anode to reduce ripple however does not additionally provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, wherein, when the diode and the switch transistor are turned on, the voltage of the anode electrode of the light-emitting element is reset to the anode reset voltage.
Zhu however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, wherein, when the diode and the switch transistor are turned on, the voltage of the anode electrode of the light-emitting element is reset to the anode reset voltage. (Zhu, [0080], “The shunt and noise reduction sub-circuit 114 includes a control terminal, a first terminal and a second terminal. Specifically, the control terminal of the shunt and noise reduction sub-circuit 114 receives a bias signal Vb, the first terminal of the shunt and noise reduction sub-circuit 114 is electrically connected to the first node S, and the second terminal of the shunt and noise reduction sub-circuit 114 receives the ground voltage GND. For example, the bias signal Vb is a constant voltage signal, and is also called as a bias voltage Vb, for example, it is 0.8 V to 1 V. The shunt and noise reduction sub-circuit 114 is configured to provide a constant current under the action of the bias signal Vb to realize a shunt function, so that a current passing through a branch where the light-emitting element is located is relatively small. Accordingly, a voltage applied to the light-emitting element 120 has a linear relationship with the data signal, which is conducive to fine control of the gray scale, thereby improving the display quality. In addition, the shunt and noise reduction sub-circuit 114 may also reduce a voltage fluctuation at the first node S caused by the voltage noise of the bias signal Vb, which will be further described in conjunction with a specific circuit below.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element as this was a known technique in view of Zhu and would have been utilized for the art recognized purpose of reduce a voltage fluctuation at the anode caused by the voltage noise to realize a shunt function, so that a current passing through a branch where the light-emitting element is located is relatively small. (Zhu, [0080])
Consider Claim 2:
Ono in view of Zhu disclose the pixel circuit according to claim 1, wherein: the diode includes an anode electrode connected to the anode electrode of the light-emitting element and a cathode electrode connected to the switch transistor, and the switch transistor is configured to electrically connect the constant voltage node to the cathode electrode of the diode in response to a scan signal. (Zhu, [0080], “The shunt and noise reduction sub-circuit 114 includes a control terminal, a first terminal and a second terminal. Specifically, the control terminal of the shunt and noise reduction sub-circuit 114 receives a bias signal Vb, the first terminal of the shunt and noise reduction sub-circuit 114 is electrically connected to the first node S, and the second terminal of the shunt and noise reduction sub-circuit 114 receives the ground voltage GND. For example, the bias signal Vb is a constant voltage signal, and is also called as a bias voltage Vb, for example, it is 0.8 V to 1 V. The shunt and noise reduction sub-circuit 114 is configured to provide a constant current under the action of the bias signal Vb to realize a shunt function, so that a current passing through a branch where the light-emitting element is located is relatively small. Accordingly, a voltage applied to the light-emitting element 120 has a linear relationship with the data signal, which is conducive to fine control of the gray scale, thereby improving the display quality. In addition, the shunt and noise reduction sub-circuit 114 may also reduce a voltage fluctuation at the first node S caused by the voltage noise of the bias signal Vb, which will be further described in conjunction with a specific circuit below.”)
Consider Claim 3:
Ono in view of Zhu disclose the pixel circuit according to claim 2, wherein a cathode electrode of the light-emitting element is coupled to a touch sensor through a capacitor. (Ono, [0061], “In practice, the anode terminal of diode 26 can have an anode voltage that is dependent on the current brightness level of diode 26 (e.g., the anode voltage level is brightness or content dependent). For example, a higher gray level can lead to a higher anode voltage, whereas a lower gray level can lead to a lower anode voltage. During an anode reset operation, current can flow through anode reset transistor Tar and diode 26, as indicated by anode reset current path 120 (see dotted current path in FIG. 5A). The anode reset current path 120 can also sometimes be referred to herein as the anode “discharge” path. Depending on the voltage level present at the anode terminal of diode 26 at the beginning of the anode reset operation, the amount of current 120 flowing into the cathode terminal 104 can vary. The cathode can be electrically coupled to one or more touch sensor electrodes of the touch sensor circuitry. This can cause a varying amount of cathode rippling when an anode reset operation is performed during the vertical blanking period. Such image/content dependent cathode rippling can inadvertently be coupled to the touch sensor circuitry, resulting in undesired interference between the display and touch components.”)
Consider Claim 4:
Ono in view of Zhu disclose the pixel circuit according to claim 1, wherein the compensation circuit includes: a driving transistor including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switch transistor connected between a second constant voltage node configured to receive a reference voltage and the second node and configured to be turned on in response to a second scan signal; a third switch transistor connected between a data line configured to receive a data voltage and the second node and configured to be turned on in response to a first scan signal; a fourth switch transistor connected between a third constant voltage node configured to receive a pixel driving voltage and the first node and configured to be turned on in response to a first emission signal; and a fifth switch transistor connected between the third node and a fourth node and configured to be turned on in response to a second emission signal. (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
Consider Claim 5:
Ono in view of Zhu disclose the pixel circuit according to claim 4, wherein: the light-emitting element further includes a cathode electrode connected to a fourth constant voltage node configured to receive a pixel ground voltage, and the anode electrode of the light-emitting element is connected to the fourth node, the switch transistor connected to the diode includes a second switch transistor connected between the first constant voltage node and a fifth node and (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
configured to be turned on in response to a third scan signal, and the diode includes a transistor including a gate electrode and a first electrode connected to the fourth node, and a second electrode connected to the fifth node. (Ono, [0050-0065], [0059], “Anode reset transistor Tar may have a first source-drain terminal coupled to the anode terminal of diode 26 (sometimes referred to as the anode electrode), a second source-drain terminal configured to receive an anode reset voltage via an anode reset voltage line (e.g., a column line carrying anode reset voltage Var), and a gate terminal configured to receive a third scan control signal SCAN3. Diode 26 has a cathode terminal (sometimes referred to as the cathode electrode) coupled to the ELVSS ground power supply line 102 (sometimes referred to as a common power supply line).”)
Consider Claim 6:
Ono in view of Zhu disclose the pixel circuit according to claim 5, wherein: the reference voltage is lower than the pixel driving voltage and higher than the anode reset voltage, and the anode reset voltage is higher than the pixel ground voltage. (Ono, [0060], “The anode reset voltage Var can be driven by an associated anode reset voltage driver 112. The anode reset voltage line on which Var is provided can have an associated path resistance R.sub.VAR. The ELVSS ground voltage can be driven by an associated ground voltage driver 114. The ground voltage line on which ELVSS is provided can have an associated ground path resistance R.sub.ELVSS. Voltage drivers 112 and 114 can optionally be implemented as part of a power management circuit 110 separate from the array of pixels 22. In the example of FIG. 5A, the ELVSS ground power supply line 102 can be coupled to cathode terminal 104 of diode 26 through a conductive via structure (e.g., a laser drilling contact having an associated contact resistance R.sub.LD). The cathode terminal 104 of one or more display pixels 22 can be implemented as a cathode layer that overlaps one or more pixels 22 and having an associated cathode resistance R.sub.CAT.”)
Consider Claim 7:
Ono in view of Zhu disclose the pixel circuit according to claim 5, wherein the compensation circuit further includes: a first capacitor connected between the second node and the third node; and a second capacitor connected between the third constant voltage node and the third node. (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
Consider Claim 10:
Ono discloses display panel comprising: (Ono, See Abstract.)
a display area in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are arranged, each of the sub-pixels including a pixel circuit connected to a light-emitting element; (Ono, [0032], “Device 10 may include input-output devices such as devices 12. Input-output devices 12 may be used in gathering user input, in gathering information on the environment surrounding the user, and/or in providing a user with output. Devices 12 may include one or more displays such as display 14. Display 14 may be an organic light-emitting diode display, a liquid crystal display, an electrophoretic display, an electrowetting display, a plasma display, a microelectromechanical systems display, a display having a pixel array formed from crystalline semiconductor light-emitting diode dies (sometimes referred to as microLEDs), and/or other display. Configurations in which display 14 is an organic light-emitting diode display are sometimes described herein as an example.”)
a touch sensor electrically coupled to the light-emitting element; and (Ono, [0033], “Sensors 16 in input-output devices 12 may include force sensors (e.g., strain gauges, capacitive force sensors, resistive force sensors, etc.), audio sensors such as microphones, touch and/or proximity sensors such as capacitive sensors (e.g., a two-dimensional capacitive touch sensor integrated into display 14, a two-dimensional capacitive touch sensor overlapping display 14, and/or a touch sensor that forms a button, trackpad, or other input device not associated with a display), and other sensors. Display 14 with overlapping touch sensor circuitry that provide touch sensing functionality may sometimes be referred to as a touch screen display.”)
a gate driving circuit connected to the gate lines, (Ono, [0040], “Gate driver circuitry 34 (sometimes referred to as horizontal line control circuitry or row driver circuitry) may be implemented as part of an integrated circuit and/or may be implemented using thin-film transistor circuitry. Horizontal/row control lines G in display 14 may carry gate line signals (scan line control signals), emission enable control signals, and/or other horizontal control signals for controlling the pixels of each row. There may be any suitable number of horizontal control signals per row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.).”)
wherein the pixel circuit includes: a light-emitting element; (Ono, [0037], “Each display pixel 22 may have a light-emitting diode 26 that emits light 24 under the control of a pixel control circuit formed from thin-film transistor circuitry such as thin-film transistors 28 and thin-film capacitors). Thin-film transistors 28 may be polysilicon thin-film transistors, semiconducting oxide thin-film transistors such as indium zinc gallium oxide transistors, or thin-film transistors formed from other semiconductors. Pixels 22 may contain light-emitting diodes of different colors (e.g., red, green, and blue) to provide display 14 with the ability to display color images.”)
a compensation circuit configured to supply current to the light-emitting element; and (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
… a switch transistor connected… between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, and (Ono, [0059], “Anode reset transistor Tar may have a first source-drain terminal coupled to the anode terminal of diode 26 (sometimes referred to as the anode electrode), a second source-drain terminal configured to receive an anode reset voltage via an anode reset voltage line (e.g., a column line carrying anode reset voltage Var), and a gate terminal configured to receive a third scan control signal SCAN3. Diode 26 has a cathode terminal (sometimes referred to as the cathode electrode) coupled to the ELVSS ground power supply line 102 (sometimes referred to as a common power supply line).”)
wherein, when …the switch transistor are turned on, the voltage of the anode electrode of the light-emitting element is reset to the anode reset voltage. (Ono, [0050-0065], [0060], “The anode reset voltage Var can be driven by an associated anode reset voltage driver 112. The anode reset voltage line on which Var is provided can have an associated path resistance R.sub.VAR. The ELVSS ground voltage can be driven by an associated ground voltage driver 114. The ground voltage line on which ELVSS is provided can have an associated ground path resistance R.sub.ELVSS. Voltage drivers 112 and 114 can optionally be implemented as part of a power management circuit 110 separate from the array of pixels 22. In the example of FIG. 5A, the ELVSS ground power supply line 102 can be coupled to cathode terminal 104 of diode 26 through a conductive via structure (e.g., a laser drilling contact having an associated contact resistance R.sub.LD). The cathode terminal 104 of one or more display pixels 22 can be implemented as a cathode layer that overlaps one or more pixels 22 and having an associated cathode resistance R.sub.CAT.”)
Ono while teaching to provides a reset function at the anode to reduce ripple however does not additionally provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, and wherein, when the diode and the switch transistor are turned on, the voltage of the anode electrode of the light-emitting element is reset to the anode reset voltage.
Zhu however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, and wherein, when the diode and the switch transistor are turned on, the voltage of the anode electrode of the light-emitting element is reset to the anode reset voltage. (Zhu, [0080], “The shunt and noise reduction sub-circuit 114 includes a control terminal, a first terminal and a second terminal. Specifically, the control terminal of the shunt and noise reduction sub-circuit 114 receives a bias signal Vb, the first terminal of the shunt and noise reduction sub-circuit 114 is electrically connected to the first node S, and the second terminal of the shunt and noise reduction sub-circuit 114 receives the ground voltage GND. For example, the bias signal Vb is a constant voltage signal, and is also called as a bias voltage Vb, for example, it is 0.8 V to 1 V. The shunt and noise reduction sub-circuit 114 is configured to provide a constant current under the action of the bias signal Vb to realize a shunt function, so that a current passing through a branch where the light-emitting element is located is relatively small. Accordingly, a voltage applied to the light-emitting element 120 has a linear relationship with the data signal, which is conducive to fine control of the gray scale, thereby improving the display quality. In addition, the shunt and noise reduction sub-circuit 114 may also reduce a voltage fluctuation at the first node S caused by the voltage noise of the bias signal Vb, which will be further described in conjunction with a specific circuit below.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element as this was a known technique in view of Zhu and would have been utilized for the art recognized purpose of reduce a voltage fluctuation at the anode caused by the voltage noise to realize a shunt function, so that a current passing through a branch where the light-emitting element is located is relatively small. (Zhu, [0080])
Consider Claim 11:
Ono in view of Zhu disclose the display panel according to claim 10, wherein: the diode includes an anode electrode connected to the anode electrode of the light-emitting element and a cathode electrode connected to the switch transistor, and the switch transistor is configured to electrically connect the constant voltage node to the cathode electrode of the diode in response to a scan signal. (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
Consider Claim 12:
Ono in view of Zhu disclose the display panel according to claim 10, wherein a cathode electrode of the light-emitting element is coupled to a touch sensor through a capacitor. (Ono, [0061], “In practice, the anode terminal of diode 26 can have an anode voltage that is dependent on the current brightness level of diode 26 (e.g., the anode voltage level is brightness or content dependent). For example, a higher gray level can lead to a higher anode voltage, whereas a lower gray level can lead to a lower anode voltage. During an anode reset operation, current can flow through anode reset transistor Tar and diode 26, as indicated by anode reset current path 120 (see dotted current path in FIG. 5A). The anode reset current path 120 can also sometimes be referred to herein as the anode “discharge” path. Depending on the voltage level present at the anode terminal of diode 26 at the beginning of the anode reset operation, the amount of current 120 flowing into the cathode terminal 104 can vary. The cathode can be electrically coupled to one or more touch sensor electrodes of the touch sensor circuitry. This can cause a varying amount of cathode rippling when an anode reset operation is performed during the vertical blanking period. Such image/content dependent cathode rippling can inadvertently be coupled to the touch sensor circuitry, resulting in undesired interference between the display and touch components.”)
Consider Claim 13:
Ono in view of Zhu disclose the display panel according to claim 10, wherein: the compensation circuit includes: a driving transistor including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switch transistor connected between a second constant voltage node configured to receive a reference voltage and the second node and configured to be turned on in response to a second scan signal from the gate driving circuit; a third switch transistor connected between a data line configured to receive a data voltage and the second node and configured to be turned on in response to a first scan signal from the gate driving circuit; a fourth switch transistor connected between a third constant voltage node configured to receive a pixel driving voltage and the first node and configured to be turned on in response to a first emission signal from the gate driving circuit; and a fifth switch transistor connected between the third node and a fourth node and configured to be turned on in response to a second emission signal from the gate driving circuit, and wherein the light-emitting element further includes a cathode electrode connected to a fourth constant voltage node configured to receive a pixel ground voltage, and the anode electrode of the light-emitting element is connected to the fourth node, the switch transistor connected to the diode includes a second switch transistor connected between the first constant voltage node and a fifth node and configured to be turned on in response to a third scan signal from the gate driving circuit, and the diode includes a transistor including a gate electrode and a first electrode connected to the fourth node, and a second electrode connected to the fifth node. (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
Consider Claim 14:
Ono in view of Zhu disclose the display panel according to claim 13, wherein the compensation circuit further includes: a first capacitor connected between the second node and the third node; and a second capacitor connected between the third constant voltage node and the third node. (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
Consider Claim 16:
Ono discloses a display device comprising: (Ono, See Abstract.)
a display panel including a display area in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are arranged, each of the sub-pixels including a pixel circuit connected to a light-emitting element; (Ono, [0032], “Device 10 may include input-output devices such as devices 12. Input-output devices 12 may be used in gathering user input, in gathering information on the environment surrounding the user, and/or in providing a user with output. Devices 12 may include one or more displays such as display 14. Display 14 may be an organic light-emitting diode display, a liquid crystal display, an electrophoretic display, an electrowetting display, a plasma display, a microelectromechanical systems display, a display having a pixel array formed from crystalline semiconductor light-emitting diode dies (sometimes referred to as microLEDs), and/or other display. Configurations in which display 14 is an organic light-emitting diode display are sometimes described herein as an example.”)
a touch sensor electrically coupled to the light-emitting element; a gate driving circuit connected to the gate lines; and (Ono, [0033], “Sensors 16 in input-output devices 12 may include force sensors (e.g., strain gauges, capacitive force sensors, resistive force sensors, etc.), audio sensors such as microphones, touch and/or proximity sensors such as capacitive sensors (e.g., a two-dimensional capacitive touch sensor integrated into display 14, a two-dimensional capacitive touch sensor overlapping display 14, and/or a touch sensor that forms a button, trackpad, or other input device not associated with a display), and other sensors. Display 14 with overlapping touch sensor circuitry that provide touch sensing functionality may sometimes be referred to as a touch screen display.”)
a data driving circuit connected to the data lines, (Ono, [0038], “Display driver circuitry 30 may be used to control the operation of pixels 22. The display driver circuitry 30 may be formed from integrated circuits, thin-film transistor circuits, or other suitable electronic circuitry. Display driver circuitry 30 of FIG. 2 may contain communications circuitry for communicating with system control circuitry such as control circuitry 16 of FIG. 1 over path 32. Path 32 may be formed from traces on a flexible printed circuit or other cable. During operation, the control circuitry (e.g., control circuitry 16 of FIG. 1) may supply circuitry 30 with information on images to be displayed on display 14.”)
wherein the pixel circuit includes: a light-emitting element; (Ono, [0050-0065], See Fig. 5A item 26.)
a compensation circuit configured to supply current to the light-emitting element; and (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
…a switch transistor connected … between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, and (Ono, [0059], “Anode reset transistor Tar may have a first source-drain terminal coupled to the anode terminal of diode 26 (sometimes referred to as the anode electrode), a second source-drain terminal configured to receive an anode reset voltage via an anode reset voltage line (e.g., a column line carrying anode reset voltage Var), and a gate terminal configured to receive a third scan control signal SCAN3. Diode 26 has a cathode terminal (sometimes referred to as the cathode electrode) coupled to the ELVSS ground power supply line 102 (sometimes referred to as a common power supply line).”)
wherein, when… the switch transistor are turned on, the voltage of the anode electrode is reset to the anode reset voltage. Ono, [0050-0065], [0060], “The anode reset voltage Var can be driven by an associated anode reset voltage driver 112. The anode reset voltage line on which Var is provided can have an associated path resistance R.sub.VAR. The ELVSS ground voltage can be driven by an associated ground voltage driver 114. The ground voltage line on which ELVSS is provided can have an associated ground path resistance R.sub.ELVSS. Voltage drivers 112 and 114 can optionally be implemented as part of a power management circuit 110 separate from the array of pixels 22. In the example of FIG. 5A, the ELVSS ground power supply line 102 can be coupled to cathode terminal 104 of diode 26 through a conductive via structure (e.g., a laser drilling contact having an associated contact resistance R.sub.LD). The cathode terminal 104 of one or more display pixels 22 can be implemented as a cathode layer that overlaps one or more pixels 22 and having an associated cathode resistance R.sub.CAT.”)
Ono while teaching to provides a reset function at the anode to reduce ripple however does not additionally provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, and wherein, when the diode and the switch transistor are turned on, the voltage of the anode electrode is reset to the anode reset voltage.
Zhu however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element and a first constant voltage node configured to receive an anode reset voltage, and wherein, when the diode and the switch transistor are turned on, the voltage of the anode electrode is reset to the anode reset voltage. (Zhu, [0080], “The shunt and noise reduction sub-circuit 114 includes a control terminal, a first terminal and a second terminal. Specifically, the control terminal of the shunt and noise reduction sub-circuit 114 receives a bias signal Vb, the first terminal of the shunt and noise reduction sub-circuit 114 is electrically connected to the first node S, and the second terminal of the shunt and noise reduction sub-circuit 114 receives the ground voltage GND. For example, the bias signal Vb is a constant voltage signal, and is also called as a bias voltage Vb, for example, it is 0.8 V to 1 V. The shunt and noise reduction sub-circuit 114 is configured to provide a constant current under the action of the bias signal Vb to realize a shunt function, so that a current passing through a branch where the light-emitting element is located is relatively small. Accordingly, a voltage applied to the light-emitting element 120 has a linear relationship with the data signal, which is conducive to fine control of the gray scale, thereby improving the display quality. In addition, the shunt and noise reduction sub-circuit 114 may also reduce a voltage fluctuation at the first node S caused by the voltage noise of the bias signal Vb, which will be further described in conjunction with a specific circuit below.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a diode and a switch transistor connected in series between an anode electrode of the light-emitting element as this was a known technique in view of Zhu and would have been utilized for the art recognized purpose of reduce a voltage fluctuation at the anode caused by the voltage noise to realize a shunt function, so that a current passing through a branch where the light-emitting element is located is relatively small. (Zhu, [0080])
Consider Claim 17:
Ono in view of Zhu disclose the display device according to claim 16, wherein: the compensation circuit includes: a driving transistor including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switch transistor connected between a second constant voltage node configured to receive a reference voltage and the second node and configured to be turned on in response to a second scan signal from the gate driving circuit; a third switch transistor connected between a data line configured to receive a data voltage from the data driving circuit and the second node and configured to be turned on in response to a first scan signal from the gate driving circuit; a fourth switch transistor connected between a third constant voltage node configured to receive a pixel driving voltage and the first node and configured to be turned on in response to a first emission signal from the gate driving circuit; and a fifth switch transistor connected between the third node and a fourth node and configured to be turned on in response to a second emission signal from the gate driving circuit, the light-emitting element further includes a cathode electrode connected to a fourth constant voltage node configured to receive a pixel ground voltage, and the anode electrode of the light-emitting element is connected to the fourth node, the switch transistor connected to the diode includes: a second switch transistor connected between the first constant voltage node and a fifth node and configured to be turned on in response to a third scan signal from the gate driving circuit, and the diode includes: a transistor including a gate electrode and a first electrode connected to the fourth node, and a second electrode connected to the fifth node. (Ono, [0050-0065], [0050], “FIG. 5A is a circuit diagram showing one embodiment of an illustrative display pixel 22. As shown in FIG. 5A, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as storage capacitor Cst, an additional capacitor such as capacitor Ca, and thin-film transistors such a drive transistor Tdrive, a gate-voltage-setting transistor Tref, a data loading transistor Tdata, an anode reset transistor Tar, and emission transistors Tem1 and Tem2. Emission transistors Tem1 and Tem2 are sometimes referred to as emission control transistors.”)
Allowable Subject Matter
Claims 8-9, 15, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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