DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE DRIVING CIRCUIT HAVING CMOS TRANSISTORS AND DISPLAY DEVICE INCLUDING A GATE DRIVER.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. Patent Pub. No. 2017/0148392).
Regarding claim 1, Kim discloses a display device (fig. 1, [0027]) comprising:
a display panel (PNL) configured to display an image, (fig. 1, [0029]); and
a gate driver (GIP) including a shift register (SL1) configured to generate signals (G1) for controlling transistors included in the display panel (PNL), (fig. 2, [0036-0038]),
wherein the shift register (SL1) comprises:
a first scan transistor (M11) configured to be turned on based on a voltage of a Q node (Q) to output a first-level signal (high level) through an output terminal (Gout), (figs. 3-4, [0054]);
a second scan transistor (M9) configured to be turned on based on a voltage of a QB node (QB) to output a second-level signal (low level) through the output terminal (Gout), (figs. 3-4, [0054]);
a third scan transistor (M1) configured to be turned on in response to a clock signal (CLKA) applied through a clock signal line (CLKA) to transmit a start signal (Gout_Pre) applied through a start signal line to the Q node (Q), (figs. 3-4, [0047, 0050 and 0059]); and
CMOS transistors (M5 and M6) configured to control the QB node (QB) based on the voltage of the Q node (Q), (figs. 3-4, [0051-0052]).
Regarding claim 2, Kim discloses wherein the CMOS transistors include a fourth scan transistor (M6) having a gate electrode connected to the Q node (Q), a first electrode connected to a first voltage line through which a first voltage (VGH) is transmitted, and a second electrode connected to the QB node (QB), and a fifth scan transistor (M5) having a gate electrode connected to the Q node (Q), a first electrode connected to a second voltage line through which a second voltage (VGL) is transmitted, and a second electrode connected to the QB node (QB), (fig. 3, [0051-0052]).
Regarding claim 3, Kim discloses wherein the fourth scan transistor (M6) is a p-type transistor having a polysilicon semiconductor (PMOS), and the fifth scan transistor (M5) is an n-type transistor having an oxide semiconductor (NMOS), (fig. 3, [0051]).
Regarding claim 4, Kim discloses wherein the first scan transistor (M11), the second scan transistor (M9), and the third scan transistor (M1) are n-type transistors each having on an oxide semiconductor (NMOS), (fig. 3, [0041]).
Regarding claim 8, please refer to claim 1 for details.
Regarding claim 9, please refer to claim 2 for details.
Regarding claim 10, please refer to claims 3-4 for details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bong et al (U.S. Patent Pub. No. 2024/0257763).
Regarding claim 5, Kim discloses everything as specified above in claim 1. However, Kim does not mention a first scan capacitor and a second scan capacitor.
In a similar field of endeavor, Bong teaches further comprising:
a first scan capacitor (CB) having a first electrode connected to a gate electrode of the first scan transistor (T21) and a second electrode connected to the output terminal (SRO[n]); and
a second scan capacitor (CQB) having a first electrode connected to a gate electrode of the second scan transistor (T22) and a second electrode connected to a second voltage line (VGL), (fig. 9, [0201-0203]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the first and second scan transistor, as taught by Bong, for the purpose of preventing threshold voltage shift of thin film transistors constituting the gate driver from influencing an output of the gate driver, [0010].
Regarding claim 6, Bong discloses wherein the gate driver (300) includes a scan driver (320) configured to supply a scan signal (SRO(n)) to the display panel (AA), and an emission control signal driver (310) configured to supply an emission control signal (EM[n]) to the display panel, and the shift register is included in at least one of the scan driver (320) and the emission control signal driver (310) (i.e. the gate driver 300 is configured such that the shift register at one side of the active area AA includes the second scan driver 322 and the emission control signal driver 310), (figs. 7-9, [0177-0178 and 0182]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the scan driver and the emission control signal driver, as taught by Bong, for the purpose of preventing threshold voltage shift of thin film transistors constituting the gate driver from influencing an output of the gate driver, [0010].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of NO (U.S. Patent Pub. No. 2025/0279046).
Regarding claim 7, Kim discloses everything as specified above in claim 1. However, Kim does not mention the gate driver comprises first to fourth scan driver.
In a similar field of endeavor, No teaches wherein the gate driver (13) comprises:
a first scan driver (13GW) configured to supply a first scan signal (GW1) to the display panel (14), (fig. 1, [0054 and 0059-0060]);
a second scan driver (13GB) configured to supply a second scan signal (GB1) to the display panel (14), (fig. 1, [0059]);
a third scan driver (13GI) configured to supply a third scan signal (GI1) to the display panel (14), (fig. 1, [0061]);
a fourth scan driver (13GC) configured to supply a fourth scan signal (GC1) to the display panel (14), (fig. 1, [0061]); and
an emission control signal driver (15) configured to supply an emission control signal (EM1) to the display panel, (fig. 1, [0062]),
wherein the shift register (i.e. the scan driver and light emitting driver may be configured in the form of a shift register) is included in at least one of the first scan driver, the third scan driver, the fourth scan driver, and the emission control signal driver, (figs. 1, 7 and 14, [0060 and 0062]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the four scan drivers and emission control signal driver, as taught by NO, for the purpose of reducing power consumption, [0005].
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG D PHAM whose telephone number is (571)270-5573. The examiner can normally be reached Monday - Friday: 9am-5pm EST.
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/LONG D PHAM/ Primary Examiner, Art Unit 2623
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