DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han (US 2023/0196998).
• Regarding claim 1, Han discloses a display device (figure 1) comprising:
a display panel including subpixels, each of the subpixels having a light-emitting element (figure 1);
a data driver configured to supply a data voltage or a park voltage to the subpixels through data lines (element 140 in figure 12 and ¶s 70-73, 78-81, and 83); and
a timing controller configured to control the data driver and provide a park voltage control value to the data driver (element 120 in figure 11 and ¶s 73-77),
wherein the data driver generates the park voltage based on the park voltage control value (¶s 70-83).
• Regarding claims 2-5 and 8-11, Han discloses everything claimed, as applied to claim 1. Additionally, Han discloses where:
Claim 2: the park voltage control value is transmitted in the form of a packet through a communication interface connected between the timing controller and the data driver (¶ 80).
Claim 3: the park voltage is changed into voltages of various levels in response to the park voltage control value determined according to driving conditions of the display panel (¶s 81-84).
Claim 4: the data driver comprises:
a first digital-to-analog converter configured to generate the park voltage (inherent in element 145 in figure 12 for performing the functions of ¶ 80);
a second digital-to-analog converter configured to generate the data voltage (¶ 79); and
a selector configured to selectively output one of the park voltage and the data voltage (element 120 in figure 11 and ¶ 75).
Claim 5: the selector outputs the park voltage in response to a park voltage enable signal applied from the timing controller (¶ 75).
Claim 8: one of the park voltage and the data voltage is output when the display panel operates in a variable refresh rate (VRR) driving mode (¶ 75).
Claim 9: the VRR driving mode includes:
a refresh frame for applying the data voltage through the data line connected to the subpixels of the display panel (“Refresh Time” in figure 17 and ¶ 92), and
an anode reset frame for applying the park voltage through the data line (“Anode Reset Time” in figure 17 and ¶ 93).
Claim 10: one of the subpixels comprises:
a driving transistor configured to supply a driving current to the light-emitting element (element DT in figure 9), and
a transistor connected between the data line and the driving transistor (element T1 in figure 9).
Claim 11: the transistor is turned on in the refresh frame so that the data voltage is supplied to the driving transistor (¶s 58-60), and
the transistor is turned off during a period in which the park voltage is provided to the data line in the anode reset frame (¶s 58-60).
• Regarding claim 12, Han discloses a data driver (figure 12) comprising:
a first digital-to-analog converter configured to generate a park voltage and gamma reference voltages (inherent in element 145 in figure 12 for performing the functions of ¶ 80);
a second digital-to-analog converter configured to generate a data voltage based on the gamma reference voltages (¶ 79); and
a selector configured to selectively output one of the park voltage and the data voltage (element 120 in figure 11 and ¶ 75),
wherein the first digital-to-analog converter generates the park voltage based on an external park voltage control value (¶ 75).
• Regarding claims 13 and 15, Han discloses everything claimed, as applied to claim 12. Additionally, Han discloses where:
Claim 13: the selector outputs the park voltage in response to an external park voltage enable signal (¶ 75).
Claim 15: a display device (figure 1) comprising:
a display panel including subpixels, each of the subpixels having a light-emitting element (figure 1); and
the data driver of claim 12 and configured to supply one of the park voltage or the data voltage to the subpixels through data lines (element 140 in figure 12 and ¶s 70-73, 78-81, and 83).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Han, in view of Chang (US 2011/0175876).
• Regarding claims 6 and 14, Han discloses everything claimed, as applied to claims 4 and 13, respectively. However, Han fails to disclose the additional details of the first digital-to-analog converter.
In the same field of endeavor, Chang discloses where:
Claim 6: the first digital-to-analog converter comprises:
a resistor string circuit configured to divide a voltage into voltages having a plurality of levels based on a first reference voltage and a second reference voltage, and output the divided voltages (element 240 in figure 3A and ¶s 35-37); and
a controller configured to change a level of the park voltage based on the voltages output from the resistor string circuit and the park voltage control value, and output the level-changed park voltage (element 244 in figure 3A and ¶s 35-37).
Claim 14: the first digital-to-analog converter comprises:
a resistor string circuit configured to divide a voltage into voltages having a plurality of levels based on a first reference voltage and a second reference voltage, and output the divided voltages (element 240 in figure 3A and ¶s 35-37); and
a controller configured to change a level of the park voltage based on the voltages output from the resistor string circuit and the park voltage control value, and output the level-changed park voltage (element 244 in figure 3A and ¶s 35-37).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Han according to the teachings of Chang, for the purpose of generating a digitally controlled voltage (¶ 47).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Han, in view of Saitoh et al (US 2014/0118421; hereinafter Saitoh).
• Regarding claim 7, Han discloses everything claimed, as applied to claim 1. However, Han fails to disclose the additional details of the display device.
In the same field of endeavor, Saitoh discloses where:
Claim 7: the data driver comprises a plurality of data drivers (elements 6-1 through 6-3 in figure 1), and
the plurality of data drivers generates the park voltage based on a park voltage reference voltage value output from a representative data driver (inherent in the combination of Han and Saitoh).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Han according to the teachings of Saitoh, for the purpose of reducing the size and power consumption of a display device (¶s 15-17).
Closing Remarks/Comments
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at (571) 272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622
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