Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are currently under review.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 11, 2025 and April 2, 2026 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 6-7 are objected to because of the following informalities: typographic error. Appropriate correction is required.
Claim 6, lines 5-6: “the channel area of the first transistor is equal to a sum of [[a]]the channel area of the first sub transistor and [[a]]the channel area of the second sub-transistor.”
Claim 7, line 5: “transistor have [[the]]a same channel area.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Watsuda (Patent No.: US 12,039,921 B1) in view of Mou et al. (Pub. No.: US 2022/0044636 A1) hereinafter referred to as Mou.
With respect to Claim 1, Watsuda teaches a display panel (fig. 2, item 200; column 4, lines 15-16), comprising: sub-pixels (fig. 2, items P(1,1) … P(N, M); column 4, lines 20-21) comprising a first sub-pixel (fig. 2, item PR of item P(1,1)) and a second sub-pixel (fig. 2, item PG of item P(1,1), the first sub-pixel comprising a first transistor (fig. 7, item T13), the second sub-pixel comprising a second transistor (fig. 7, item T23); and light-emitting control signal lines (figs. 2 and 7, items EL_A and EL_B; column 4, lines 22-24) comprising a first light-emitting control signal line (figs. 2 and 7, item EL_A) and a second light-emitting control signal line (figs. 2 and 7, item EL_B), wherein a gate of the first transistor is connected to the first light-emitting control signal line (fig. 7; column 11, lines 60-63), and a gate of the second transistor is connected to the second light-emitting control signal line (fig. 7; column 12, lines 16-18).
Watsuda does not teach and a channel area of the first transistor and a channel area of the second transistor are different.
Mou teaches sub-pixels (fig. 1C; ¶50; ¶56) comprising a first sub-pixel (fig. 1C, item 110) and a second sub-pixel (fig. 1C, item 120), the first sub-pixel comprising a first transistor (fig. 1C, item 111), the second sub-pixel comprising a second transistor (fig. 1C, item 121), wherein a channel area of the first transistor and a channel area of the second transistor are different (¶50).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Watsuda, wherein a channel area of the first transistor and a channel area of the second transistor are different, as taught by Mou so as to improve brightness of a display device by optimizing channel width-length ratios of driving transistors of sub-pixels with different colors on the array substrate (¶48).
With respect to Claim 2, claim 1 is incorporated, Watsuda teaches wherein the display panel further comprises a third sub-pixel (fig. 2, item PB of P(1,1)) comprising a third transistor (fig. 7, item T33), a gate of the third transistor being connected to the second light-emitting control signal line (fig. 7).
Watsuda does not mention and the channel area of the first transistor is larger than the channel area of the second transistor, and the channel area of the first transistor is larger than a channel area of the third transistor.
Mou teaches sub-pixels (fig. 1C; ¶50; ¶56) comprising a first sub-pixel (fig. 1C, item 110) and a second sub-pixel (fig. 1C, item 120), the first sub-pixel comprising a first transistor (fig. 1C, item 111), the second sub-pixel comprising a second transistor (fig. 1C, item 121), wherein a channel area of the first transistor and a channel area of the second transistor are different (¶50) and the channel area of the first transistor is larger than the channel area of the second transistor (¶50, “a channel width-length ratio W1/L1 of the first driving transistor 111 is greater than a channel width-length ratio W2/L2 of the second driving transistor 121”), and the channel area of the first transistor is larger than a channel area of the third transistor (¶58, “the channel width-length ratio of the second driving transistor 121 of the red sub-pixel may be the same as the channel width-length ratio of the third driving transistor 131 of the green sub-pixel”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Watsuda, wherein the channel area of the first transistor is larger than the channel area of the second transistor, and the channel area of the first transistor is larger than a channel area of the third transistor, as taught by Mou so as to improve brightness of a display device by optimizing channel width-length ratios of driving transistors of sub-pixels with different colors on the array substrate (¶48).
With respect to Claim 18, claim 1 is incorporated, Watsuda teaches wherein the first sub-pixel comprises a red sub-pixel, one of the second sub-pixel and the third sub-pixel is a green sub-pixel, and the other is a blue sub-pixel (column 4, lines 41-53).
With respect to Claim 20, Watsuda teaches a display apparatus (column 2, lines 54-66), comprising a display panel (fig. 2, item 200; column 4, lines 15-16) comprising: sub-pixels (fig. 2, items P(1,1) … P(N, M); column 4, lines 20-21) comprising a first sub-pixel (fig. 2, item PR of item P(1,1)) and a second sub-pixel (fig. 2, item PG of item P(1,1), the first sub-pixel comprising a first transistor (fig. 7, item T13), the second sub-pixel comprising a second transistor (fig. 7, item T23); and light-emitting control signal lines (figs. 2 and 7, items EL_A and EL_B; column 4, lines 22-24) comprising a first light-emitting control signal line (figs. 2 and 7, item EL_A) and a second light-emitting control signal line (figs. 2 and 7, item EL_B), wherein a gate of the first transistor is connected to the first light-emitting control signal line (fig. 7; column 11, lines 60-63) and a gate of the second transistor is connected to the second light-emitting control signal line (fig. 7; column 12, lines 16-18).
Watsuda does not teach and a channel area of the first transistor and a channel area of the second transistor are different.
Mou teaches sub-pixels (fig. 1C; ¶50; ¶56) comprising a first sub-pixel (fig. 1C, item 110) and a second sub-pixel (fig. 1C, item 120), the first sub-pixel comprising a first transistor (fig. 1C, item 111), the second sub-pixel comprising a second transistor (fig. 1C, item 121), wherein a channel area of the first transistor and a channel area of the second transistor are different (¶50).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Watsuda, wherein a channel area of the first transistor and a channel area of the second transistor are different, as taught by Mou so as to improve brightness of a display device by optimizing channel width-length ratios of driving transistors of sub-pixels with different colors on the array substrate (¶48).
Claims 1 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (Pub. No.: US 2021/0217348 A1) in view of Watsuda and in view of Mou.
With respect to Claim 1, Liu teaches a display panel (fig. 1; ¶38), comprising: sub-pixels (fig. 4, items 01a, 01b, and 01c = sub-pixel) comprising a first sub-pixel (fig. 4, item 01c; ¶49; ¶65) and a second sub-pixel (fig. 4, item 01b; ¶49; ¶65), the first sub-pixel comprising a first transistor (¶39, “each sub-pixel 01 may include a pixel circuit 011” – each pixel circuit comprises a driving transistor which for a first sub-pixel is a first transistor, ¶50 mentions “a driving transistor in the pixel circuit”), the second sub-pixel comprising a second transistor (¶39, “each sub-pixel 01 may include a pixel circuit 011” – each pixel circuit comprises a driving transistor which for a second sub-pixel is a second transistor, ¶50 mentions “a driving transistor in the pixel circuit”); and light-emitting control signal lines comprising a first light-emitting control signal line (¶65, “A light-emitting control signal terminal of the pixel circuit of the red sub-pixels 01c in one row of sub-pixels may be connected to the first light-emitting control sub-circuit 0211”) and a second light-emitting control signal line (¶65, “the green sub-pixel 01b is connected to the second light-emitting control sub-circuit 0212”), wherein the first sub-pixel is connected to the first light-emitting control signal line (¶65), and the second sub-pixel is connected to the second light-emitting control signal line (¶65).
Liu does not explicitly teach wherein a gate of the first transistor is connected to the first light-emitting control signal line and a gate of the second transistor is connected to the second light-emitting control signal line.
Watsuda teaches a display panel (fig. 2, item 200; column 4, lines 15-16), comprising: sub-pixels (fig. 2, items P(1,1) … P(N, M); column 4, lines 20-21) comprising a first sub-pixel (fig. 2, item PR of item P(1,1)) and a second sub-pixel (fig. 2, item PG of item P(1,1), the first sub-pixel comprising a first transistor (fig. 7, item T13), the second sub-pixel comprising a second transistor (fig. 7, item T23); and light-emitting control signal lines (figs. 2 and 7, items EL_A and EL_B; column 4, lines 22-24) comprising a first light-emitting control signal line (figs. 2 and 7, item EL_A) and a second light-emitting control signal line (figs. 2 and 7, item EL_B), wherein a gate of the first transistor is connected to the first light-emitting control signal line (fig. 7; column 11, lines 60-63), and a gate of the second transistor is connected to the second light-emitting control signal line (fig. 7; column 12, lines 16-18).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Liu, wherein a gate of the first transistor is connected to the first light-emitting control signal line and a gate of the second transistor is connected to the second light-emitting control signal line, as taught by Watsuda so as to provide a pixel circuit for connection to the light-emitting control line and driving the sub-pixels.
Liu and Watsuda combined do not teach and a channel area of the first transistor and a channel area of the second transistor are different.
Mou teaches sub-pixels (fig. 1C; ¶50; ¶56) comprising a first sub-pixel (fig. 1C, item 110) and a second sub-pixel (fig. 1C, item 120), the first sub-pixel comprising a first transistor (fig. 1C, item 111), the second sub-pixel comprising a second transistor (fig. 1C, item 121), wherein a channel area of the first transistor and a channel area of the second transistor are different (¶50).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display panel of Liu and Watsuda, wherein a channel area of the first transistor and a channel area of the second transistor are different, as taught by Mou so as to improve brightness of a display device by optimizing channel width-length ratios of driving transistors of sub-pixels with different colors on the array substrate (¶48).
With respect to Claim 18, claim 1 is incorporated, Liu teaches wherein the first sub-pixel comprises a red sub-pixel (¶65), one of the second sub-pixel and the third sub-pixel is a green sub-pixel (¶62), and the other is a blue sub-pixel (¶61).
With respect to Claim 19, claim 18 is incorporated, Liu teaches wherein in one frame, a time duration of an active level on the first light-emitting control signal line is longer than a time duration of an active level on the second light-emitting control signal line (¶59).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Watsuda and Mou as applied to claim 2 above, and further in view of Lai et al. (Pub. No.: US 2021/0407383 A1).
With respect to Claim 14, claim 2 is incorporated, Watsuda and Mou combined do not teach wherein a line width of the first light emitting control signal line is smaller than a line width of the second light-emitting control signal line.
Lai teaches a display panel (fig. 23, item 100; ¶141) comprising a first sub-pixel (fig. 23, top row leftmost sub-pixel) and a second sub-pixel (fig. 23, top row second sub-pixel from the left), the first sub-pixel comprising a first transistor (first sub-pixel comprises fig. 1, item T1 is the first transistor), the second sub-pixel comprising a second transistor (second sub-pixel comprises fig. 1); and light-emitting control signal lines comprising a first light-emitting control signal line (fig. 1, item EM1) and a second light-emitting control signal line (fig. 1, item EM2), wherein a gate of the first transistor is connected to the first light-emitting control signal line (fig. 1), and a gate of the second transistor is connected to the second light-emitting control signal line (fig. 1, item T1 of the second transistor is connected to EM2 via items T3 and T0); wherein a line width of the first light emitting control signal line is smaller than a line width of the second light-emitting control signal line (¶49).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Watsuda and Mou, wherein a line width of the first light emitting control signal line is smaller than a line width of the second light-emitting control signal line, as taught by Lai so as to reduce a transmission impedance, reducing a transmission loss of the first light emitting control signal line EM1 and avoiding that long-term loss accumulation of the first light emitting control signal line affects the bias or the light emission (¶49).
Allowable Subject Matter
Claims 3-13 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 3, none of the prior art teaches wherein the channel area of the first transistor is equal to a sum of the channel area of the second transistor and the channel area of the third transistor including all the base limitations. With respect to claim 6, none of the prior art teaches wherein the first transistor comprises a first sub-transistor and a second sub-transistor that are connected in series, and a gate of the first sub-transistor and a gate of the second sub-transistor are connected to the first light-emitting control signal line; and the channel area of the first transistor is equal to a sum of a channel area of the first sub transistor and a channel area of the second sub-transistor including all the base limitations. With respect to claim 9, none of the prior art teaches wherein at least one of the first light-emitting control signal line or the second light-emitting control signal line is connected with a compensation structure for compensating a load of the light-emitting control signal line to which the compensation structure is connected including all the base limitations. With respect to claim 15, none of the prior art teaches wherein the first sub-pixel comprises a first driving transistor and a first light-emitting element, and the first transistor comprises a first power supply writing transistor and a first light-emitting control transistor; the first power supply writing transistor is connected between a first electrode of the first driving transistor and a first power supply line, and the first light-emitting control transistor is connected between a second electrode of the first driving transistor and the first light-emitting element; a channel width-to-length ratio of the first power supply writing transistor is less than a channel width-to-length ratio of the first light-emitting control transistor including all the base limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xuan et al. (Pub. No.: US 2021/0390904A1).
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/DONNA V Bocar/Primary Examiner, Art Unit 2621
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