DETAILED ACTIONNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-26 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19/323,303 (US 2026/0150532) (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is a broader recitation and an amalgamation of various claims in the copending application, as shown below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application 19/387,087
Copending Application No. 19/323,303
1. A display apparatus comprising: a data line configured to supply a data voltage; an initialization voltage line configured to supply an initialization voltage; a reference voltage line configured to supply a reference voltage; a light emitting element configured to emit light during a driving section; a sensing line configured to receive a sensing signal during a sensing section; a hold line configured to supply a hold signal; a first transistor configured to control a driving current flowing in the light-emitting element; a second transistor connected between the data line and a first node, which is a gate electrode of the first transistor; a third transistor connected between the initialization voltage line and a second node, which is a source electrode of the first transistor; a fourth transistor connected between the hold line and a third node; a fifth transistor connected between the reference voltage line and the first node; and a sixth transistor connected between the second node and the sensing line, wherein gate electrodes of the fifth and sixth transistors are connected to the third node.
1. A display device, comprising: a substrate; a first light shielding layer disposed on the substrate; a second light shielding layer disposed on the first light shielding layer; an active layer disposed on the second light shielding layer and including a semiconductor region of Claim 1 recited below (bolded)Claim 3 recites an initialization voltage lineClaim 9 recites a reference voltage lineClaim 1 recited below (bolded)Claims 2 recites a sensing lineClaim 1 recited below (bolded)a first transistor; a gate layer including a gate electrode of the first transistor disposed on the active layer; a first source metal layer including a first hold line disposed on the gate layer, the first source metal layer extending in a first direction and configured to supply a hold signal; a second source metal layer including a second hold line disposed on the first source metal layer, the second source metal layer extending in a second direction intersecting the first direction and connected to the first hold line; a light emitting element including a pixel electrode disposed on the second source metal layer; a second transistor configured to supply a data voltage to a first node being at a gate electrode of the first transistor, based on a first scan signal; a third transistor configured to supply an initialization voltage to a second node being at a source electrode of the first transistor, based on a second scan signal; a fourth transistor configured to supply the hold signal to a third node based on the first scan signal; a fifth transistor electrically connecting a reference voltage line and the first node based on a voltage of the third node; and a sixth transistor electrically connecting the second node and a sensing line based on a voltage of the third node.
As can be shown above, the instant application claim 1 is a broader recitation and an amalgamation of claims 1, 2, 3 and 9 of the copending application. Independent claim 17 is an amalgamation of claims 1, 2, 3 and 5-9 where claims 5-8 recite the details of the first and second capacitor. The dependent claims read on various dependent claims of the copending application or are well known features of display devices.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: JEONG et al (2022/0051629) teaches the closest prior art, however fails to teach the entirety of the independent claim.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN A BOYD whose telephone number is (571)270-7503. The examiner can normally be reached Mon - Fri 8:00 - 5:00.
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/JONATHAN A BOYD/Primary Examiner, Art Unit 2627
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