DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (pub # 20240212594) in view of Lim et al (pub # 20240331616).
Consider claim 1. Choi et al teaches A display device, (abstract). comprising:
a pixel including a first sub-pixel (Fig. 7 and paragraph 0152, a first subpixel SP1).
and a second sub-pixel configured to emit light of a color different from the first sub-pixel; (paragraph 0159 and Fig. 7, second subpixel SP2. Paragraph 0170, the first subpixel SP1 can emit light of a first color, the second subpixel SP2 can emit light of a second color different from light of the first color).
wherein the first sub-pixel includes:
a first light-emitting diode; (Fig. 7 and paragraph 0172, first light emitting element ED1).
a first driving transistor having one end connected to the first light-emitting diode and configured to provide a driving current to the first light-emitting diode, (Fig. 7 and paragraph 0153, a first light emitting control transistor EMT1 configured to control a connection between the first light emitting element ED1 and the first driving circuit PAM1).
and wherein the second sub-pixel includes:
a second light-emitting diode; (Fig. 7 and paragraph 0160, the second subpixel SP2 may include a second light emitting element ED2).
a second driving transistor having one end connected to the second light-emitting diode and configured to provide a driving current to the second light-emitting diode; (Fig. 7 and paragraph 0163, The second light emitting control transistor EMT2 can be turned on or off by a second light emitting control signal EM2 applied to its gate node, and control a connection between the second light emitting element ED2 and the second driving circuit PAM2).
Choi et al does not specifically disclose a first charging control line for providing a first charging control signal, which is activated during a first time interval, to the first sub-pixel; and a second charging control line for providing a second charging control signal, which is activated during a second time interval different from the first time interval, to the second sub-pixel ; and a first charging transistor configured to provide a reference voltage to a gate of the first driving transistor in response to the first charging control signal and a second charging transistor configured to provide the reference voltage to a gate of the second driving transistor in response to the second charging control signal.
In an analogous art Lim et al teaches a first charging control line for providing a first charging control signal, which is activated during a first time interval, to the first sub-pixel; and a second charging control line for providing a second charging control signal, which is activated during a second time interval different from the first time interval, to the second sub-pixel; (Fig. 11 and paragraph 0091, transistor T2 may transfer a reference voltage VREF to the gate node NG in response to a reference signal GR, thus a charging control line. Fig. 12 and paragraph 0103, In the compensation period CMPP, the first emission signal EM1 may have the high level, the second emission signal EM2 may have the low level, the reference signal GR may have the high level, the initialization signal GI may have the low level, and the writing signal GW may have the low level. In some embodiments, as illustrated in FIG. 12, the reference signal GR may be changed to the low level before the compensation period CMPP ends.).
and a first charging transistor configured to provide a reference voltage to a gate of the first driving transistor in response to the first charging control signal and a second charging transistor configured to provide the reference voltage to a gate of the second driving transistor in response to the second charging control signal. (Fig. 11 and paragraph 0091, transistor T2 may transfer a reference voltage VREF to the gate node NG which is connected to the gate of the driving transistor TD).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the charging control line and charging transistor of Lim et al to the subpixels of Choi et al so that an image quality change (e.g., a luminance change and/or a color coordinate change) according to a temperature may be reduced or minimized (Lim et al paragraph 0082).
Consider claim 9. Choi et al teaches A display device, (abstract). comprising:
a first pixel including a first sub-pixel; (Fig. 7 and paragraph 0152, a first subpixel SP1).
a second pixel placed in a different pixel row from the first pixel and including a second sub-pixel; (paragraph 0159 and Fig. 7, second subpixel SP2. Paragraph 0170, the first subpixel SP1 can emit light of a first color, the second subpixel SP2 can emit light of a second color different from light of the first color).
wherein the first sub-pixel includes:
a first light-emitting diode; (Fig. 7 and paragraph 0172, first light emitting element ED1).
a first driving transistor having one end connected to the first light-emitting diode and configured to provide a driving current to the first light-emitting diode; (Fig. 7 and paragraph 0153, a first light emitting control transistor EMT1 configured to control a connection between the first light emitting element ED1 and the first driving circuit PAM1).
and wherein the second sub-pixel includes:
a second light-emitting diode; (Fig. 7 and paragraph 0160, the second subpixel SP2 may include a second light emitting element ED2).
a second driving transistor having one end connected to the second light-emitting diode and configured to provide a driving current to the second light-emitting diode; (Fig. 7 and paragraph 0163, The second light emitting control transistor EMT2 can be turned on or off by a second light emitting control signal EM2 applied to its gate node, and control a connection between the second light emitting element ED2 and the second driving circuit PAM2).
Choi et al does not specifically disclose a first charging control line for providing a first charging control signal to the first pixel; and a second charging control line for providing a second charging control signal to the second pixel, wherein the second charging control signal is adjusted to be activated during a time interval different from the first charging control signal when a usage amount of the second pixel exceeds a predetermined value and a first charging transistor configured to provide a reference voltage to a gate of the first driving transistor in response to the first charging control signal and a second charging transistor configured to provide the reference voltage to a gate of the second driving transistor in response to the second charging control signal.
In an analogous art Lim et al teaches a first charging control line for providing a first charging control signal to the first pixel; and a second charging control line for providing a second charging control signal to the second pixel, (Fig. 11 and paragraph 0091, transistor T2 may transfer a reference voltage VREF to the gate node NG in response to a reference signal GR, thus a charging control line.).
wherein the second charging control signal is adjusted to be activated during a time interval different from the first charging control signal (Fig. 12 and paragraph 0103, In the compensation period CMPP, the first emission signal EM1 may have the high level, the second emission signal EM2 may have the low level, the reference signal GR may have the high level, the initialization signal GI may have the low level, and the writing signal GW may have the low level. In some embodiments, as illustrated in FIG. 12, the reference signal GR may be changed to the low level before the compensation period CMPP ends.).
when a usage amount of the second pixel exceeds a predetermined value (paragraph 0125, at least one of the reference voltage and the initialization voltage may be adjusted according to a brightness value (usage amount)).
and a first charging transistor configured to provide a reference voltage to a gate of the first driving transistor in response to the first charging control signal and a second charging transistor configured to provide the reference voltage to a gate of the second driving transistor in response to the second charging control signal. (Fig. 11 and paragraph 0091, transistor T2 may transfer a reference voltage VREF to the gate node NG which is connected to the gate of the driving transistor TD).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the charging control line and charging transistor of Lim et al to the subpixels of Choi et al so that an image quality change (e.g., a luminance change and/or a color coordinate change) according to a temperature may be reduced or minimized (Lim et al paragraph 0082).
Consider claim 10. Choi et al teaches An operating method of a display device, the method comprising:
providing an initialization control signal to each of a first sub-pixel and a second sub-pixel to provide an initialization voltage to one end of a first light-emitting diode of the first sub-pixel and one end of a second light-emitting diode of the second sub-pixel, respectively; (Fig. 2 and paragraph 0084, each subpixel SP disposed in the display panel 110 of the display device 100 according to aspects of the present disclosure may include a light emitting element ED, a driving transistor DRT, a data switching transistor DST, an initialization switching transistor IST, and a storage capacitor Cst.
providing an emission control signal to each of the first sub-pixel and the second sub-pixel to charge the one end of the first light-emitting diode to a voltage at which the first driving transistor is turned off and to charge the one end of the second light-emitting diode to a voltage at which the second driving transistor is turned off; (Fig. 6 and paragraph 0136, The light emitting driving voltage line EMDVL may be arranged for each light emission control circuit EMC or each light emission control circuit column (EMC column).).
and providing a data control signal to each of the first sub-pixel and the second sub-pixel to provide a driving current to the first light-emitting diode by the first driving transistor and to provide a driving current to the second light-emitting diode by the second driving transistor, according to data input to each of the first sub-pixel and the second sub-pixel. (paragraph 0059, The controller 140 can supply a data control signal DCS to the data driving circuit 120 in order to control an operation time of the data driving circuit 120.).
Choi et al does not specifically disclose providing a first charging control signal, which is activated during a first time interval, to the first sub-pixel to provide a reference voltage to a gate of a first driving transistor that provides a driving current to the first light-emitting diode during the first time interval; providing a second charging control signal, which is activated during a second time interval longer than the first time interval, to the second sub-pixel to provide the reference voltage to a gate of a second driving transistor that provides a driving current to the second light-emitting diode during the second time interval;.
In an analogous art Lim et al teaches providing a first charging control signal, which is activated during a first time interval, to the first sub-pixel to provide a reference voltage to a gate of a first driving transistor that provides a driving current to the first light-emitting diode during the first time interval; (Fig. 11 and paragraph 0091, transistor T2 may transfer a reference voltage VREF to the gate node NG in response to a reference signal GR, thus a charging control line.).
providing a second charging control signal, which is activated during a second time interval longer than the first time interval, to the second sub-pixel to provide the reference voltage to a gate of a second driving transistor that provides a driving current to the second light-emitting diode during the second time interval; (Fig. 11 and paragraph 0091, transistor T2 may transfer a reference voltage VREF to the gate node NG in response to a reference signal GR, thus a charging control line. Fig. 12 and paragraph 0103, In the compensation period CMPP, the first emission signal EM1 may have the high level, the second emission signal EM2 may have the low level, the reference signal GR may have the high level, the initialization signal GI may have the low level, and the writing signal GW may have the low level. In some embodiments, as illustrated in FIG. 12, the reference signal GR may be changed to the low level before the compensation period CMPP ends.).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the charging control line and charging transistor of Lim et al to the subpixels of Choi et al so that an image quality change (e.g., a luminance change and/or a color coordinate change) according to a temperature may be reduced or minimized (Lim et al paragraph 0082).
Consider claim 2. Choi et al further teaches The display device of claim 1, wherein the first sub-pixel is configured to emit red light or green light, and the second sub-pixel is configured to emit blue light. (paragraph 0171, light of the first color may be any one of red light, green light, and blue light. Light of the second color may be any one of red light, green light, and blue light.).
Consider claim 3. Choi et al further teaches The display device of claim 1, wherein the first sub-pixel further includes:
a first initialization transistor configured to provide an initialization voltage to the one end of the first driving transistor in response to an initialization control signal; (Fig. 8 and paragraph 0180, a first control initialization switching transistor EMIS1).
a first emission control transistor configured to provide a power supply voltage to the other end of the first driving transistor in response to an emission control signal; (Fig. 8 and paragraph 0181, The first control driving transistor EMDR1 may be connected between the gate node of the first light emitting control transistor EMT1 and a light emitting driving voltage line EMDVL to which a light emitting driving voltage EMVDD is transmitted.).
a first input transistor configured to provide a voltage corresponding to data to the gate of the first driving transistor in response to a data control signal; (paragraph 0182, The first control data switching transistor EMDS1 may include a source node (or a drain node) connected to the gate node M1 of the first control driving transistor EMDR1 and the drain node (or the source node) connected to the first scan line SCL1, and a gate node connected to the first control signal line EMSCL1.).
a first capacitor connected between the gate of the first driving transistor and the one end of the first driving transistor; (paragraph 0187, he first control storage capacitor EMST1 may be connected between the gate node M1 and the source node M2 of the first control driving transistor EMDR1.).
and a second capacitor connected between the one end of the first driving transistor and the power supply voltage. (paragraph 0188, The first light emitting control capacitor CEM1 may be connected between the source node of the first control driving transistor EMDR1 and a light emitting base voltage node Nemvss to which a light emitting base voltage EMVSS is applied.).
Consider claim 4. The display device of claim 3,
wherein the second sub-pixel further includes:
a second initialization transistor configured to provide the initialization voltage to the one end of the second driving transistor in response to the initialization control signal; (Fig. 8 and paragraph 0192, a second control initialization switching transistor EMIS2).
a second emission control transistor configured to provide the power supply voltage to the other end of the second driving transistor in response to the emission control signal; (Fig. 8 and paragraph 0193, The second control driving transistor EMDR2 may be connected between the gate node of the second light emitting control transistor EMT2 and the light emitting driving voltage line EMDVL.).
a second input transistor configured to provide a voltage corresponding to data to the gate of the second driving transistor in response to the data control signal; (Fig. 8 and paragraph 0194, The second control data switching transistor EMDS2 can be turned on or off by the second control signal SIG2, and control a connection between the gate node M1 of the second control driving transistor EMDR2 and the first scan line SCL1.).
a third capacitor connected between the gate of the second driving transistor and the one end of the second driving transistor; (Fig. 8 and paragraph 0197, The second control storage capacitor EMST2 may be connected between the gate node and the source node of the second control driving transistor EMDR2.).
and a fourth capacitor connected between the one end of the second driving transistor and the power supply voltage, wherein a size of the second driving transistor is larger than that of the first driving transistor. (Fig. 8 and paragraph 0198, The second light emitting control capacitor CEM2 may be connected between the source node of the second control driving transistor EMDR2 and the light emitting base voltage node Nemvss.).
Consider claim 5. Lim et al further teaches The display device of claim 1, further comprising: a gate driver configured to generate the first charging control signal and provide the first charging control signal to the first charging control line, and to generate the second charging control signal and provide the second charging control signal to the second charging control line. (Fig. 1 and paragraph 0062, scan driver 140).
Consider claim 6. Lim et al further teaches The display device of claim 5, wherein at least one time interval of a first time interval of the first charging control signal and a second time interval of the second charging control signal is adjusted by the gate driver. (Fig. 1 and paragraph 0062, scan driver 140. Fig. 12 and paragraph 0103, In the compensation period CMPP, the first emission signal EM1 may have the high level, the second emission signal EM2 may have the low level, the reference signal GR may have the high level, the initialization signal GI may have the low level, and the writing signal GW may have the low level. In some embodiments, as illustrated in FIG. 12, the reference signal GR may be changed to the low level before the compensation period CMPP ends.).
Allowable Subject Matter
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Consider claim 7. The prior art of record does not teach or render obvious The display device of claim 5, wherein the gate driver includes: a shift register for generating a charging control signal based on a gate control signal; a first delay circuit for generating the first charging control signal by adjusting an activation interval of the charging control signal; and a second delay circuit for generating the second charging control signal by adjusting the activation interval of the charging control signal.
Consider claim 8. The prior art of record does not teach or render obvious The display device of claim 5, wherein the gate driver receives a first gate control signal generated based on a first clock and a second gate control signal generated based on a second clock having a different duty cycle from the first clock, and wherein the gate driver includes: a first shift register for generating the first charging control signal based on the first gate control signal; and a second shift register for generating the second charging control signal based on the second gate control signal.
Conclusion
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/CHAYCE R BIBBEE/Examiner, Art Unit 2624
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