DETAILED ACTION
Status of the Claims
The response dated 9/17/26 is entered. Claims 1, 2, 10, 11, 16, and 17 are amended. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 9/17/26 have been fully considered but they are directed to newly amended claims and therefore believed to be answered by and thus moot in view of new grounds of rejections presented below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10-13, and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cok, US-20100123694, in view of Mate, US-20110164065.
In regards to claim 1, Cok discloses a modular display apparatus (Fig. 1, 5 imaging device), comprising: a plurality of display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module); and a controller (Fig. 1, 60 controller) configured to control the plurality of display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), wherein the plurality of display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module) comprise a plurality of scan groups (Fig. 1, 32 pixel group), respectively, wherein the controller (Fig. 1, 60 controller) is configured to: transmit an image signal corresponding to the respective display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module) based on an image frame (Par. 0029 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”), wherein the respective scan groups (Fig. 1, 32 pixel group) comprised in a first display module from among the plurality of display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), comprise: a plurality of scan lines (Fig. 1, 40 row electrodes) arranged in one direction; a plurality of data lines (Fig. 1, 42 column electrodes) arranged in a direction perpendicular to the plurality of scan lines (Fig. 1, 40 row electrodes); light emitting diodes (LEDs) (Fig. 1, 30 pixel; Par. 0038 LED) generated at a cross area of the plurality of scan lines (Fig. 1, 40 row electrodes) and the plurality of data lines (Fig. 1, 42 column electrodes); and at least one driver integrated circuit (IC) (Fig. 1, 20 chiplet) configured to provide a scan signal to the plurality of scan lines (Fig. 1, 40 row electrodes) with a progressive scan method during a time period corresponding to the image frame (Par. 0029 sequential/progressive image loading), and provide the image signal to the plurality of data lines (Fig. 1, 42 column electrodes) corresponding to the plurality of scan lines (Fig. 1, 40 row electrodes) through which the scan signal is provided (Par. 0029 sequential/progressive image loading), wherein the plurality of scan groups (Fig. 1, 32 pixel group) comprised in the first display module is connected in a daisy chain method (Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”), and wherein a first driver IC (Fig. 1, 20 chiplet), from among the at least one driver IC (Fig. 1, 20 chiplet) of a first scan group, is configured to sequentially transmit the image signal to the at least one driver IC (Fig. 1, 20 chiplet) of a second scan group (Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”).
Cok does not disclose expressly the controller is further configured to transmit the image signal corresponding to the first display module to the first driver IC of the first scan group from among the plurality of scan groups comprised in the first display module, the image signal corresponding to the first display module being buffered to correspond to a connection order of the plurality of scan groups according to the daisy chain method and a connection order of driver ICs within each scan group.
Mate discloses the controller is further configured to transmit the image signal corresponding to the first display module to the first driver IC of the first scan group from among the plurality of scan groups comprised in the first display module, the image signal corresponding to the first display module being buffered to correspond to a connection order of the plurality of scan groups according to the daisy chain method and a connection order of driver ICs within each scan group (Par. 0042 and 0046 daisy chained displays are buffered according to a connection order).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the driver ICs can be daisy chained and buffered in the manner of Mate. The motivation for doing so would have been to provide image information in the order and position required by the daisy chain method thereby providing proper image alignment.
In regards to claim 10, Cok discloses a control method of a modular display apparatus (Fig. 1, 5 imaging device) formed of a plurality of display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), the control method comprising: transmitting an image signal corresponding to the plurality of display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), respectively, based on an image frame by a controller (Fig. 1, 60 controller; Par. 0029 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”); providing a scan signal to a plurality of scan lines (Fig. 1, 40 row electrodes) comprised in a first display module with a progressive scan method during a time period corresponding to the image frame (Par. 0029 sequential/progressive image loading) by at least one driver integrated circuit (IC) (Fig. 1, 20 chiplet); and providing the image signal to data lines (Fig. 1, 42 column electrodes) corresponding to scan lines (Fig. 1, 40 row electrodes) through which the scan signal is provided from among a plurality of data lines (Fig. 1, 42 column electrodes) arranged in a direction perpendicular to the plurality of scan lines (Fig. 1, 40 row electrodes) by the at least one driver IC (Fig. 1, 20 chiplet; Par. 0029 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”), wherein a plurality of scan groups (Fig. 1, 32 pixel group) comprised in the plurality of display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), respectively, is connected in a daisy chain method (Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”), and wherein the control method further comprises sequentially transmitting the image signal, from a first driver IC (Fig. 1, 20 chiplet), from among the at least one driver IC (Fig. 1, 20 chiplet) of a first scan group, to the at least one driver IC (Fig. 1, 20 chiplet) of a second scan group (Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”).
Cok does not disclose expressly the transmitting the image signal corresponding to the first display module comprises transmitting the image signal corresponding to the first display module to the first driver IC of the first scan group from among the plurality of scan groups comprised in the first display module, the image signal corresponding to the first display module being buffered to correspond to a connection order of the plurality of scan groups according to the daisy chain method and a connection order of driver ICs within each scan group.
Mate discloses the transmitting the image signal corresponding to the first display module comprises transmitting the image signal corresponding to the first display module to the first driver IC of the first scan group from among the plurality of scan groups comprised in the first display module, the image signal corresponding to the first display module being buffered to correspond to a connection order of the plurality of scan groups according to the daisy chain method and a connection order of driver ICs within each scan group (Par. 0042 and 0046 daisy chained displays are buffered according to a connection order).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the driver ICs can be daisy chained and buffered in the manner of Mate. The motivation for doing so would have been to provide image information in the order and position required by the daisy chain method thereby providing proper image alignment.
In regards to claim 16, Cok discloses a display apparatus (Fig. 1, 5 imaging device), comprising: a controller (Fig. 1, 60 controller) configured to control one or more display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), wherein the one or more display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module) include one or more scan groups (Fig. 1, 32 pixel group), wherein the controller (Fig. 1, 60 controller) is configured to: provide an image signal corresponding to the one or more display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module) based on an image frame (Par. 0029 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”), wherein the one or more scan groups (Fig. 1, 32 pixel group) included in a first display module from among the one or more display modules (Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), comprise: one or more scan lines (Fig. 1, 40 row electrodes) arranged in one direction; one or more data lines (Fig. 1, 42 column electrodes) arranged in a direction perpendicular to the one or more scan lines (Fig. 1, 40 row electrodes); one or more light emitting diodes (LEDs) (Fig. 1, 30 pixel; Par. 0038 LED) generated at a cross area of the one or more scan lines (Fig. 1, 40 row electrodes) and the one or more data lines (Fig. 1, 42 column electrodes); and at least one driver integrated circuit (IC) (Fig. 1, 20 chiplet) configured to provide a scan signal to the one or more scan lines (Fig. 1, 40 row electrodes) during a time period corresponding to the image frame (Par. 0029 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”), and provide the image signal to the one or more data lines (Fig. 1, 42 column electrodes) corresponding to the one or more scan lines (Fig. 1, 40 row electrodes) through which the scan signal is provided (Par. 0029 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”), and wherein a first driver IC (Fig. 1, 20 chiplet), from among the at least one driver IC (Fig. 1, 20 chiplet) of a first scan group, is configured to sequentially transmit the image signal to the at least one driver IC (Fig. 1, 20 chiplet) of a second scan group (Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”).
Cok does not disclose expressly the controller is configured to provide the image signal corresponding to the first display module to the first driver IC of the first scan group from among the one or more scan groups included in the first display module, the image signal corresponding to the first display module being buffered to correspond to a connection order of the one or more scan groups according to a daisy chain method and a connection order of driver ICs within each scan group.
Mate discloses the controller is configured to provide the image signal corresponding to the first display module to the first driver IC of the first scan group from among the one or more scan groups included in the first display module, the image signal corresponding to the first display module being buffered to correspond to a connection order of the one or more scan groups according to a daisy chain method and a connection order of driver ICs within each scan group (Par. 0042 and 0046 daisy chained displays are buffered according to a connection order).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the driver ICs can be daisy chained and buffered in the manner of Mate. The motivation for doing so would have been to provide image information in the order and position required by the daisy chain method thereby providing proper image alignment.
In regards to claim 2, Cok and Mate, as combined above, disclose the controller (Cok Fig. 1, 60 controller) is further configured to: obtain the image signal corresponding to the first display module from the image frame (Cok Par. 0060 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”), and transmit the corresponding image signal to the first display module (Cok Par. 0060 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”).
In regards to claim 3, Cok and Mate, as combined above, disclose the controller (Cok Fig. 1, 60 controller) is further configured to: transmit the image signal to at least one driver IC (Cok Fig. 1, 20 chiplet) comprised in the first scan group from among the plurality of scan groups (Cok Fig. 1, 32 pixel group) comprised in the first display module (Cok Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”).
In regards to claim 4, Cok and Mate, as combined above, disclose a memory configured to store the image frame, wherein a size of an image signal corresponding to the first display module corresponds to a bandwidth loadable by the controller (Cok Fig. 1, 60 controller) during the time period corresponding to the image frame from the memory (Cok Par. 0029 “Chiplet controller stores the luminance information in a storage element corresponding to each light-emitting pixel element. The controller then drives the luminance information from each storage element corresponding to pixels in a row through connection pads and group column electrodes to the light-emitting pixel elements in that row.”).
In regards to claim 11, Cok and Mate, as combined above, disclose the transmitting the image signal comprises: obtaining an image signal corresponding to the first display module from the image frame (Cok Par. 0060 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”); and transmitting the image signal corresponding to the first display module (Cok Par. 0060 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”).
In regards to claim 12, Cok and Mate, as combined above, disclose the transmitting the image signal corresponding to the first display module comprises: transmitting the image signal to the at least one driver IC (Cok Fig. 1, 20 chiplet) comprised in the first scan group from among the plurality of scan groups (Cok Fig. 1, 32 pixel group) comprised in the first display module (Cok Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”).
In regards to claim 13, Cok and Mate, as combined above, disclose a size of an image signal corresponding to the plurality of display modules (Cok Fig. 1, 50 control chiplet + 32 pixel groups, i.e. display module), respectively, corresponds to a bandwidth loadable by the controller (Cok Fig. 1, 60 controller) during the time period corresponding to the image frame (Cok Par. 0029 “Chiplet controller stores the luminance information in a storage element corresponding to each light-emitting pixel element. The controller then drives the luminance information from each storage element corresponding to pixels in a row through connection pads and group column electrodes to the light-emitting pixel elements in that row.”).
In regards to claim 17, Cok and Mate, as combined above, disclose the controller (Cok Fig. 1, 60 controller) is further configured to: obtain an image signal corresponding to the first display module from the image frame (Cok Par. 0060 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”), provide the corresponding image signal to the first display module (Cok Par. 0060 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”).
In regards to claim 18, Cok and Mate, as combined above, disclose the controller (Cok Fig. 1, 60 controller) is further configured to: provide the image signal to the at least one driver IC (Cok Fig. 1, 20 chiplet) included in the first scan group from among the one or more scan groups (Cok Fig. 1, 32 pixel group) included in the first display module (Cok Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”).
In regards to claim 19, Cok and Mate, as combined above, disclose at least one memory configured to store the image frame, wherein a size of an image signal corresponding to the first display module corresponds to a bandwidth loadable by the controller (Cok Fig. 1, 60 controller) during the time period corresponding to the image frame from the at least one memory (Cok Par. 0029 “Chiplet controller stores the luminance information in a storage element corresponding to each light-emitting pixel element. The controller then drives the luminance information from each storage element corresponding to pixels in a row through connection pads and group column electrodes to the light-emitting pixel elements in that row.”).
Claim(s) 5-9, 14, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cok, US-20100123694, and Mate, US-20110164065, as combined above in regards to claims 1, 10, and 16, in further view of Hyeon, US-20200082752.
In regards to claim 5, Cok and Mate do not disclose expressly at least one driver IC comprised in a scan group connected last according to the daisy chain method from among the plurality of scan groups comprised in the first display module is configured to transmit an output signal to the controller, and wherein the controller is further configured to identify open LED information corresponding to the first display module based on the output signal.
Hyeon discloses at least one driver IC comprised in a scan group connected last according to the daisy chain method from among the plurality of scan groups comprised in the first display module is configured to transmit an output signal to the controller (Fig. 4, 121 and 131 switches; Par. 0088 feedback signal (called "state data") being fed back from the last driver 122-n in the daisy chain to the controller 130 which is configured to receive/extract the feedback signal using switches 121 and 131), and wherein the controller is further configured to identify open LED information corresponding to the first display module based on the output signal (Par. 0022 “state data signal may include error information of the display panel and monitoring information of the display panel.”, i.e. open LED information).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
In regards to claim 6, Cok and Mate do not disclose the first display module comprises: a switch IC configured to: connect with the controller, transmit, based on the image signal corresponding to the first display module being received from the controller, the image signal to the at least one driver IC comprised in the first scan group from among the plurality of scan groups comprised in the first display module, and transmit, based on an output signal being received from the at least one driver IC comprised in a scan group connected last from among the plurality of scan groups, the output signal to the controller.
Hyeon discloses the first display module (Fig. 4, 130 timing controller + group 1 of 122 driver ICs + switches 121 and 131) comprises: a switch IC (Fig. 4, 121 and 131) configured to: connect with the controller, transmit, based on the image signal corresponding to the first display module being received from the controller, the image signal to the at least one driver IC comprised in the first scan group from among the plurality of scan groups comprised in the first display module, and transmit, based on an output signal being received from the at least one driver IC comprised in a scan group connected last from among the plurality of scan groups, the output signal to the controller (Fig. 4, 121 and 131 switches; Par. 0088 feedback signal (called "state data") being fed back from the last driver 122-n in the daisy chain to the controller 130 which is configured to receive/extract the feedback signal using switches 121 and 131).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
In regards to claim 7, Cok and Mate do not disclose the controller comprises a multiplexer IC, and wherein the multiplexer IC is configured to: connect with the switch IC, and transmit an image signal corresponding to the first display module to the switch IC, or receive the output signal from the switch IC.
Hyeon discloses the controller comprises a multiplexer IC, and wherein the multiplexer IC (Fig. 4, 131 switch) is configured to: connect with the switch IC, and transmit an image signal corresponding to the first display module to the switch IC, or receive the output signal from the switch IC (Fig. 4, 121 and 131 switches; Par. 0088 feedback signal (called "state data") being fed back from the last driver 122-n in the daisy chain to the controller 130 which is configured to receive/extract the feedback signal using switches 121 and 131).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
In regards to claim 8, Cok and Mate do not disclose the controller is configured to identify whether an error of one or more LEDs included in the first display module occurs based on open LED information.
Hyeon discloses the controller is configured to identify whether an error of one or more LEDs included in the first display module occurs based on open LED information (Par. 0022 “state data signal may include error information of the display panel and monitoring information of the display panel.”, i.e. open LED information).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
In regards to claim 9, Cok discloses the controller is further configured to: transmit an image signal corresponding to a second display module to at least one driver IC comprised in a scan group connected first according to the daisy chain method from among the plurality of scan groups comprised in the second display module from among the plurality of display modules (Par. 0021 “The interconnection buss 52 can be daisy-chained from one chiplet 20 to another chiplet 20”; Par. 0060 “The controller processes the signal according to the needs of the imaging device and transmits the processed signal through one or more control busses or busses to each chiplet in the chiplet array”).
Cok and Mate do not disclose the controller is further configured to: receive an output signal corresponding to the second display module from the at least one driver IC comprised in the scan group connected last according to the daisy chain method from among the plurality of scan groups comprised in the second display module.
Hyeon discloses receive an output signal corresponding to the second display module from the at least one driver IC comprised in the scan group connected last according to the daisy chain method from among the plurality of scan groups comprised in the second display module (Par. 0088 feedback signal (called "state data") being fed back from the last driver 122-n in the daisy chain to the controller 130 which is configured to receive/extract the feedback signal using switches 121 and 131).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
In regards to claim 14, Cok and Mate do not disclose expressly transmitting, by the at least one driver IC comprised in a scan group connected last according the daisy chain method from among the plurality of scan groups comprised in the first display module from among the plurality of display modules, an output signal to the controller; and identifying open LED information corresponding to the first display module based on the output signal.
Hyeon discloses transmitting, by the at least one driver IC comprised in a scan group connected last according the daisy chain method from among the plurality of scan groups comprised in the first display module from among the plurality of display modules, an output signal to the controller (Fig. 4, 121 and 131 switches; Par. 0088 feedback signal (called "state data") being fed back from the last driver 122-n in the daisy chain to the controller 130 which is configured to receive/extract the feedback signal using switches 121 and 131), and identifying open LED information corresponding to the first display module based on the output signal (Par. 0022 “state data signal may include error information of the display panel and monitoring information of the display panel.”, i.e. open LED information).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
In regards to claim 15, Cok and Mate do not disclose the plurality of display modules respectively comprise a switch integrated circuit (IC), and wherein the transmitting the image signal comprises: receiving an image signal corresponding to the first display module from the controller by the switch IC comprised in the first display module; transmitting the image signal to the at least one driver IC comprised in the first scan group from among the plurality of scan groups comprised in the first display module; and transmitting, based on an output signal being received from the at least one driver IC comprised in a scan group connected last from among the plurality of scan groups comprised in the first display module by the switch IC comprised in the first display module, the output signal to the controller.
Hyeon discloses the plurality of display modules (Fig. 4, 130 timing controller + group 1 of 122 driver ICs + switches 121 and 131 comprise a switch integrated circuit (IC) (Fig. 4, 121 and 131), and wherein the transmitting the image signal comprises: receiving an image signal corresponding to the first display module from the controller by the switch IC comprised in the first display module; transmitting the image signal to the at least one driver IC comprised in the first scan group from among the plurality of scan groups comprised in the first display module; and transmitting, based on an output signal being received from the at least one driver IC comprised in a scan group connected last from among the plurality of scan groups comprised in the first display module by the switch IC comprised in the first display module, the output signal to the controller (Fig. 4, 121 and 131 switches; Par. 0088 feedback signal (called "state data") being fed back from the last driver 122-n in the daisy chain to the controller 130 which is configured to receive/extract the feedback signal using switches 121 and 131).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
In regards to claim 20, Cok and Mate do not disclose expressly at least one driver IC included in a scan group connected last according to a daisy chain method from among the one or more scan groups included in the first display module is configured to provide an output signal to the controller, and wherein the controller is further configured to identify open LED information corresponding to the first display module based on the output signal.
Hyeon discloses at least one driver IC included in a scan group connected last according to a daisy chain method from among the one or more scan groups included in the first display module is configured to provide an output signal to the controller (Fig. 4, 121 and 131 switches; Par. 0088 feedback signal (called "state data") being fed back from the last driver 122-n in the daisy chain to the controller 130 which is configured to receive/extract the feedback signal using switches 121 and 131), and wherein the controller is further configured to identify open LED information corresponding to the first display module based on the output signal (Par. 0022 “state data signal may include error information of the display panel and monitoring information of the display panel.”, i.e. open LED information).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the daisy chain of Cok and Mate can feedback error information in the manner of Hyeon. The motivation for doing so would have been to decrease complexity of the display panel signal lines (Hyeon Par. 0006).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY A ALMEIDA whose telephone number is (571)270-3143. The examiner can normally be reached M-Th 9AM-730PM.
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/CORY A ALMEIDA/Primary Examiner, Art Unit 2628 10/8/26
