Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claims 1 and 14 lines 10-11 recite “extension lines of two boundaries of the second region close to two adjacent first regions intersect” being uncomprehensive.
The dependent claims are rejected for depending upon a rejected base claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0125565).
Regarding claim 1, Kim teaches a display substrate (100, see ¶58-¶80, and Figs 2-8, 15), a base substrate and a drive circuit layer disposed on the base substrate (see ¶58-¶80), a display region (AA1, AA2) and a non-display region (NA1, NA2), the drive circuit layer (see ¶58-¶80); a pixel drive circuit (PXL) located in the display region (AA1, AA2) and a gate drive circuit (220, 210) located in the non-display region (NA1, NA2);
a boundary of the display region (AA1) comprises an arc-shaped boundary (a corner portion has a curve shape, ¶84, ¶87, ¶211, Fig 5), and a non-display region (NA1, NA2) located on an outside of the arc-shaped boundary is referred to as a rounded corner region (the corner portion, ¶84, ¶87, ¶211-¶248, Fig 5), a plurality of first regions (EG1-EG3 have the emission stages EST21-EST23, (320’), see ¶230-¶232, figs 7-8) and at least one second region (one or more dummy scan stage circuits have DSSTs (220’), see ¶ 258-¶261, Figs 7-8);
the gate drive circuit (220, 210) is configured to provide a drive signal to the pixel drive circuit (PXL), and is partially located within a first region (EG1-EG3),
the second region is located between adjacent first regions (the dummy scan stage circuits DSST are positioned between the second scan stage circuits SST21 to SST2j, See ¶ 259); extension lines of two boundaries of the second region close to two adjacent first regions intersect (Fig 5), and an area of the second region (NA2) is smaller than that of the first region (AA1),
wherein the boundary of the display region further comprises: a straight line boundary connected with the arc-shaped boundary, a non-display region located on an outside of the straight line boundary is referred to as a straight line region, and a part of the gate drive circuit is located in the straight line region (See ¶215-¶296);
the gate drive circuit comprises a plurality of drive circuits (210, 220, 310, 320), wherein an arrangement direction of a plurality of drive circuits located in the rounded corner region (the corner portion) is an extension direction of a boundary of at least one first region (EG1-EG3) close to the second region (DSSTs 220’), and an arrangement direction of a plurality of drive circuits located in the straight line region (Straight line, ¶215) intersects with an extension direction of the straight line boundary; the first region (210, 220, 310, 320), is provided with a partial circuit of each drive circuit (EG1-EG3);
wherein the pixel drive circuit (PXL1, see Figure 15) comprises: a light emitting transistor (T5) and a writing transistor (T2), and the plurality of drive circuits (Fig 3) comprise: a light emitting drive circuit (310) and a scan drive circuit (210), the light emitting drive circuit (310) is electrically connected with the light emitting transistor (T5), the scan drive circuit (210) is electrically connected with the writing transistor (T2), and the scan drive circuit (210) is located on a side of the light emitting drive circuit (310) close to the display region (AA1);
the light emitting drive circuit (320, Fig 4) comprises a plurality of cascaded light emitting shift registers (SST21 to SST2j, Fig 4), and the scan drive circuit (220, fig 4) comprises a plurality of cascaded scan shift registers (See ¶174 to ¶184);
the first region (EG1-EG3) is provided with one light emitting shift register (EST21) and at least one scan shift register (SST21).
As to claim 20, Kim teaches a display apparatus, comprising a display substrate according to claim 1. (See Abstract).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0125565) in view of Na et al. (US 2022/0310013) in view of Toyotaka (US 2012/0287099).
Regarding claim 14, Kim teaches a display substrate (100, see ¶58-¶80, and Figs 2-8, 15), a base substrate and a drive circuit layer disposed on the base substrate (see ¶58-¶80), a display region (AA1, AA2) and a non-display region (NA1, NA2), the drive circuit layer (see ¶58-¶80); a pixel drive circuit (PXL) located in the display region (AA1, AA2) and a gate drive circuit (220, 210) located in the non-display region (NA1, NA2);
a boundary of the display region (AA1) comprises an arc-shaped boundary (a corner portion has a curve shape, ¶84, ¶87, ¶211, Fig 5), and a non-display region (NA1, NA2) located on an outside of the arc-shaped boundary is referred to as a rounded corner region (the corner portion, ¶84, ¶87, ¶211-¶248, Fig 5), a plurality of first regions (EG1-EG3 have the emission stages EST21-EST23, (320’), see ¶230-¶232, figs 7-8) and at least one second region (one or more dummy scan stage circuits have DSSTs (220’), see ¶ 258-¶261, Figs 7-8);
the gate drive circuit (220, 210) is configured to provide a drive signal to the pixel drive circuit (PXL), and is partially located within a first region (EG1-EG3),
the second region is located between adjacent first regions (the dummy scan stage circuits DSST are positioned between the second scan stage circuits SST21 to SST2j, See ¶ 259); extension lines of two boundaries of the second region close to two adjacent first regions intersect (Fig 5), and an area of the second region (NA2) is smaller than that of the first region (AA1),
wherein the boundary of the display region further comprises: a straight line boundary connected with the arc-shaped boundary, a non-display region located on an outside of the straight line boundary is referred to as a straight line region, and a part of the gate drive circuit is located in the straight line region (See ¶215-¶296);
the gate drive circuit comprises a plurality of drive circuits (210, 220, 310, 320), wherein an arrangement direction of a plurality of drive circuits located in the rounded corner region (the corner portion) is an extension direction of a boundary of at least one first region (EG1-EG3) close to the second region (DSSTs 220’), and an arrangement direction of a plurality of drive circuits located in the straight line region (Straight line, ¶215) intersects with an extension direction of the straight line boundary; the first region (210, 220, 310, 320), is provided with a partial circuit of each drive circuit (EG1-EG3);
wherein the pixel drive circuit (PXL1, see Figure 15) comprises: a light emitting transistor (T5) and a writing transistor (T2), and the plurality of drive circuits (Fig 3) comprise: a light emitting drive circuit (310) and a scan drive circuit (210), the light emitting drive circuit (310) is electrically connected with the light emitting transistor (T5), the scan drive circuit (210) is electrically connected with the writing transistor (T2), and the scan drive circuit (210) is located on a side of the light emitting drive circuit (310) close to the display region (AA1);
the light emitting drive circuit (320, Fig 4) comprises a plurality of cascaded light emitting shift registers (SST21 to SST2j, Fig 4), and the scan drive circuit (220, fig 4) comprises a plurality of cascaded scan shift registers (See ¶174 to ¶184);
the first region (EG1-EG3) is provided with one light emitting shift register (EST21) and at least one scan shift register (SST21).
Kim fails to teach
wherein the pixel drive circuit comprises: a light emitting transistor, a writing transistor, and a control transistor, the plurality of drive circuits comprise a light emitting drive circuit, a control drive circuit, and a scan drive circuit, the light emitting drive circuit is electrically connected with the light emitting transistor, the scan drive circuit is electrically connected with the writing transistor, and the control drive circuit is electrically connected with the control transistor, transistor types of the writing transistor and the control transistor are opposite, the control drive circuit is located on a side of the light emitting drive circuit close to the display region, and the scan drive circuit is located on a side of the control drive circuit close to the display region;
one light emitting shift register, at least one control shift register, and at least one scan shift register.
Figures 2-3 and 6 of Na teaches the pixel drive circuit (SP) comprises: a light emitting transistor (ST5), a writing transistor (ST2), and a control transistor (ST3, ¶ 148), a light emitting drive circuit (450), a control drive circuit (410), and a scan drive circuit (420), the light emitting drive circuit (450) is electrically connected with the light emitting transistor (ST5), the scan drive circuit (420) is electrically connected with the writing transistor (ST5), and the control drive circuit (410) is electrically connected with the control transistor (ST3), transistor types of the writing transistor and the control transistor are opposite (p-channel and n-channel, ¶17-¶18), the control drive circuit (420) is located on a side of the light emitting drive circuit (450) close to the display region (DA), and the scan drive circuit (420) is located on a side of the control drive circuit (410) close to the display region (DA); one light emitting shift register (EMn), at least one control shift register (GLn), and at least one scan shift register (GWn).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to combine the teaching of Na with the teaching of Kim. The motivation for doing so would improve the high quality of the image being displayed (Na ¶4-¶5);
Kim and Na fail to teach the control drive circuit comprises a plurality of cascaded control shift registers.
Toyotaka teaches a plurality of cascaded control shift registers (20_1 to 20_m) (See ¶35-¶36, Fig 6A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to combine the teaching of Toyotaka with the teaching of Kim and Na. The motivation for doing so would improve the high quality of driving circuitry (Toyotaka ¶3-¶5).
Allowable Subject Matter
Claims 2-13, and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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KEVIN M NGUYEN
Patent Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628
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