DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,2,8,9 is/are rejected under 35 U.S.C. 103 as being unpatentable over FUJIMURA in view of SASAKI et al (US 2023/0386424).
Regarding claim 1, FUJIMURA disclose an electro-optical device (abstract), comprising: a pixel circuit 110 including a liquid crystal element in which liquid crystal is sandwiched between a pixel electrode 118 and a common electrode 108, and a first switch 116 provided between the pixel electrode and a data line 114 to which a data signal is supplied (Figure 2); a second switch 152, 156, 160 provided between a terminal that receives input of the data signal and the data line (Figure 1, 2). However, FUJIMURA does not expressly disclose and a level shift circuit that level-shifts, during a period in which the second switch is in an off-state, a voltage of the data signal supplied to the data line during a period in which the second switch is in an on-state. In a similar field of endeavor, SASAKI discloses a level shift circuit that level-shifts, during a period in which the second switch is in an off-state, a voltage of the data signal supplied to the data line during a period in which the second switch is in an on-state (Figure 3, 5, 7; paragraph 5, 112,120-122; since the image to be displayed is a binary image, the binary driver 300 generates each of data signals D(j) as a binary signal for which the voltage level can be switched for each horizontal period as illustrated in FIG. 2, and applies either a white voltage or a black voltage to each of data signal lines DLj as the data signal D(j) (j=1 to m)). Therefore, it would have been obvious to a person of ordinary skill in the art to modify FUJIMURA to include the teachings of SASAKI, since SASAKI states that such a modification would reduce circuit complexity of AC driven pixel memory devices. Furthermore, as both inventions are analogous, such a modification would provide additional voltage regulation based on the techniques disclosed by SASAKI.
Regarding claim 2, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. The combination of FUJIMURA and SASAKI further discloses wherein the level shift circuit starts the level shift in a period in which the first switch is in an on-state (paragraph 5, 112,120-122).
Regarding claim 8, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. The combination of FUJIMURA and SASAKI further discloses wherein the level shift circuit is provided between the second switch and the pixel circuit or at a side opposite to a point where the second switch is provided with respect to the pixel circuit (SASAKI – Figure 1, 3; paragraph 24-27).
Regarding claim 9, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. The combination of FUJIMURA and SASAKI further discloses an electronic apparatus, comprising the electro-optical device according to claim 1 (FUJIMURA, SASAKI - abstract).
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior Art fails to disclose circuit layout and connections as disclosed in claims 3,5,7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIEL A BALAOING whose telephone number is (571)272-7317. The examiner can normally be reached 8AM-4AM M-F.
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/ARIEL A BALAOING/ Primary Examiner, Art Unit 2624
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