DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12518679. Although the claims at issue are not identical, they are not patentably distinct from each other because the systems of this application contains similar structures adequate to perform the functions recited in the patent application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. The claims are as follows with the differences highlighted:
19396817
12518679
With reference to claim 1: A scan circuit applicable to driving a plurality of light-emitting-diodes (LED) of a plurality of scan lines of a display panel, comprising: a plurality of switching components, wherein each of the plurality of switching components is electrically connected with one of the plurality of scan lines of the display panel; a plurality of power transistors, disposed corresponding to the plurality of scan lines of the display panel, wherein each of the plurality of power transistors is electrically connected to each of the plurality of scan lines; and a low-dropout regulator circuit, being electrically connected to the plurality of switching components such that a common joint is formed between the low-dropout regulator circuit and the plurality of switching components, and the low-dropout regulator circuit selectively generates an output voltage to at least one of the plurality of scan lines of the display panel through the plurality of switching components.
With reference to claim 1: A scan circuit applicable to driving a plurality of light-emitting-diodes (LED) of a display panel, comprising: a plurality of switching components, wherein each of the plurality of switching components is electrically connected with a scan line of the display panel for determining if the plurality of LEDs connected to the scan line are conductive, a plurality of power transistors, disposed corresponding to a plurality of the scan lines of the display panel, wherein each of the plurality of power transistors is electrically connected to each of the plurality of the scan lines; and a low-dropout regulator circuit, being electrically connected to the plurality of switching components such that a common joint is formed between the low-dropout regulator circuit and the plurality of switching components, and the low-dropout regulator circuit selectively pulls up a voltage level of at least one of the scan lines so as to avoid ghosting imaging on the display panel.
With reference to claim 7: wherein the low-dropout regulator circuit comprises an operational amplifier, a power switch, an enable switch, a plurality of resistors connected in series and a low-dropout capacitance, a positive terminal of the operational amplifier is adapted to receive a reference voltage, a negative terminal of the operational amplifier is selectively coupled with a joint node of the plurality of resistors connected in series, and an output terminal of the operational amplifier is connected with a gate terminal of the power switch.
With reference to claim 8: wherein a drain terminal of the power switch is coupled with a power supplied voltage through the enable switch and a source terminal of the power switch is electrically connected with the plurality of resistors which are connected in series, and outputting a positive voltage to the common joint where the low-dropout regulator circuit and the plurality of switching components are commonly connected.
Claim 1 of this application is being anticipated by claims 1, 7 and 8 of patent 12518679 with similar variation in the non-highlighted limitation above.
19396817
12518679
With reference to claim 11: A scan circuit applicable to driving a plurality of light-emitting-diodes (LED) of a plurality of scan lines of a display panel, comprising: a plurality of switching components, wherein each of the plurality of switching components is electrically connected with one of the plurality of scan lines of the display panel; a plurality of power transistors, disposed corresponding to the plurality of scan lines of the display panel, wherein each of the plurality of power transistors is electrically connected to each of the plurality of scan lines; and a global operational amplifier, being electrically connected to the plurality of switching components such that a common joint is formed between the global operational amplifier and the plurality of switching components, and the global operational amplifier selectively generates an output voltage to at least one of the plurality of scan lines of the display panel through the plurality of switching components.
With reference to claim 11: A scan circuit applicable to driving a plurality of light-emitting-diodes (LED) of a display panel, comprising: a plurality of switching components, wherein each of the plurality of switching components is electrically connected with a scan line of the display panel for determining if the plurality of LEDs connected to the scan line are conductive, a plurality of power transistors, disposed corresponding to a plurality of the scan lines of the display panel, wherein each of the plurality of power transistors is electrically connected to each of the plurality of the scan lines; and a global operational amplifier, being electrically connected to the plurality of switching components such that a common joint is formed between the global operational amplifier and the plurality of switching components, and the global operational amplifier selectively pulls up a voltage level of at least one of the scan lines so as to avoid ghosting imaging on the display panel.
With reference to claim 17: wherein the global operational amplifier includes a positive terminal, a negative terminal and an output terminal, the positive terminal of the global operational amplifier is adapted to receive a reference voltage, the output terminal of the global operational amplifier is electrically connected to the common joint of the plurality of switching components, and the negative terminal and the output terminal of the operational amplifier are commonly connected.
With reference to claim 19: wherein a positive voltage generated at the output terminal of the global operational amplifier is in a range between 1V and 2V.
Claim 11 of this application is being anticipated by claims 11, 17 and 19 of patent 12518679 with similar variation in the non-highlighted limitation above.
Claim 2 is anticipated and comparison
With respect to claim 2.
Claim 3 is anticipated and comparison
With respect to claim 3.
Claim 4 is anticipated and comparison
With respect to claim 4.
Claim 5 is anticipated and comparison
With respect to claim 5.
Claim 6 is anticipated and comparison
With respect to claim 6.
Claim 7 is anticipated and comparison
With respect to claim 7.
Claim 8 is anticipated and comparison
With respect to claim 8.
Claim 9 is anticipated and comparison
With respect to claim 9.
Claim 10 is anticipated and comparison
With respect to claim 10.
Claim 12 is anticipated and comparison
With respect to claim 12.
Claim 13 is anticipated and comparison
With respect to claim 13.
Claim 14 is anticipated and comparison
With respect to claim 14.
Claim 15 is anticipated and comparison
With respect to claim 15.
Claim 16 is anticipated and comparison
With respect to claim 16.
Claim 17 is anticipated and comparison
With respect to claim 17.
Claim 18 is anticipated and comparison
With respect to claim 18.
Claim 19 is anticipated and comparison
With respect to claim 19.
Claim 20 is anticipated and comparison
With respect to claim 20.
Claims 2-10 and 12-20 of this application is being anticipated by and comparable to claims 2-10 and 12-20 of patent 12518679.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IFEDAYO B ILUYOMADE whose telephone number is (571)270-7118. The examiner can normally be reached Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 5712707230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IFEDAYO B ILUYOMADE/Primary Examiner, Art Unit 2624 07/25/2026
Prosecution Insights