DETAILED ACTION
This action is responsive to 11/25/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/743,466, filed on 5/13/2022.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2 and 4-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-4, 11-13, and 15 of U.S. Patent No. 12,507,362 B2, hereinafter, 362 patent. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the 362 patent anticipate the claims in the instant application, and, therefore, a patent to the claims in the instant application would improperly extend the right to exclude granted by a patent to the claims in the instant application should the instant application issue as a patent. The claims are compared with each other in the following:
US 12,507,362 B2
US Application: 19/399,665
1. An electronic device, comprising: a first base;
1. An electronic device, comprising: a base structure;
a first conductive layer disposed on the first base;
a first conductive layer, disposed on the base structure, wherein the first conductive layer comprises a first conductive part and a second conductive part;
an insulating layer disposed on the first conductive layer and having a first hole, wherein the first hole exposes at least a portion of the first conductive layer;
a first insulating layer, disposed on the first conductive layer, wherein the first insulating layer comprises a first hole exposing at least a portion of the first conductive part of the first conductive layer;
a first electronic element disposed on the first base;
a first electronic element, disposed on the base structure;
a second base disposed between the insulating layer and the first electronic element, wherein the second base has a second hole; and
a second insulating layer, disposed between the first insulating layer and the first electronic element, wherein the second insulating layer comprises a second hole; and
a second electronic element electrically connected to the first conductive layer, wherein the first electronic element is electrically connected to the first conductive layer via the second hole and the first hole, and
a second electronic element, electrically connected to the second conductive part of the first conductive layer, wherein the first electronic element is electrically connected to the first conductive part of the first conductive layer through the second hole of the second insulating layer and the first hole of the first insulating layer, and
and in a cross-sectional view of the electronic device, the second hole is different from the first hole in width.
wherein in a cross-sectional view of the electronic device, the first hole has a first width, the second hole has a second width, and the first width is different from the second width.
3. The electronic device of claim 1, wherein in a top view of the electronic device, the first hole is overlapped with the second hole.
2. The electronic device of claim 1, wherein in the cross-sectional view, the first hole of the first insulating layer and the second hole of the second insulating layer are partially overlapped.
4. The electronic device of claim 1, wherein the insulating layer further has a third hole to exposed at least another portion of the first conductive layer.
4. The electronic device of claim 1, wherein the first insulating layer further comprises a third hole exposing at least a portion of the second conductive part of the first conductive layer.
11. The electronic device of claim 1, further comprising a second conductive layer disposed between the first conductive layer and the first base, wherein the second conductive layer is electrically connected to the first conductive layer.
5. The electronic device of claim 1, further comprising: a second conductive layer, disposed between the first conductive layer and the base structure, wherein the second conductive layer is electrically connected to the first conductive part of the first conductive layer.
13. The electronic device of claim 12, wherein the first conductive layer and the second conductive layer are configured to transmit different electrical signals respectively.
6. The electronic device of claim 5, wherein the first conductive layer and the second conductive layer are configured to transmit different electrical signals respectively.
12. The electronic device of claim 1, further comprising a second conductive layer disposed between the first conductive layer and the first base, wherein the second conductive layer is electrically isolated from the first conductive layer.
7. The electronic device of claim 1, further comprising: a second conductive layer, disposed between the first conductive layer and the base structure, wherein the second conductive layer is electrically isolated from the first conductive layer.
15. The electronic device of claim 1, wherein the second electronic element is a chip.
8. The electronic device of claim 1, wherein the second electronic element comprises an electronic chip.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The limitation “wherein in the cross-sectional view, the first width of the first hole is greater than the second width of the second hole” is not taught or suggested by the references of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
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