DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 discloses a non-active area disposed outside the active area where claim 1 recites a non-active area surrounding the active area. It is not clear if the non-active area of claim 14 is the same non-active area of claim 1. For the purpose of art, Examiner interprets a non-active area of claim 14 to be the same non-active area as claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US PGPub 2025/0308432) in view of Yuan et al. (US PGPub 2024/0087516).
Regarding claim 1, Yoon discloses a display panel ([0046] and fig. 1, display panel DP) comprising:
an active area ([0047], “The substrate SUB (or the display panel DP) may include a display area DA in which an image is displayed”) including a plurality of pixel areas ([0047], “A plurality of pixels PX may be disposed in the display area DA of the display panel DP“) and a plurality of scan circuit areas disposed between the plurality of pixel areas ([0052], “the gate drivers 110 may be distributedly disposed in the display area DA (e.g., between pixels PX)”);
a non-active area surrounding the active area and disposed between the active area and an edge of the display panel ([0047], “The substrate SUB (or the display panel DP) may include…a non-display area NDA at the periphery of the display area DA (e.g., an edge area of the display area DA)”);
an emission driver (fig. 1, emission drivers 120) configured to provide an emission control signal ([0050], The emission drivers 120 may supply emission control signals to the plurality of pixels PX through the emission control lines);
a plurality of pixel circuits (fig. 1, plurality of pixels PX) disposed in the plurality of pixel areas ([0047], “A plurality of pixels PX may be disposed in the display area DA of the display panel DP“) and configured to control emission of lights by a plurality of light emitting devices based on the emission control signal ([0050], The emission drivers 120 may supply emission control signals to the plurality of pixels PX through the emission control lines); and
a plurality of scan circuits ([0049], “The gate drivers 110 may include a first gate driver 111 and a second gate driver 112”) disposed in the plurality of scan circuit areas ([0052], “the gate drivers 110 may be distributedly disposed in the display area DA (e.g., between pixels PX)”) and configured to generate a scan signal which is to be supplied to the plurality of pixel circuits ([0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines”).
While Yoon discloses gate driver circuits and emission driver circuits which are controlled by a driving integrated circuit 140, it has been known to have the plurality of gate drivers receive an emission control signal. In a similar field of endeavor of display devices, Yuan discloses wherein the plurality of scan circuits receive the emission control signal to generate the scan signal ([0084] and fig. 7, “the light-emitting control circuit 025 may provide a DC power supply signal to the light-emitting drive circuit 021 connected thereto in response to the light-emitting control signal provided by the light-emitting control signal line EM. Correspondingly, the light-emitting drive circuit 021 may output a drive signal to the light-emitting element 024 in response to the data signal and the DC power supply signal”).
In view of the teachings of Yoon and Yuan, it would have been obvious to one of ordinary skill in the art to have the light-emitting drive circuit controlled based on the light-emitting control circuit, as taught by Yuan, within the system of Yoon where the plurality of sub-pixels 02, the first drive circuit 03 and/or the second drive circuit 04 may all be disposed in the display region A1, which is beneficial to the implementation of a narrow frame (Yuan: [0085]).
Regarding claim 2, the combination of Yoon and Yuan further discloses further comprising:
a first division scan circuit (Yoon: [0049], “The gate drivers 110 may include a first gate driver 111 and a second gate driver 112”) disposed in a first scan circuit area of the plurality of scan circuit areas (Yoon: [0049], “The first gate driver 111 and the second gate driver 112 may be spaced apart from each other in a first direction DR1.”) and electrically connected to a first gate line (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines. More specifically, the gate drivers 110 may generate gate signals, based on first and second gate driver control signals SCS1 and SCS2 (refer to FIG. 3), and provide the gate signals to the gate lines.”), wherein the first division scan circuit generates a first scan signal to output the first scan signal to the first gate line based on a first emission control signal (Yoon: [0048], “The first and second gate driver control signals SCS1 and SCS2 may be supplied from the driving integrated circuit 140. In an embodiment, each of the first and second gate driver control signals SCS1 and SCS2 may be provided in a pulse form alternately having a first gate power voltage VGH (e.g., a voltage having a level of a positive value) (refer to FIG. 3) and a second gate power voltage VGL (e.g., a voltage having a level of a negative value) (refer to FIG. 3). In another embodiment, each of the first and second gate driver control signals SCS1 and SCS2 may be provided in a linear form having the first gate power voltage VGH. The first gate driver control signal SCS1 and the second gate driver control signal SCS2 may be substantially the same signal”); and
first pixel circuits (Yoon: fig. 1, pixels PX) respectively disposed in the plurality of pixel areas (Yoon: [0047], “A plurality of pixels PX may be disposed in the display area DA of the display panel DP“) and electrically connected to the first gate line (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines”), wherein the first pixel circuits receive the first emission control signal and the first scan signal of the first division scan circuit to control emission of light by a light emitting device included in each of the first pixel circuits (Yoon: [0050], “The emission drivers 210 may supply emission control signals to the plurality of pixels PX through the emission control lines”).
Regarding claim 3, the combination of Yoon and Yuan further discloses wherein timings of a gate on voltage and a gate off voltage of the first emission control signal input to the first division scan circuit are synchronized with timings of a gate on voltage and a gate off voltage of the first emission control signal input to the first pixel circuits (Yuan: [0084], “the light-emitting drive circuit 021 may output a drive signal to the light-emitting element 024 in response to the data signal and the DC power supply signal”).
Regarding claim 4, the combination of Yoon and Yuan further discloses further comprising:
a second division scan circuit (Yoon: [0049], “The gate drivers 110 may include a first gate driver 111 and a second gate driver 112”) disposed in a second scan circuit area spaced apart from the first scan circuit area among the plurality of scan circuit areas (Yoon: [0049], “The first gate driver 111 and the second gate driver 112 may be spaced apart from each other in a first direction DR1.”) and electrically connected to the first gate line (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines. More specifically, the gate drivers 110 may generate gate signals, based on first and second gate driver control signals SCS1 and SCS2 (refer to FIG. 3), and provide the gate signals to the gate lines.”),
wherein the second division scan circuit generates the first scan signal to output the first scan signal to the first gate line based on the first emission control signal (Yoon: [0048], “The first and second gate driver control signals SCS1 and SCS2 may be supplied from the driving integrated circuit 140. In an embodiment, each of the first and second gate driver control signals SCS1 and SCS2 may be provided in a pulse form alternately having a first gate power voltage VGH (e.g., a voltage having a level of a positive value) (refer to FIG. 3) and a second gate power voltage VGL (e.g., a voltage having a level of a negative value) (refer to FIG. 3). In another embodiment, each of the first and second gate driver control signals SCS1 and SCS2 may be provided in a linear form having the first gate power voltage VGH. The first gate driver control signal SCS1 and the second gate driver control signal SCS2 may be substantially the same signal”), and
wherein the first pixel circuits receive the first emission control signal and the first scan signal of the second division scan circuit to control emission of light by the light emitting device included in each of the first pixel circuits (Yoon: [0050], “The emission drivers 210 may supply emission control signals to the plurality of pixels PX through the emission control lines”).
Regarding claim 5, the combination of Yoon and Yuan further discloses wherein timings of a gate on voltage and a gate off voltage of the first emission control signal input to the second division scan circuit are synchronized with timings of a gate on voltage and a gate off voltage of the first emission control signal input to the first pixel circuits (Yoon: [0050], “The emission drivers 210 may supply emission control signals to the plurality of pixels PX through the emission control lines. More specifically, the emission drivers 120 may generate emission control signals, based on first and second emission driver control signals ECS1 and ECS2 (refer to FIG. 3), and provide the emission control signals to the emission control lines. The first and second emission driver control signals ECS1 and ECS2 may be supplied from the driving integrated circuit 140. In an embodiment, each of the first and second emission driver control signals ECS1 and ECS2 may be provided in a pulse form having alternately having a first gate power voltage VGH (e.g., a voltage having a level of a positive value) and a second gate power voltage VGL (e.g., a voltage having a level of a negative value). In another embodiment, each of the first and second emission driver control signals ECS1 and ECS2 may be provided in a linear form having the first gate power voltage VGH. The first emission driver control signal ECS1 and the second emission driver control signal ECS2 may be substantially the same signal”).
Regarding claim 6, the combination of Yoon and Yuan further discloses wherein timings of a gate on voltage and a gate off voltage of the first scan signal output from the first division scan circuit is synchronized with timings of a gate on voltage and a gate off voltage of the first scan signal output from the second division scan circuit (Yoon: [0048], “The first and second gate driver control signals SCS1 and SCS2 may be supplied from the driving integrated circuit 140. In an embodiment, each of the first and second gate driver control signals SCS1 and SCS2 may be provided in a pulse form alternately having a first gate power voltage VGH (e.g., a voltage having a level of a positive value) (refer to FIG. 3) and a second gate power voltage VGL (e.g., a voltage having a level of a negative value) (refer to FIG. 3). In another embodiment, each of the first and second gate driver control signals SCS1 and SCS2 may be provided in a linear form having the first gate power voltage VGH. The first gate driver control signal SCS1 and the second gate driver control signal SCS2 may be substantially the same signal”).
Regarding claim 7, the combination of Yoon and Yuan further discloses further comprising:
a second scan circuit electrically connected to a second gate line differing from the first gate line, wherein the second scan circuit receives a second emission control signal having a phase differing from a phase of the first emission control signal to generate a second scan signal having a phase differing from a phase of the first scan signal and output the second scan signal to the second gate line (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines. More specifically, the gate drivers 110 may generate gate signals, based on first and second gate driver control signals SCS1 and SCS2 (refer to FIG. 3), and provide the gate signals to the gate lines.”); and
second pixel circuits electrically connected to the second gate line (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines. More specifically, the gate drivers 110 may generate gate signals, based on first and second gate driver control signals SCS1 and SCS2 (refer to FIG. 3), and provide the gate signals to the gate lines.”), wherein the second pixel circuits receive the second scan signal and the second emission control signal to control emission of light by a light emitting device included in each of the second pixel circuits (Yoon: [0050], “The emission drivers 210 may supply emission control signals to the plurality of pixels PX through the emission control lines”).
Regarding claim 8, the combination of Yoon and Yuan further discloses wherein timings of a gate on voltage and a gate off voltage of the second emission control signal input to the second scan circuit are synchronized with timings of a gate on voltage and a gate off voltage of the second emission control signal input to each of the second pixel circuits (Yoon: [0058], “The driving integrated circuit 140 may compare a waveform of a signal output from the driving integrated circuit 140 with a waveform of a signal fed back and transferred to the driving integrated circuit 140. In an embodiment, the driving integrated circuit 140 may compare a waveform of the first gate driver control signal SCS1 with a waveform of the eleventh feedback signal FDS11 fed back and transferred through the first test pad 131, for example”).
Regarding claim 9, the combination of Yoon and Yuan further discloses wherein the first scan signal output from the first division scan circuit or the second division scan circuit is input to the second scan circuit (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines”).
Regarding claim 10, the combination of Yoon and Yuan further discloses wherein the first scan signal output from the first division scan circuit or the second division scan circuit is input to each of the second pixel circuits (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines”).
Regarding claim 14, the combination of Yoon and Yuan further discloses further comprising a non-active area disposed outside the active area (Yoon: fig. 1, non-display area NDA outside display area DA),
wherein an EM driver supplying the emission control signal to the pixel circuit and the scan circuit is disposed in the non-active area (Yoon: fig. 1, emission drivers 120 shown in non-display area NDA).
Regarding claim 15, Yoon, a display apparatus (fig. 1, display device DD) comprising:
a display panel ([0046] and fig. 1, display panel DP) that includes an active area ([0047], “The substrate SUB (or the display panel DP) may include a display area DA in which an image is displayed”) including a plurality of pixel areas ([0047], “A plurality of pixels PX may be disposed in the display area DA of the display panel DP“) and a plurality of scan circuit areas disposed between the plurality of pixel areas ([0052], “the gate drivers 110 may be distributedly disposed in the display area DA (e.g., between pixels PX)”);
a non-active area surrounding the active area and disposed between the active area and an edge of the display panel ([0047], “The substrate SUB (or the display panel DP) may include…a non-display area NDA at the periphery of the display area DA (e.g., an edge area of the display area DA)”);
an emission driver (fig. 1, emission drivers 120) configured to provide an emission control signal ([0050], The emission drivers 120 may supply emission control signals to the plurality of pixels PX through the emission control lines);
a plurality of pixel circuits (fig. 1, plurality of pixels PX) disposed in the plurality of pixel areas ([0047], “A plurality of pixels PX may be disposed in the display area DA of the display panel DP“) and configured to control emission of lights by a plurality of light emitting devices based on the emission control signal ([0050], The emission drivers 120 may supply emission control signals to the plurality of pixels PX through the emission control lines); and
a plurality of scan circuits ([0049], “The gate drivers 110 may include a first gate driver 111 and a second gate driver 112”) disposed in the plurality of scan circuit areas ([0052], “the gate drivers 110 may be distributedly disposed in the display area DA (e.g., between pixels PX)”) ([0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines”),
wherein each of the plurality of pixel areas extend along a length direction and are spaced apart from each other in a second direction intersecting the length direction (fig. 1, pixels PX where the dots show the pixels being in an array),
each of the plurality of scan circuit areas extend along the length direction and are spaced apart from each other in the second direction (fig. 1, gate drivers 111 and 112 shown in a length direction and spaced apart), and
at least one scan circuit is disposed directly between two pixel circuits ([0052], “the gate drivers 110 may be distributedly disposed in the display area DA (e.g., between pixels PX)”).
While Yoon discloses gate driver circuits and emission driver circuits which are controlled by a driving integrated circuit 140, it has been known to have the plurality of gate drivers receive an emission control signal. In a similar field of endeavor of display devices, Yuan discloses wherein the plurality of scan circuits configured to receive the emission control signal and to generate a scan signal based on the emission control signal ([0084] and fig. 7, “the light-emitting control circuit 025 may provide a DC power supply signal to the light-emitting drive circuit 021 connected thereto in response to the light-emitting control signal provided by the light-emitting control signal line EM. Correspondingly, the light-emitting drive circuit 021 may output a drive signal to the light-emitting element 024 in response to the data signal and the DC power supply signal”).
In view of the teachings of Yoon and Yuan, it would have been obvious to one of ordinary skill in the art to have the light-emitting drive circuit controlled based on the light-emitting control circuit, as taught by Yuan, within the system of Yoon where the plurality of sub-pixels 02, the first drive circuit 03 and/or the second drive circuit 04 may all be disposed in the display region A1, which is beneficial to the implementation of a narrow frame (Yuan: [0085]).
Regarding claim 16, the combination of Yoon and Yuan further discloses wherein the emission driver supplying the emission control signal is disposed in the active area directly between at least two pixels (Yoon: [0052], “the gate drivers 110 and the emission drivers 120 may be integrated with the pixels PX to be formed in the display panel DP”).
Regarding claim 17, the combination of Yoon and Yuan further discloses wherein at least two scan circuits disposed in different scan areas drive a common gate line to supply a common scan signal (Yoon: [0048], “The gate drivers 110 may supply gate signals to the plurality of pixels PX through the gate lines. More specifically, the gate drivers 110 may generate gate signals, based on first and second gate driver control signals SCS1 and SCS2 (refer to FIG. 3), and provide the gate signals to the gate lines”).
Claims 18-20 are within the scope of claims 2, 4 and 7 respectively and are therefore interpreted and rejected based on similar reasoning.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon and Yuan further in view of Lee et al. (US PGPub 2022/0139335).
Regarding claim 11, the combination of Yoon and Yuan further discloses wherein each of the plurality of scan circuits comprises:
a capacitor (Yuan: fig. 10, storage sub-circuit 0213) connected to a first node at one end thereof and connected to an output terminal at the other end thereof (Yuan: fig 10, nodes N1 and N2);
a first transistor (Yuan: fig. 10, transistor 022) connected to the first node at one end thereof and configured to receive a previous scan signal through the other end thereof to charge a voltage of the previous scan signal in the first node (Yuan: [0057], “The reset circuit 022 may provide a reset signal to the light-emitting element 024, to realize reset (may also be referred to as noise reduction) of the light-emitting element 024”);
a second transistor (Yuan: fig. 10, transistor 025) supplied with an initialization voltage through one end thereof, connected to the first node at the other end thereof, and configured to supply the initialization voltage to the first node based on the emission control signal (Yuan: [0062], “The light-emitting control circuit 025 may be connected to the light-emitting drive circuit 021. The light-emitting control circuit 025 may provide a DC power supply signal to the light-emitting drive circuit 021”);
a third transistor (Yuan: fig. 10, transistor 023) supplied with the initialization voltage through one end thereof, connected to the first node at the other end thereof, and configured to supply the initialization voltage to the other end of the capacitor based on the emission control signal (Yuan: [0057], “the compensation circuit 023 may be connected to the light-emitting drive circuit 021 and may provide a compensation signal to the light-emitting drive circuit 021, to enable the light-emitting drive circuit 021 to output the compensated drive signal to the light-emitting element 024 based on the compensation signal, thereby avoiding abnormal light-emitting effect of the light-emitting element 024 due to some reasons (e.g., drift of the threshold voltage of transistors in the light-emitting drive circuit 021), and ensuring the display effect of the sub-pixels 02”); and
While the combination of Yoon and Yuan transistor circuitry controlled by clocks, it has been known to bootstrap a voltage of the clock signal. In a similar field of endeavor of display devices, Lee discloses a fourth transistor supplied with a clock signal through one end thereof, connected to the output terminal at the other end thereof, and configured to bootstrap a voltage of the clock signal to output a current scan signal to the output terminal based on a voltage of the first node ([0141], “When the voltage of the first control node Q is charged and the shift clock CLK1 to CLK4 is inputted, the pull-up transistor Tu is turned on to charge the voltage of the output node up to the gate-on voltage VGL. At this time, the scan pulse SRO(n−1) to SRO(n+2) and the carry signal CAR rise up to the gate-on voltage VGL. When the voltage of the shift clock CLK1 to CLK4 changes to the gate-on voltage VGL, the voltage of the first control node Q is bootstrapped to be increased up to the gate-on voltage of approximately 2VGL. When the voltage of the first control node Q becomes substantially higher than the threshold voltage of the pull-up transistor, the pull-up transistor Tu is turned on”).
In view of the teachings of Yoon, Yuan and Lee, to include the circuity of Lee within the system of Yoon and Yuan, for the purpose of allowing clock distribution lines to have an increased voltage swing.
Regarding claim 12, the combination of Yoon, Yuan and Lee further discloses wherein, in an initialization period, the second and third transistors are turned on based on a gate on voltage of the emission control signal and initializes the first node into the initialization voltage (Yuan: [0113], “In the compensation stage t2, the potential of the second gate drive signal provided by the first drive circuit 03 to the second gate line G2 connected to the pixel P1 jumps from an active potential to an inactive potential, and the reset transistor F1 is turned off. Moreover, the potential of the third gate drive signal provided by the first drive circuit 03 to the third gate line G3 connected to the pixel P1 and the potential of the light-emitting control signal provided by the second drive circuit 04 to the light-emitting control signal line EM connected to the pixel P1 maintain at active potentials, and the compensation transistor M1 and the light-emitting transistor B1 keep being turned-on. The DC power supply terminal VDD continues to provide a DC power supply signal to the first electrode of the drive transistor T1 through the light-emitting transistor B1. Under the coupling action of the storage capacitor C1, the potential of the second node N2 changes with the potential of the compensation signal written to the first node N1 until it changes to Vg (the potential of the first node N1)−Vs (the potential of the second node N2)=Vth (threshold voltage of the drive transistor T1). This process may also be referred to as a process of charging the second node N2 of each sub-pixel through the drive transistor T1 of each sub-pixel respectively”),
in a charge period, the first transistor is turned on based on a gate on voltage of the previous scan signal, charges the first node with a voltage of the previous scan signal, and turns on the fourth transistor (Yuan: [0115], “In the data write stage t3, the potential of the second gate drive signal provided by the first drive circuit 03 to the second gate line G2 connected to the pixel P1 maintains at the inactive potential, and the reset transistor F1 is turned off. In addition, both the potential of the third gate drive signal provided by the first drive circuit 03 to the third gate line G3 connected to the pixel P1 and the potential of the light-emitting control signal provided by the second drive circuit 04 to the light-emitting control signal line EM connected to the pixel P1 jump from the active potential to the inactive potential. The light-emitting transistor B1 and the compensation transistor M1 are turned off. The potential of the first gate drive signal provided by the first drive circuit 03 to the first gate line G1 connected to the pixel P1 jumps from the inactive potential to the active potential, the data write transistor K1 is turned on. The data line D1 provides a data signal (which may also be referred to as gray-scale data) to the first node N1 through the data write transistor K1”), and
in an output period, the fourth transistor receives the clock signal and outputs the current scan signal generated through bootstrapping based on a voltage of the previous scan signal stored in the first node (Yuan: [0116], “In the light-emitting stage t4, both the potential of the second gate drive signal provided by the first drive circuit 03 to the second gate line G2 connected to the pixel P1 and the potential of the third gate drive signal provided by the first drive circuit 03 to the third gate line G3 connected to the pixel P1 maintain at the inactive potential, and the reset transistor F1 and the compensation transistor M1 are turned off. The potential of the first gate drive signal provided by the first drive circuit 03 to the first gate line G1 connected to the pixel P1 jumps from the active potential to the inactive potential, and the data write transistor K1 is turned off. The potential of the light-emitting control signal provided by the second drive circuit 04 to the light-emitting control signal line EM connected to the pixel P1 jumps from the inactive potential to the active potential, the light-emitting transistor B1 is turned on. The drive transistor T1 outputs a drive signal to the second node N2 in response to the DC power supply signal provided by the light-emitting transistor B1 and the potential of the first node N1 at the moment, and the light-emitting element 024 emits light in response to the drive signal”).
Regarding claim 13, the combination of Yoon, Yuan and Lee further discloses wherein each of the plurality of scan circuits further comprises a fifth transistor (Yuan: fig. 10, transistor 0212) connected between the first transistor and the second transistor at one end thereof and connected to the first node at the other end thereof (Yuan: [0090], “The drive sub-circuit 0212 may further be connected to the light-emitting control circuit 025 and the second node N2, and the light-emitting element 024 may be connected to the second node N2. The drive sub-circuit 0212 may be configured to provide a drive signal to the second node N2 in response to the DC power supply signal and the potential of the first node N1”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jia et al. (US PGPub 2026/0057841) discloses a schematic structural diagram of a display panel (fig. 1).
Kim et al. (US PGPub 2025/0292723) discloses a schematic block diagram illustrating a display device (fig. 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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