DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, 8, 15-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (CN 113593475, cited in IDS dated 11/26/2025, see the English Translation of CN 113593475) in view of Zhan et al. (CN 115662349, see the English Translation of CN 115662349).
Regarding claim 1, Dong discloses a pixel circuit (Figs 3-4), comprising:
a driving module (11), a voltage writing module (15, 20), a compensation module (12), a coupling module (capacitor C1), and a first initialization module (16),
wherein the first initialization module (16) is connected to a first terminal of a light-emitting module (e.g., connected to the first terminal N of light emitting element O1);
the compensation module (12) is connected between a control terminal and a first terminal of the driving module (e.g., connected between a control terminal G and a first terminal D of 11), and the compensation module (12) is configured to compensate for a threshold voltage of the driving module in a compensation phase based on a voltage at the first terminal of the driving module obtained after the first terminal is discharged via the driving module and the first initialization module (Figs 4-5; [0131], e.g., in the compensation stage S2, the compensation module 12 is turned on to compensate for a threshold of the driving module 11 after the first terminal D is discharged through the driving module 11 and the first initialization module 16), and
a first terminal of the coupling module is connected to the voltage writing module (e.g., a first terminal of the capacitor C1 is connected to the voltage writing module (15, 20)), a second terminal of the coupling module is connected to the first terminal of the driving module (e.g., a second terminal of the capacitor C1 is connected to the first terminal D of the driving module 11), the voltage writing module is configured to output a fixed voltage to the first terminal of the coupling module at least in the compensation phase (Fig. 5; e.g., output a fixed voltage Vref to the first terminal of C1 in the compensation stage S2), and
output a data voltage to the first terminal of the coupling module in a data writing phase (Figs 4-5; e.g., output a data voltage to the first terminal of C1 in a data writing stage S3), and the coupling module is configured to couple a voltage containing information about the data voltage to the control terminal of the driving module via the compensation module in the data writing phase (e.g., in the data writing stage S3, the compensation module 12 is turned on so that the control terminal G becomes Vinit + Vth + (Vdata-Vref) * (C1z/ (C1z + C2z))),
wherein the data writing phase is later than the compensation phase (Fig. 5; e.g., the data writing stage S3 is later than the compensation stage S2).
Dong does not specifically disclose wherein the first initialization module is connected to a second terminal of the driving module, and the first initialization module is configured to control a magnitude of a current flowing through the driving module.
However, Zhan discloses a pixel circuit (Figs 4-5) comprising
a driving module (10), a compensation module (90), and a first initialization module (420),
wherein the first initialization module (420) is connected to the second terminal of the driving module (e.g., connected to the second terminal of 10), and the first initialization module is configured to control a magnitude of a current flowing through the driving module based on a first initialization voltage connected to the first initialization module (Figs 5-6; e.g., in the initialization stage, controlling the first light emitting control module 20 and the first initialization module 420 to turn on so as to control the driving module to conduct, forming a current path from the first power supply line ELVDD sequentially the first light emitting control module 20, the driving module 10 and the first initialization module 420 to the first initialization signal line Vref1, to reset the charge amount captured by the driving module 10); and
the compensation module is configured to compensate for a threshold voltage of the driving module in a compensation phase based on a voltage at the first terminal of the driving module obtained after a first terminal is discharged via the driving module and the first initialization module (Figs 5-6; e.g., the compensation module 90 is compensate for a threshold voltage of DT in data writing stage and compensation stage t2 after the first terminal is discharged via the driving module 10 and the first initialization module 420).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Zhan in the invention of Dong for providing a first initialization transistor connected to a second terminal of a driving module and configured to control a magnitude of a current flowing through the driving module based on a first initialization voltage so as to reset a charge amount captured by the driving module, thereby improving display uniformity of a display screen.
Regarding claim 2, Dong further discloses the pixel circuit according to claim 1, further comprising a light-emitting module (Fig 4; e.g., a light-emitting element O1), wherein the driving module and the light-emitting module are connected between a first power supply voltage terminal and a second power supply voltage terminal (e.g., between VDD and VSS), and the driving module is configured to drive the light-emitting module to emit light in a light emission phase (Fig. 5; e.g., in the light emitting stage S4, the driving module 11 drives O1 emitting light).
Regarding claim 3, Dong further discloses the pixel circuit according to claim 2, further comprising a first light emission control module and a second light emission control module (Fig. 4; e.g., a first light emission control module 32 and a second light emission control module 31), wherein the second light emission control module is connected between the first power supply voltage terminal and the first terminal of the driving module (e.g., the second light emission control module 31 is connected between VDD and the first terminal D of the driving module 11), the first light emission control module is connected between the second terminal of the driving module and a first terminal of the light-emitting module (e.g., the first light emission control module 32 is connected between the second terminal S of the driving module 11 and the first terminal of O1), and a second terminal of the light-emitting module is connected to the second power supply voltage terminal (e.g., connected to VSS); and a control terminal of the first light emission control module and a control terminal of the second light emission control module are both connected to a light emission control signal line (e.g., the gate of the first light emitting control module 32 is connected to a second light emitting control line EM2 and the gate of the second light emitting control module 31 is connected to a first light emitting control line EM1).
Regarding claim 6, Dong further discloses the pixel circuit according to claim 1, wherein the voltage writing module comprises a data writing unit and a reset unit (Figs 4-5; e.g., a data writing unit 15 and a reset unit 20), a first terminal of the reset unit is connected to the fixed voltage (e.g., a first terminal of the reset unit 20 is connected to the fixed voltage Vref), a second terminal of the reset unit is connected to the first terminal of the coupling module (e.g., a second terminal of the reset unit 20 is connected to the first terminal of the capacitor C1), the first terminal of the coupling module is further connected to a second terminal of the data writing unit (e.g., the first terminal of the capacitor C1 is connected to a second terminal of the data writing unit 15), a first terminal of the data writing unit is connected to a data line (e.g., connected to a data line Data), a control terminal of the data writing unit is connected to a third scan line (e.g., a third scan line Gate), a control terminal of the reset unit is connected to a fourth scan line (e.g., a fourth scan line EM2), the reset unit is configured to transmit the fixed voltage to the first terminal of the coupling module in an initialization phase and continue transmitting the fixed voltage to the first terminal of the coupling module in the compensation phase (Figs 4-5; e.g., transmit the fixed voltage Vref to the first terminal of the capacitor C1 in an initialization phase S1 and in the compensation phase S2), and the data writing unit is configured to transmit the data voltage to the first terminal of the coupling module in the data writing phase (e.g., the data writing unit 15 transmits the data voltage to the first terminal of the capacitor C1 in the data writing phase S3).
Regarding claim 8, Dong further discloses the pixel circuit according to claim 6, further comprising a storage module (Fig. 3; capacitor C2); wherein the storage module is connected between the control terminal of the driving module and a first terminal of a light-emitting module (e.g., connected between the gate terminal G of the driving module 11 and a first terminal of O1).
Regarding claim 15, Dong discloses a driving method for a pixel circuit (Figs 3-4),
wherein the pixel circuit comprises a driving module (11), a voltage writing module (15, 20), a compensation module (12), a coupling module (C1), and a first initialization module (16); and the driving method for a pixel circuit comprises:
in an initialization phase, controlling the voltage writing module to output a fixed voltage to a first terminal of the coupling module (Figs 4-5; e.g., in the initialization state S1, the fixed voltage Vref is output to a first terminal of C1 by the voltage writing module);
in a compensation phase (e.g., in the compensation stage S2), controlling the compensation module to compensate for a threshold voltage of the driving module based on a voltage at a first terminal of the driving module obtained after the first terminal is discharged via the driving module and the first initialization module (Figs 4-5; e.g., in the compensation stage S2, the compensation module 12 is turned on to compensate for a threshold of the driving module 11 after the first terminal D is discharged through the driving module 11 and the first initialization module 16), and controlling the voltage writing module 20 to continue outputting the fixed voltage to the first terminal of the coupling module (Figs 4-5; e.g., the voltage writing module 20 outputs the fixed voltage Vref to the first terminal of C1 in the compensation stage S2); and
in a data writing phase (Fig. 5; e.g., the data writing stage S3),
controlling the voltage writing module to output a data voltage to the first terminal of the coupling module (e.g., the voltage writing module 15 outputs data voltage Data to the first terminal of C1), and
controlling the coupling module to couple a voltage containing information about the data voltage to a control terminal of the driving module via the compensation module (e.g., in the data writing stage S3, the compensation module 12 is turned on so that the control terminal G becomes Vinit + Vth + (Vdata-Vref) * (C1z/ (C1z + C2z))).
Dong does not specifically disclose method comprising in the compensation phase, controlling a magnitude of a current flowing through the driving module via a first initialization voltage.
However, Zhan discloses a driving method for a pixel circuit (Figs 4-5),
wherein the pixel circuit comprises a driving module (10), a compensation module (90), a first initialization module (420), a second initialization module (80), and a light-emitting module (30); and the driving method for a pixel circuit comprises:
in a compensation phase (Fig. 6; a compensation phase comprises initialization stage t1 and data writing stage t2),
controlling the compensation module to compensate for a threshold voltage of the driving module based on a voltage at a first terminal of the driving module obtained after the first terminal is discharged via the driving module and the first initialization module (e.g., in the data writing stage t2, the compensation module 90 is turned on so that the voltage of the control terminal G of the drive module 10 is related to both the data voltage and the threshold voltage of the drive module 10), and
controlling a magnitude of a current flowing through the driving module via a first initialization voltage connected to the first initialization module (e.g., in the initialization stage t1, the first light emitting control module 20. the driving module 10 and the first initialization unit 420 form a conductive path, to reset the charge amount captured by the driving module 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Zhan in the invention of Dong for providing a first initialization transistor connected to a second terminal of a driving module and configured to control a magnitude of a current flowing through the driving module based on a first initialization voltage so as to reset a charge amount captured by the driving module, thereby improving display uniformity of a display screen.
Regarding claim 16, Dong in view of Zhan further discloses the driving method for a pixel circuit according to claim 15, wherein the pixel circuit further comprises a second initialization module (Fig. 5 of Dong, e.g., a second initialization module 16. Fig. 4 of Zhan, e.g., a second initialization module 80), and the method further comprises: at least in the compensation phase, controlling the second initialization module to transmit a second initialization voltage to a first terminal of a light-emitting module (Fig. 6 of Dong, e.g., in the compensation stage S2, a second initialization voltage Vinit is transmitted to a first terminal of O1).
Regarding claim 18, Dong further discloses the driving method for a pixel circuit according to claim 16, wherein the voltage writing module comprises a data writing unit and a reset unit (Fig. 4; e.g., a data writing unit 15 and a reset unit 20); the controlling the voltage writing module to output a fixed voltage to a first terminal of the coupling module comprises: controlling the reset unit to transmit the fixed voltage to the first terminal of the coupling module (e.g., controlling the reset unit 20 to transmit the fixed voltage Vref to the first terminal of C1); and the controlling the voltage writing module to output a data voltage to the first terminal of the coupling module comprises: controlling the data writing unit to output the data voltage to the first terminal of the coupling module (e.g., controlling the data writing unit 15 to output the data voltage data to the first terminal of C1).
Regarding claim 19, Dong further discloses the driving method for a pixel circuit according to claim 16, wherein in the initialization phase (Fig. 5, e.g., the initialization stage S1), the driving method for a pixel circuit further comprises: controlling a first power supply voltage to be transmitted to the first terminal of the driving module (Figs 4-5; e.g., a first power supply voltage VDD is transmitted to a first terminal D of the driving module 11 in the initialization stage S1).
Claim(s) 4, 10-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (CN 113593475, see the English translation of CN 113593475) in view of Zhan et al. (CN 115662349, see the English Translation of CN 115662349), and further in view of Cheng et al. (US 2024/0312416).
Regarding claim 4, Dong in view of Zhan further discloses the pixel circuit according to claim 2, further comprising a second initialization module (Figs 3-4 of Dong, e.g., the second initialization module 16),
wherein the second initialization module is connected between a second initialization signal line and the first terminal of the light-emitting module (Figs 3-4 of Dong, e.g., connected between a second initialization signal line Vini and the first terminal N of O1),
a control terminal of the second initialization module is connected to a first scan line (Figs 3-4 of Dong, e.g., a control terminal is connected to a first scan line Reset), and
the second initialization module is configured to transmit a second initialization voltage on the second initialization signal line to the first terminal of the light-emitting module at least in the compensation phase (Figs 4-5 of Dong, e.g., transmit a second initialization voltage Vinit to the first terminal of O1 in the compensation stage S2);
the first initialization module is connected between a first initialization signal line and the second terminal of the driving module (Figs 4-5 of Zhan, e.g., the first initialization module 420 is connected between a first initialization signal line Vref1 and the second terminal of the driving module 10);
a control terminal of the compensation module is connected to a second scan line (Figs 3-4 of Dong, e.g., a control terminal of the compensation module 12 is connected to a second scan line Reset); and
a start moment of the data writing phase is later than an end moment of the compensation phase (Fig. 5 of Dong, e.g., the data writing stage S3 is later than an end moment of the compensation stage S2).
Zhan further discloses a first initialization voltage on the first initialization signal line and a second initialization voltage are different (Fig. 5, e.g., the first initialization voltage Vref1 and the second initialization voltage Vref2 are different).
Zhan does not specifically disclose wherein the first initialization voltage is greater than the second initialization voltage.
However, Cheng discloses a pixel circuit wherein a first initialization voltage is greater than a second initialization voltage (Fig. 8; [0204], e.g., the first initial voltage Vi1 is greater than the reset voltage Vi3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Cheng in the invention of Zhan for setting a first initialization voltage greater than a second initialization voltage in order to initialize a second terminal of a driving module and a first terminal of a light-emitting module by using different initialization voltages (see [0207]-[0208] of Cheng).
Regarding claim 10, Dong discloses a pixel circuit (Figs 3-4), comprising:
a driving module (11), a compensation module (12), a second initialization module (16), a first light emission control module (32), and a light-emitting module (O1),
wherein the driving module and the light-emitting module are connected between a first power supply voltage terminal and a second power supply voltage terminal (e.g., connected between VDD and VSS), and the driving module is configured to drive the light-emitting module to emit light in a light emission phase (Fig. 5; e.g., the driving module 11 is driving the O1 to emit light in the light emission stage S4);
the first light emission control module is connected between a second terminal of the driving module and a first terminal of the light-emitting module (e.g., the first light emission control module 32 is connected between a second terminal S and a first terminal N of O1),
the second initialization module is connected to the first terminal of the light-emitting module (e.g., the second initialization module 16 is connected to the first terminal N of O1), and the second initialization module is configured to transmit a second initialization voltage to the first terminal of the light-emitting module at least in a compensation phase (Fig. 5; e.g., in the compensation state S2, the second initialization module 16 is turned to transmit a second initialization voltage Vinit to the first terminal N of the light-emitting module); and
the compensation module is connected between a control terminal and a first terminal of the driving module (e.g., the compensation module 12 is connected between a control terminal G and a first terminal D of the driving module 11), and the compensation module is configured to compensate for a threshold voltage of the driving module in the compensation phase based on a voltage at the first terminal of the driving module obtained after the first terminal is discharged via the driving module and the second initialization module (Figs 4-5; e.g., in the compensation stage S2, the compensation module 12 is turned on to compensate for a threshold of the driving module 11 after the first terminal D is discharged through the driving transistor T0 and the second initialization transistor T3).
Dong does not specifically disclose the pixel circuit comprising a first initialization module, the first initialization module is connected to the second terminal of the driving module, and the first initialization module is configured to control a magnitude of a current flowing through the driving module based on a first initialization voltage connected to the first initialization module, wherein the first initialization voltage is greater than the second initialization voltage.
However, Zhan discloses a pixel circuit (Figs 4-5) comprising
a driving module (10), a compensation module (90), a first initialization module (420), a second initialization module (80), a first light emission control module (70), and a light-emitting module (a light emitting element D1),
wherein the driving module and the light-emitting module are connected between a first power supply voltage terminal and a second power supply voltage terminal (e.g., the driving module 10 and the light emitting module D1 are connected between ELVDD and ELVSS), and the driving module is configured to drive the light-emitting module to emit light in a light emission phase (Fig. 6; e.g., in the emission phase t3, the driving transistor DT is driving the light emitting element D1 to emit light);
the first light emission control module is connected between a second terminal of the driving module and a first terminal of the light-emitting module (e.g., the first light emission control module 70 is connected between a second terminal of DT and a first terminal of D1),
the first initialization module is connected to the second terminal of the driving module (e.g., the first initialization module 420 is connected to the second terminal of DT), and the first initialization module is configured to control a magnitude of a current flowing through the driving module based on a first initialization voltage connected to the first initialization module (Figs 5-6; e.g., in the initialization stage, controlling the first light emitting control module and the first initialization module to turn on, so as to write the initialization voltage of the first initialization signal line transmission to the control end of the driving module through the first initialization module, so as to control the driving module to conduct, forming a current path from the first power supply line sequentially the first light emitting control module, the driving module and the first initialization module to the first initialization signal line),
the second initialization module is connected to the first terminal of the light-emitting module (e.g., the second initialization module 80 is connected to the first terminal of D1), and the second initialization module is configured to transmit a second initialization voltage to the first terminal of the light-emitting module at least in a compensation phase (e.g., transmit a second initialization voltage Vref2 to the first terminal of D1 in compensation phase t2),
wherein the first initialization voltage is different from the second initialization voltage (e.g., the voltages transmitted by the first initialization signal line Vref1 and the second initialization signal line Vref2 may be the same or may be different); and
the compensation module is configured to compensate for a threshold voltage of the driving module in the compensation phase based on a voltage at the first terminal of the driving module obtained after the first terminal is discharged via the driving module and the first initialization module (Figs 5-6; e.g., the compensation module 90 is compensate for a threshold voltage of DT in the compensation stage t2 after the first terminal is discharged via the driving module DT and the first initialization module 420).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Zhan in the invention of Dong for providing a first initialization transistor connected to the second terminal of the driving module and configured to control a magnitude of a current flowing through the driving module based on a first initialization voltage so as to reset a charge amount captured by the driving module, thereby improving display uniformity of a display screen.
Dong in view of Zhan does not specifically disclose wherein the first initialization voltage is greater than the second initialization voltage.
However, Cheng discloses a pixel circuit wherein a first initialization voltage is greater than a second initialization voltage (Fig. 8; [0204], e.g., the first initial voltage Vi1 is greater than the reset voltage Vi3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Cheng in the invention of Dong in view of Zhan for setting a first initialization voltage greater than a second initialization voltage in order to initialize a second terminal of a driving module and a first terminal of a light-emitting module by using different initialization voltages (see [0207]-[0208] of Cheng).
Regarding claim 11, Dong further discloses the pixel circuit according to claim 10, further comprising a voltage writing module and a coupling module (Fig. 4, e.g., a voltage writing module (15, 20), wherein the voltage writing module is configured to output a fixed voltage to a first terminal of the coupling module at least in the compensation phase and output a data voltage to the first terminal of the coupling module in a data writing phase (Figs 4-5; e.g., output a fixed voltage Vref to a first terminal of C1 in the compensation phase S2 and output a data voltage Data to the first terminal of C1 in a data writing phase S3), and the coupling module is configured to couple a voltage containing information about the data voltage to the control terminal of the driving module via the compensation module in the data writing phase (Figs 4-5; e.g., in the data writing stage S3, the compensation module 12 is turned on so that the control terminal G becomes Vinit + Vth + (Vdata-Vref) * (C1z/ (C1z + C2z))), wherein the data writing phase is later than the compensation phase (Fig. 5; e.g., the data writing stage S3 is later than the compensation stage S20.
Regarding claim 12, Dong further discloses the pixel circuit according to claim 11, wherein a start moment of the data writing phase is later than an end moment of the compensation phase (Fig. 5; e.g., the data writing stage S3 is later than the compensation stage S2);
the voltage writing module comprises a data writing unit, a control terminal of the data writing unit is connected to a third scan line, a first terminal of the data writing unit is connected to a data line, and a second terminal of the data writing unit is connected to the first terminal of the coupling module; the data line is configured to transmit the fixed voltage in an initialization phase to initialize a potential at the first terminal of the coupling module, continue transmitting the fixed voltage in the compensation phase, and transmit the data voltage in the data writing phase; or,
the voltage writing module (Figs 3-4) comprises a data writing unit (15) and a reset unit (20), a first terminal of the reset unit is connected to the fixed voltage (e.g., the fixed voltage Vref), a second terminal of the reset unit is connected to the first terminal of the coupling module (e.g., a first terminal of C1), a second terminal of the coupling module is connected to the first terminal of the driving module (the first terminal of the driving module 11), the first terminal of the coupling module is further connected to a second terminal of the data writing unit (e.g., a second terminal of the data writing unit 15), a first terminal of the data writing unit is connected to a data line (e.g., data line Data), a control terminal of the data writing unit is connected to a third scan line (e.g., third scan line Gate), a control terminal of the reset unit is connected to a fourth scan line (e.g., fourth scan line EM2), the reset unit is configured to transmit the fixed voltage to the first terminal of the coupling module in an initialization phase and continue transmitting the fixed voltage to the first terminal of the coupling module in the compensation phase (e.g., transmit the fixed voltage Vref in the initialization phase S1 and the compensation phase S2), and the data writing unit is configured to transmit the data voltage to the first terminal of the coupling module in the data writing phase (e.g., transmit the data voltage data in the data writing phase S3).
Regarding claim 13, Dong further discloses the pixel circuit according to claim 11, further comprising a second light emission control module (Fig. 4, e.g., a second light emission control module 31), wherein the second light emission control module is connected between the first power supply voltage terminal and the first terminal of the driving module (e.g., connected between VDD and the first terminal D of the driving module 11), and a control terminal of the first light emission control module and a control terminal of the second light emission control module are both connected to a light emission control signal line (e.g., a control terminal of the first light emission control module 32 is connected to a light emission control signal line EM2. a control terminal of the second light emission control module 31 is connected to a light emission control signal line EM1).
Regarding claim 14, Dong further discloses the pixel circuit according to claim 11, further comprising a storage module (Fig. 4; e.g., a storage capacitor C2), wherein the storage module is connected between the control terminal of the driving module and the first terminal of the light-emitting module (e.g., connected between the control terminal G of the driving module 11 and the first terminal of O1).
Regarding claim 17, Zhan further discloses a first initialization voltage on the first initialization signal line and a second initialization voltage are different (Fig. 5, e.g., the first initialization voltage Vref1 and the second initialization voltage Vref2 are different).
Dong in view of Zhan does not specifically disclose wherein the first initialization voltage is greater than the second initialization voltage.
However, Cheng discloses a pixel circuit wherein a first initialization voltage is greater than a second initialization voltage (Fig. 8; [0204], e.g., the first initial voltage Vi1 is greater than the reset voltage Vi3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Cheng in the invention of Zhan for setting a first initialization voltage greater than a second initialization voltage in order to initialize a second terminal of a driving module and a first terminal of a light-emitting module by using different voltages (see [0207]-[0208] of Cheng).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dong (CN 113593475, see the English translation of CN 113593475) in view of Zhan et al. (CN 115662349, see the English Translation of CN 115662349), and further in view of Park et al. (US 2022/0366835).
Regarding claim 5, Dong further discloses the pixel circuit according to claim 1, wherein the voltage writing module comprises a data writing unit (Figs 4-5; e.g., data writing unit 15), a control terminal of the data writing unit is connected to a third scan line (e.g., a gate terminal of the data writing unit 15 is connected to a third scan line Gate), a first terminal of the data writing unit is connected to a data line (e.g., a first terminal is connected to a data line Data), and a second terminal of the data writing unit is connected to the first terminal of the coupling module (e.g., a second terminal is connected to the first terminal of the capacitor C1); a fix voltage line is configured to transmit the fixed voltage in an initialization phase to initialize a potential at the first terminal of the coupling module, continue transmitting the fixed voltage in the compensation phase (Figs 4-5; e.g., a fix voltage line Vref transmit the fixed voltage Vref in an initialization phase S1 and in the compensation phase S2), and the data line is configured to transmit the data voltage in the data writing phase (Figs 4-5; e.g., transmit the data voltage in the data writing phase S3); and the compensation module is further configured to transmit a potential at the first terminal of the driving module to the control terminal of the driving module in the compensation phase (Fig. 5).
Dong in view of Zhan does not specifically disclose wherein the data line is configured to transmit the fixed voltage.
However, Park discloses a pixel circuit wherein a data line is configured to transmit a fixed voltage (Fig. 3; [0086], e.g., when the second transistor T2 is turned on in the active period, the data voltage Vdata may be supplied to the first node N1. When the second transistor T2 is turned on in the blank period, a bias voltage Vbs may be supplied to the first node N1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Park in the invention of Dong in view of Zhan for transmitting a fixed voltage by using a data line in order to save the number of signal lines and reduce the complexity of a pixel circuit by reusing a data writing unit as a reset unit.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Dong (CN 113593475, see the English translation of CN 113593475) in view of Zhan et al. (CN 115662349, see the English Translation of CN 115662349), and further in view of Huang et al. (US 2024/0304141).
Regarding claim 7, Dong in view of Zhan further discloses the pixel circuit according to claim 6, wherein the first initialization module is connected between a first initialization signal line and the second terminal of the driving module (Zhan, Fig.5, e.g., the first initialization module 420 is connected between a first initialization signal line Vref1).
Dong in view of Zhan does not specifically disclose wherein a first initialization voltage on the first initialization signal line is reused as the fixed voltage, and a control terminal of the first initialization module is connected to the fourth scan line.
However, Huang discloses a pixel circuit (Fig. 3A; [0091]-[0092], e.g., 200) comprising:
a driving module ([0067], e.g., 220), a voltage writing module ([0070], [0080], e.g., data writing transistor T2 and data reset circuit 240), a coupling module ([0069], e.g., capacitor C1), and a first initialization module ([0074], e.g., a first compensation sub-circuit 2301),
wherein the voltage writing module comprises a data writing unit ([0070], e.g., the data writing transistor T2) and a reset unit ([0080], e.g., 240), a first terminal of the reset unit is connected to a fixed voltage ([0081], e.g., Vinit2), a second terminal of the reset unit is connected to a first terminal of the coupling module (e.g., connected to a first terminal of C1), the first terminal of the coupling module is further connected to a second terminal of the data writing unit (e.g., connected to a second terminal of the data writing transistor T2), a first terminal of the data writing unit is connected to a data line (e.g., a data line Vdata), a control terminal of the data writing unit is connected to a third scan line ([0070], e.g., SG1), a control terminal of the reset unit is connected to a fourth scan line ([0081], e.g., RG1), the reset unit is configured to transmit the fixed voltage to the first terminal of the coupling module (e.g., transmit the fixed voltage to the first terminal of C1); and
wherein the first initialization module is connected between a first initialization signal line and the second terminal of the driving module ([0076], e.g., the first compensation sub-circuit 2301 is connected between a first initialization signal line Vinit1), a first initialization voltage on the first initialization signal line is reused as the fixed voltage ([0082], e.g., the first reset voltage line Vinit1 and the second reset voltage line Vinit2 may be the same signal line), and a control terminal of the first initialization module is connected to the fourth scan line ([0095], e.g., a control signal CG1 of a control terminal of the first compensation sub-circuit 2301 and the fourth scan line are same).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Huang in the invention of Dong in view of Zhan for reusing a first initialization voltage on a first initialization signal line as a fixed voltage and connecting a control signal of a first initialization module to a fourth scan line in order to save the number of signal lines, reduce the complexity of a pixel circuit, and save the cost.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhan et al. (CN 115662349, see the English Translation of CN 115662349) in view of Cheng et al. (US 2024/0312416).
Regarding claim 20, Zhan discloses a driving method for a pixel circuit (Figs 4-5),
wherein the pixel circuit comprises a driving module (10), a compensation module (90), a first initialization module (420), a second initialization module (80), and a light-emitting module (30); and the driving method for a pixel circuit comprises:
in a compensation phase (Fig. 6; a compensation phase comprises initialization stage t1 and data writing stage t2),
controlling the compensation module to compensate for a threshold voltage of the driving module based on a voltage at a first terminal of the driving module obtained after the first terminal is discharged via the driving module and the first initialization module (e.g., in the data writing stage t2, the compensation module 90 is turned on so that the voltage of the control terminal G of the drive module 10 is related to both the data voltage and the threshold voltage of the drive module 10),
controlling a magnitude of a current flowing through the driving module via a first initialization voltage connected to the first initialization module (e.g., in the initialization stage t1, the first light emitting control module 20. the driving module 10 and the first initialization unit 420 form a conductive path, to reset the charge amount captured by the driving module 10), and
controlling the second initialization module to transmit a second initialization voltage to a first terminal of the light-emitting module (Figs 5-6; e.g., the second initialization module 80 transmits a second initialization voltage Vref2 to a first terminal of the light-emitting module 30), wherein the first initialization voltage and the second initialization voltage are different (e.g., the voltages transmitted by the first initialization signal line Vref1 and the second initialization signal line Vref2 may be the same or may be different).
Zhan does not specifically disclose wherein the first initialization voltage is greater than the second initialization voltage.
However, Cheng discloses a pixel circuit wherein a first initialization voltage is greater than a second initialization voltage (Fig. 8; [0204], e.g., the first initial voltage Vi1 is greater than the reset voltage Vi3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Cheng in the invention of Zhan for setting a first initialization voltage greater than a second initialization voltage in order to initialize a second terminal of a driving module and a first terminal of a light-emitting module by using different initialization voltages (see [0207]-[0208] of Cheng).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 2013/0088417) discloses a pixel circuit (Fig. 2) comprising a first initialization module and a second initialization module ([0042]-[0047]), wherein the first initialization module (T4) is connected between a first initialization signal line and a first terminal of a light-emitting module, a control terminal of the first initialization module is connected to a first scan line, and the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the first terminal of the light-emitting module, wherein a control terminal of the second initialization module is connected to a second scan line, a first terminal of the second initialization module is connected to a second initialization signal line, a second terminal of the second initialization module is connected to the first terminal of the light-emitting module, and the second initialization module is configured to transmit a second initialization voltage to the first terminal of the light-emitting module (Fig. 2).
LI (US 2024/0071289) discloses a pixel circuit (Figs 23-24) comprising a second initialization module, wherein the second initialization module is connected between a second initialization signal line and a first terminal of a light-emitting module, a control terminal of the second initialization module is connected to a first scan line, and the second initialization module is configured to transmit a second initialization voltage on a second initialization signal line to the first terminal of the light-emitting module in an initialization phase in a write frame of a display cycle (F1), and transmit the second initialization voltage to the first terminal of the light-emitting module in an initialization phase in a hold frame of the same display cycle (F2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HONG ZHOU whose telephone number is (571)270-5372. The examiner can normally be reached 9:00-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN C LEE can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HONG ZHOU/Primary Examiner, Art Unit 2629
Prosecution Insights