Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE (US 20220013619 A1).
Regarding claim 1, LEE (e.g., Fig. 11) discloses a display device comprising:
a first transistor (Fig. 11; transistor ST1) including a first material as a semiconductor material (active layer of transistor ST1 including polysilicon material; [0125]) and including a first gate electrode (gate electrode G1);
a second transistor (Fig. 11; transistor ST3) including a second material as a semiconductor material (active layer of transistor ST3 including oxide material; [0127]) different from the first material and including a second gate electrode (gate electrode G3) arranged in a different layer from the first gate electrode (gate electrode G1);
a first wiring (wire GL3) arranged in the same layer as the first gate electrode (gate electrode G1);
a second wiring (wire GL4) arranged in the same layer as the second gate electrode (gate electrode G3); and
a third wiring (wire VDDL) formed in the same layer as a source electrode or drain electrode (source connection electrode BE3) of the second transistor (transistor ST3) and different from the first wiring (wire GL3) and the second wiring (wire GL4);
wherein the first wiring (wire GL3) and the second wiring (wire GL4) are arranged at a distance from the third wiring (wire VDDL) overlap in a plan view (e.g., Fig. 11).
5. Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIMURA (US 20220189398 A1).
Regarding claim 1, KIMURA (e.g., Figs. 1-2, 6 and 14-17, 22) discloses a display device comprising:
a first transistor (transistor 601 in data driver circuit 22; figs. 2 and 6 and [0224]) including a first material as a semiconductor material (claim 4 and [0028]; silicon material; claim 4 and [0028]) and including a first gate electrode (gate 443; [0230] and [0225]);
a second transistor (transistor 750) including a second material as a semiconductor material (active layer 230 including oxide material; [0354]-[0358] and [0366]) different from the first material and including a second gate electrode (gate 205; Figs. 22-24 and [0371]) arranged in a different layer from the first gate electrode (gate 443);
a first wiring (conductor 451) arranged in the same layer as the first gate electrode (gate 443 of transistor 601);
a second wiring (conductor 455) arranged in the same layer as the second gate electrode (gate 205 of transistor 750); and
a third wiring (conductor 321) formed in the same layer as a source electrode or drain electrode (source/drain 311/313) of the second transistor (transistor 750) and different from the first wiring (conductor 451) and the second wiring (conductor 455);
wherein the first wiring (conductor 451) and the second wiring (conductor 455) are arranged at a distance from the third wiring (conductor 317) overlap in a plan view (e.g., Figs. 15-17)
Regarding claim 2, KIMURA (e.g., Figs. 1-2, 6 and 14-17, 22) discloses the display device according to claim 1, further comprising: a plurality of pixels (pixels 34) arranged in a matrix in a first direction and a second direction intersecting the first direction (Fig. 1); a first driving circuit (e.g., Figs. 1 and 9; driving circuit 22) electrically connected to the plurality of pixels (pixels 34); an IC chip (e.g., Figs. 6 and 2; driving circuit 40); and a plurality of data signal supply lines (e.g., Figs. 6 and 2; signal lines) arranged between the first driving circuit (driving circuit 22) and the IC chip (driving circuit 40) and connecting the first driving circuit (driving circuit 22) and the IC chip (driving circuit 40), wherein the first material is polysilicon (claim 4 and [0028]; first transistor 601 including silicon or polycrystalline silicon material; claim 4 and [0028], [0004]), the second material is an oxide semiconductor (second transistor 750 including oxide material; [0354]-[0358] and [0366]), each of the plurality of pixels (pixel 34) includes the second transistor (transistor 750), and the first driving circuit (data driver circuit 22) includes the first transistor (transistor 601).
Allowable Subject Matter
6. Claims 3-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The present invention is directed to a display device. The closet prior arts, KIMURA (US 20220189398 A1), and KAWASHIMA (US 20220319462 A1), LEE (US 20220013619 A1), individually or in combination, discloses a display device similar to the claimed invention, comprising: a first transistor including a first material as a semiconductor material and including a first gate electrode; a second transistor including a second material as a semiconductor material different from the first material and including a second gate electrode arranged in a layer different from the first gate electrode; a first wiring arranged in the same layer as the first gate electrode; a second wiring arranged in the same layer as the second gate electrode; and a third wiring formed in the same layer as a source electrode or drain electrode of the second transistor and different from the first wiring and the second wiring, wherein the first wiring and the second wiring overlap in a plan view, and the first wiring and the second wiring are arranged at a distance from the third wiring in a plan view; and a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction; a first driving circuit electrically connected to the plurality of pixels; an IC chip; and a plurality of data signal supply lines arranged between the first driving circuit and the IC chip and connecting the first driving circuit and the IC chip, wherein the first material is polysilicon, the second material is an oxide semiconductor, each of the plurality of pixels includes the second transistor, and the first driving circuit includes the first transistor. However, the closet prior arts of record fail to teach wherein the plurality of data signal supply lines includes a first signal line having a positive polarity, a second signal line having a positive polarity, and a third signal line having a positive polarity, the first signal line includes the second wiring and a third wiring, the second signal line includes a second wiring and the third wiring, the third signal line includes the first wiring, a second wiring and a third wiring, the first wiring of the third signal line intersects the third wiring of the second signal line in a plan view, the first wiring of the first signal line and the second wiring of the second signal line overlap in a plan view, and the first wiring of the first signal line and the second wiring of the second signal line are arranged at a distance from the third wiring of the third signal line in a plan view.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
Prosecution Insights