DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Shepelev et al. (USPN 2022/0139273 A1) in view of Oh et al. (USPN 2016/0064421 A1).
As to claim 1, Shepelev teaches a light emitting display device, comprising:
a display panel including a display region where pixels are arranged, a non-display region outside the display region, and a folding region extending along a direction (see at least Fig. 2: flexible display panel 210, active area 212, and bend axis 202 extending horizontally through active area 212 and the peripheral region outside active area 212; [0028] “Example suitable display technologies include light emitting diode (LED), organic LED (OLED) … and the array of access transistors M (and pixel elements 101) may be disposed in an active area 112 of the display panel 110”; [0037] “the display panel 110 may be a flexible display panel (such as a flexible OLED display) … For example, a flexible display panel may be folded or rolled to create a smaller footprint”; [0039] “the flexible display panel 210 may be a flexible OLED display … The front plane of the flexible display panel 210 includes an array of display pixels … and the backplane of the display panel includes an array of access transistors … coupled to the display pixels … the display pixels and access transistors are disposed within an active area 212 of the display panel 210”; [0040] “the flexible display panel 210 may be configured to bend or fold along a first axis 202 (also referred to herein as a “bend axis”) … the bend axis 202 bifurcates the display panel 210”; [0044] “the strain sensors 214 are disposed along the perimeter of the display panel 210, outside the active area 212”);
a strain sensor located in the folding region in the non-display region (see at least Fig. 2: strain sensors 214 positioned along bend axis 202 in the peripheral region outside active area 212; [0040] “the flexible display panel 210 may include one or more strain sensors 214 to detect the strain in the display panel 210 .. the strain sensors 214 may be disposed in locations or layers of the display panel 210 under maximum strain (when the display panel 210 is folded)”; [0044] “the strain sensors 214 are disposed along the perimeter of the display panel 210, outside the active area 212”; [0067] “the piezoresistive sensors may be disposed along the perimeter of the display panel, outside an active area”));
wherein the pixel located in the folding region in the display region includes a plurality of transistors, and a light emitting diode connected to one of the plurality of transistors (see at least Fig. 2: bend axis 202 extends through active area 212; [0028] “thin-film transistor (TFT) technology is commonly used in the backplane (such as in LCDs and OLED displays)”; [0039] “the flexible display panel 210 may be a flexible OLED display …. the flexible display panel 210 may include an OLED front plane fabricated on the flexible substrate … The front plane of the flexible display panel 210 includes an array of display pixels … and the backplane of the display panel includes an array of access transistors … coupled to the display pixels … the display pixels and access transistors are disposed within an active area 212 of the display panel 210”).
Shepelev does not directly teach wherein the plurality of transistors includes a first thin film transistor on a substrate, and a second thin film transistor on an insulating layer which is on the first thin film transistor, and wherein the first thin film transistor includes a first semiconductor layer including polycrystalline silicon, and the second thin film transistor includes a second semiconductor layer including oxide semiconductor.
Oh teaches wherein the pixel in the display region includes a plurality of transistors, and a light emitting diode connected to one of the plurality of transistors (see at least [0083] “a pixel of an organic light emitting display device includes an organic light emitting diode (OLED), a storage capacitor, one or more switching elements ST1, ST2, ST3, and ST4, and a driving element DT … An anode of the OLED is connected to the second node B”; [0110] “the active matrix type organic light emitting diode display comprises a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor ST, and an organic light emitting diode OLE connected to the driving thin film transistor DT”; [0112] “The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE”),
wherein the plurality of transistors includes a first thin film transistor on a substrate, and a second thin film transistor on an insulating layer which is on the first thin film transistor (see at least [0046] “A second buffer layer BUF2 is formed on the first interlayer insulating layer ILD1 to cover the first TFT T1. The second buffer layer BUF2 serves as a protective layer or a passivation layer protecting the first TFT T1. Also, the second buffer layer BUF2 planarizes the surface on which the second TFT T2 is disposed”; [0057] “an oxide semiconductor material is deposited on the second buffer layer BUF2 and patterned … to form a second semiconductor pattern ACT2”; [0063] “the thin film transistor (TFT) substrate for a flat panel display according to the second embodiment includes a first TFT T1 disposed on a substrate SUBS and a second TFT T2 disposed on the first TFT T1. At least a portion of the second TFT T2 overlaps the first TFT T1 in a thickness direction or in a vertical direction (z)”; [0064] “The second buffer layer BUF2 covers the first TFT T1 and planarizes a surface on which the second TFT T2 is formed”; [0065] “The second TFT T2 includes a second gate G2 formed on the second buffer layer BUF2”; [0066] “insulating material … insulating layers”), and
wherein the first thin film transistor includes a first semiconductor layer including polycrystalline silicon, and the second thin film transistor includes a second semiconductor layer including oxide semiconductor (see at least [0038] “A first semiconductor pattern ACT1 of a first TFT T1 includes a polycrystalline semiconductor material such as low temperature polysilicon. A second semiconductor pattern ACT2 of a second TFT T2 includes an oxide semiconductor”; [0064] “A first semiconductor pattern ACT1 of the first TFT T1 includes a polycrystalline semiconductor material, such as LTPS”; [0065] “The second semiconductor pattern ACT2 of the second TFT T2 includes an oxide semiconductor”).
It would have been obvious to one of ordinary skill in the art to modify the pixels of Shepelev’s flexible OLED display to include Oh’s vertically arranged polycrystalline-silicon and oxide-semiconductor TFTs in order to reduce power consumption, improve video quality, and minimize the area occupied by the TFTs, as taught by Oh (see [0061], [0096]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shepelev et al. (USPN 2022/0139273 A1) in view of Oh et al. (USPN 2016/0064421 A1), further in view of Gupta et al. (USPN 2014/0225838 A1).
As to claim 2, Shepelev and Oh teach the light emitting display device of claim 1 (see above rejection).
Shepelev and Oh do not directly teach a bank layer covering an edge of an anode electrode of the light emitting diode in the folding region in the display region; and a touch layer disposed on the light emitting diode in the folding region in the display region, and including touch electrodes and touch electrode connection lines connecting the touch electrodes, wherein at least portion of the touch electrode connection lines overlaps the bank layer.
Gupta teaches a bank layer covering an edge of an anode electrode of the light emitting diode (see at least Figs. 10 and 15B-1 – 15B-6: organic passivation 1513/PDL is disposed between adjacent OLED pixel structures and extends over peripheral edge portions of anodes 1506; [0066] “Anode 1007 can provide an electrical connection between the circuit elements of TFT layer 1001 and OLED layer 1009 … PDL 1005 can be a layer for electrically isolating adjacent anodes 1007 and OLED layers 1009”; [0087] “Anodes 1506 can be formed on PLN 1511. Anodes 1506 can correspond to anodes 1007 in FIG. 10. OLED layers 1505 can be formed on anodes 1506. … Anode 1506 and OLED layer 1505 stacks can be electrically isolated from each other by organic passivation 1513. Organic passivation can correspond to PDL 1005 in FIG. 10”);
a touch layer disposed on the light emitting diode in the display region, and including touch electrodes and touch electrode connection lines connecting the touch electrodes (see at least figs. 15A and 15B-1 – 15B-6: drive line segments 1501 and sense line 1503 constitute touch electrodes disposed over the OLED layers 1505; [0032] “integrating touch circuitry into an LED or OLED display pixel stackup (i.e., the stacked material layers forming the LED or OLED display pixels) can be desired (in-cell touch)”; [0041] “each common electrode 401 can serve as a multi-function circuit element that can operate as display circuitry … and can also operate as touch sensing circuitry … a common electrode 401 can operate as a capacitive part of a drive line (i.e., a drive line segment 403) or as a capacitive sense line 405”; [0086] “Drive line segments 1501 can be on either side of sense line 1503, … Both drive line segments 1501 and sense line 1503 can be formed of cathode 1011 of FIG. 10. OLED layers 1505 can be underneath drive line segments 1501 and sense line 1503 .. Drive line segments 1501 can be electrically connected to each other by way of drive line connection 1507. … Drive line connection 1507 can be electrically connected to drive line segments 1501 by way of vias 1509”; [0092] “Drive line connection 1507 can be formed inside vias 1509 and across TFE2 1519 … drive line segments 1501 can be electrically connected to each other through vias 1509 and drive line connection 1507”);
wherein at least portion of the touch electrode connection lines overlaps the bank layer (see at least Figs. 15B-1 – 15B-6: note Fig. 15B-6 illustrates drive line connection 1507 extending across the OLED pixel stack and vertically over portions of organic passivation 1513/PDL disposed at and between peripheral portions of the underlying anodes 1506. Therefore, at least a portion of touch-electrode drive line connection 1507 overlaps the organic passivation 1513/PDL corresponding to the claimed bank layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the flexible OLED display resulting from the combination of Shepelev and Oh to include Gupta’s integrated touch-sensing structure, including the bank/PDL structure, touch electrodes disposed over the OLED elements, and connection lines connecting the touch electrodes, in order to provide integrated touch-input functionality in the OLED display (see Gupta [0032]). Applying Gupta’s integrated touch structure to the active display area of Shepelev, including the portion of active area 212 through which bend axis 202 extends, would provide the recited bank layer and touch layer in the folding region in the display region.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shepelev et al. (USPN 2022/0139273 A1) in view of Oh et al. (USPN 2016/0064421 A1), further in view of Xiong (USPN 2024/0177666 A1).
As to claim 3, the combination of Shepelev and Oh teach the light emitting display device of claim 1 (see above rejection).
Shepelev does not directly teach wherein the plurality of transistors includes: a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first transistor including a gate electrode receiving a first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node; and a second transistor including a gate electrode receiving a second scan signal, a first electrode connected to a data line, and a second electrode connected to the second node.
Xiong teaches wherein the plurality of transistors includes: a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node (see at least fig. 7: driving transistor T1; and [0057] “The driving circuit 101 may include a first transistor T1”; [0058] “A gate of the first transistor T1 is electrically connected to a first node N1, a first electrode of the first transistor T1 is electrically connected to a second node N2, and a second electrode of the first transistor T1 is electrically connected to a third node N3”);
a first transistor including a gate electrode receiving a first scan signal, a first electrode connected to the first node, and a second electrode connected to the third node (see at least fig. 7: first transistor T3, first scan signal S2; [0061] A gate of the third transistor T3 is electrically connected to the second scan signal terminal S2, a first electrode of the third transistor T3 is electrically connected to the first node N1, a second electrode of the third transistor T3 is electrically connected to the third node N3”); and
a second transistor including a gate electrode receiving a second scan signal, a first electrode connected to a data line, and a second electrode connected to the second node (see at least fig. 7: second transistor T2, second scan signal is S1; [0060] “A gate of the second transistor T2 is electrically connected to the first scan signal terminal S1, a first electrode of the second transistor T2 is electrically connected to the data signal terminal data, and a second electrode of the second transistor T2 is electrically connected to the second node N2.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light-emitting display device of Shepelev and Oh to include the transistor configuration taught by Xiong, in order to provide a known pixel driving circuit in which scan-controlled transistors selectively connect the data line and nodes of the driving transistor, thereby controlling application of the data signal and operation of the driving transistor. Such a modification would have amounted to the use of a known pixel-circuit configuration in a known light-emitting display device to obtain predictable results.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Shepelev et al. (USPN 2022/0139273 A1) in view of Oh et al. (USPN 2016/0064421 A1), in view of Xiong (USPN 2024/0177666 A1), and further in view of Shi et al. (USPN 2024/0135885 A1).
As to claim 4, the combination of Shepelev, Oh and Xiong teach the light emitting display device of claim 3 (see above rejection), wherein the plurality of transistors includes: a third transistor including a gate electrode receiving an emission control signal, a first electrode connected to a fourth node and receiving a high-potential driving voltage, and a second electrode connected to the second node (see Xiong at least fig. 7: third transistor T5; [0063] “A gate of the fifth transistor T5 is electrically connected to a light emission control signal terminal EM, a first electrode of the fifth transistor T5 is electrically connected to a second direct voltage signal terminal PVDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2.”; [0084] “second direct voltage signal lines PVDD may output direct voltage signals with positive voltage values.”); and
a fourth transistor including a gate electrode receiving the emission control signal, a first electrode connected to the third node, and a second electrode connected to a fifth node that is connected to the light emitting diode (see Xiong at least fig. 7: fourth transistor T6, fifth node N4; [0059] “The light-emitting element D is electrically connected to a fourth node N4”; [0064] “A gate of the sixth transistor T6 is electrically connected to the light emission control signal terminal EM, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.”).
Shepelev, Oh and Xiong do not directly teach wherein the pixel includes a capacitor connected between the first node and the fourth node.
Shi teaches wherein the pixel includes a capacitor connected between the first node and the fourth node (see at least fig. 2: C; [0058] a second terminal of the storage capacitor C is electrically connected with the first power terminal VDD, and a first terminal of the storage capacitor C is electrically connected with a gate of the third transistor T3; …; a source of the fifth transistor T5 is electrically connected to the first power terminal VDD, a drain of the fifth transistor T5 is electrically connected to the source of the third transistor T3”; [0059] “the first power terminal VDD is a voltage source to output a first voltage, which is a constant positive voltage”; [0082] “The storage capacitor C is mainly configured to store the data voltage”).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to incorporate Shi’s conventional storage-capacitor arrangement connecting the storage capacitor between the driving-transistor gate node and the high-potential power node into Xiong’s pixel circuit and the light-emitting display device of Shepelev and Oh in order to maintain the driving-transistor gate voltage for controlling light emission.
As to claim 5, the combination of Shepelev, Oh, Xiong and Shi teach the light emitting display device of claim 4 (see above rejection), wherein the driving transistor is formed of the first thin film transistor, and wherein one of the first to fourth transistors is formed of the second thin film transistor (see Shi at least figs. 2-5: driving transistor T3, first transistor T2, second transistor T4, third transistor T5, fourth transistor T6; [0072] “since the data writing sub-circuit 7 includes the fourth transistor T4 and the fourth transistor T4 is an oxide thin film transistor, the problem of display abnormality caused by the voltage at the first terminal of the driving sub-circuit 1 being pulled up due to the leakage current of the fourth transistor T4 can be greatly alleviated.”; [0085] “The data writing sub-circuit 7 includes a fourth transistor T4, the driving sub-circuit 1 includes a third transistor T3”; [0086] “both the first transistor T1 and the fourth transistor T4 in the pixel driving circuit are oxide thin film transistors ... The third transistor T3, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are low-temperature polysilicon transistors”).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Shepelev et al. (USPN 2022/0139273 A1) in view of Oh et al. (USPN 2016/0064421 A1), further in view of Lee at al. (USPN 2016/0190522 A1).
As to claim 6, the combination of Shepelev and Oh teach the light emitting display device of claim 1 (see above rejection).
Shepelev and Oh do not directly teach further comprising a gate driving portion and a low-potential driving power line in the folding region in the non-display region, wherein the low-potential driving power line is located outside the gate driving portion.
Lee teaches a gate driving portion and a low-potential driving power line in the folding region in the non-display region, wherein the low-potential driving power line is located outside the gate driving portion (see at least figs. 15A-B, 16A: low-potential driving power line VSS; [0201] FIGS. 15A and 15B, each shows a cross-sectional view of a flexible display along the line A-A′ marked in FIG. 1, …, the GIP may be at the left and/or the right side of the central active area”; [0202] “the inactive areas with the GIP circuit can be the bend portions of the flexible display 100. In this case, the part of the base layer 106 where the GIP is disposed on is curved away from the plane of the part of the base layer 106 where the active area is provided therein.”; [0211] “a bend allowance section may be provided between the GIP area and the area positioned even further out toward the scribe line of the base layer 106, which may be referred in the present disclosure as the GIP input signal line area. Various signal lines, including but not limited to, the data signal lines from the display D-IC and the VDD/VSS lines from the power supply unit and/or other components of the flexible display 100 disposed on some other part of the base layer 106 or on a separate printed circuit attached to the base layer 106, may be routed in the GIP input signal line area.”; [0212] “Accordingly, a bend allowance section can be provided between the GIP input signal line area and the GIP area so that the GIP input signal line area can be bent away from the plane of the base layer 106 with the GIP area. .., conductive lines extending across the bend allowance section between the GIP input signal line area and the GIP area can connect the GIP input signal lines to the corresponding part of the GIP.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shepelev and Oh to include Lee’s GIP circuit and VSS power line arrangement in the non-display folding region in order to accommodate the gate-driving circuitry and power lines in the bendable peripheral region and reduce the apparent border size of the display (see Lee [0202], [0211]-[0212], [0275]).
Claims 7-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shepelev et al. (USPN 2022/0139273 A1) in view of Oh et al. (USPN 2016/0064421 A1), further in view of Ahn et al. (USPN 2011/0175942 A1).
As to claim 7, the combination of Shepelev and Oh teach the light emitting display device of claim 1 (see above rejection), further comprising: an input voltage to the strain sensor; a controller receiving an output voltage of the strain sensor (see Shepelev at least [0042], “a supply voltage (VS) is coupled to the intersection of resistors R1 and R4 … An output voltage (VO) may be measured between the intersection of resistors R1 and R2 and the intersection of resistors R3 and R4”; [0043] “the display controller 220 may be coupled to the intersection of resistors R1 and R2 and the intersection of resistors R3 and R4, via respective leads, to detect the output voltage VO”; [0045] “a supply voltage (VS) may be coupled to the intersection of strain gauges S1 and S4 … An output voltage (VO) may be measured between the intersection of strain gauges S1 and S2 and the intersection of strain gauges S3 and S4”; [0048] “the display controller 220 is configured to receive sensor signals from the strain sensors 214”; [0049] “the sensor signals received from each strain sensor 214 may be representative of its output voltage VO”).
Shepelev and Oh do not directly teach a gamma reference voltage circuit; and a power supply circuit providing a reference voltage to the gamma reference voltage circuit.
Ahn teaches a gamma reference voltage circuit; and a power supply circuit providing a reference voltage to the gamma reference voltage circuit (see at least [0033] “a gamma reference voltage output circuit of a source driver … includes a reference voltage generation unit 31, a gamma buffer unit 32, a TN gamma voltage generation unit 33A, an IPS gamma voltage generation unit 33B”; [0034] “The reference voltage generation unit 31 … is configured to divide a voltage difference between power supply voltages Vin1 and Vin2 … and generate a plurality of gamma reference voltages Vref0 through Vref6”; [0035] “The gamma buffer unit 32 … is configured to stabilize and output the gamma reference voltages Vref0 through Vref6 which are outputted from the reference voltage generation unit 31”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Ahn’s gamma-reference-voltage circuitry in Shepelev and Oh’s display to provide the supply voltage required by Shepelev’s strain sensor, thereby using existing display voltage-generation circuitry to provide the sensor excitation voltage rather than requiring separate voltage-generation circuitry.
As to claim 8, the combination of Shepelev, Oh and Ahn teach the light emitting display device of claim 7 (see above rejection), wherein the gamma reference voltage circuit includes: a reference gamma voltage generator receiving the reference voltage and generating a reference gamma voltage; an input voltage generator receiving the reference gamma voltage and generating the input voltage; and a gamma reference voltage generator receiving the reference gamma voltage and generating gamma reference voltages (see Shepelev at least [0042], “a supply voltage (VS) is coupled to the intersection of resistors R1 and R4 … An output voltage (VO) may be measured between the intersection of resistors R1 and R2 and the intersection of resistors R3 and R4”; [0043] “the display controller 220 may be coupled to the intersection of resistors R1 and R2 and the intersection of resistors R3 and R4, via respective leads, to detect the output voltage VO”; [0045] “a supply voltage (VS) may be coupled to the intersection of strain gauges S1 and S4 … An output voltage (VO) may be measured between the intersection of strain gauges S1 and S2 and the intersection of strain gauges S3 and S4”; [0048] “the display controller 220 is configured to receive sensor signals from the strain sensors 214”; [0049] “the sensor signals received from each strain sensor 214 may be representative of its output voltage VO”); and Ahn at least [0034], “The reference voltage generation unit 31 … is configured to divide a voltage difference between power supply voltages Vin1 and Vin2 by the resistors R_r and generate a plurality of gamma reference voltages Vref0 through Vref6”; [0035] “The gamma buffer unit 32 … is configured to stabilize and output the gamma reference voltages Vref0 through Vref6 which are outputted from the reference voltage generation unit 31. Each of the gamma buffers GB1 through GB7 has two output terminals which are connected to the TN gamma voltage generation unit 33A and the IPS gamma voltage generation unit 33B”; [0036] “The TN gamma voltage generation unit 33A and the IPS gamma voltage generation unit 33B are configured to divide the gamma reference voltages Vref0 through Vref6, which are inputted from the gamma buffer unit 32 … and output divided gamma voltages”).
As to claim 9, the combination of Shepelev, Oh and Ahn teach the light emitting display device of claim 8 (see above rejection), wherein the controller provides a selection signal to the gamma reference voltage circuit, and wherein the reference gamma voltage is selectively input to the input voltage generator or the gamma reference voltage generator based on the selection signal (see Ahn at least [0037], “The multiplexer 34 is configured to select and output the gamma voltages … according to a mode select signal IPSEN. The mode select signal IPSEN … can be changed in the logic state thereof depending upon an operation mode”; [0047] “if the mode select signal IPSEN is outputted from the controller (for example, a timing controller) by being enabled to a high level … the first through fourth switches SW1 through SW4 are turned on, and the fifth through eighth switches SW5 through SW8 are turned off. … the gamma reference voltages are outputted to the IPS gamma voltage generation unit 33B”; [0048] “If the mode select signal IPSEN is outputted from the controller by being disabled to a low level … the first through fourth switches SW1 through SW4 are turned off, and the fifth through eighth switches SW5 through SW8 are turned on. … the gamma reference voltages are outputted to the TN gamma voltage generation unit 33A”).
As to claim 11, the combination of Shepelev, Oh and Ahn teach the light emitting display device of claim 9 (see above rejection), wherein the gamma reference voltage circuit includes a first switch for switching connection between the reference gamma voltage generator and the input voltage generator, and a second switch for switching connection between the reference gamma voltage generator and the gamma reference voltage generator, based on the selection signal (see Ahn at least [0041] “the gamma buffers GB1 through GB7 includes … first through fourth switches SW1 through SW4 which are configured to select and operate the IPS gamma reference voltage output section 41; fifth through eighth switches SW5 through SW8 which are configured to select and output the TN gamma reference voltage output section 42”; [0044]–[0045]: electrical connections of SW1–SW8; [0047] “IPSEN is outputted from the controller .. by being enabled to a high level, … the first through fourth switches SW1 through SW4 are turned on, and the fifth through eighth switches SW5 through SW8 are turned off”; [0048] “IPSEN is outputted from the controller by being disabled to a low level, … the first through fourth switches SW1 through SW4 are turned off, and the fifth through eighth switches SW5 through SW8 are turned on”).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shepelev et al. (USPN 2022/0139273 A1) in view of Oh et al. (USPN 2016/0064421 A1), in view of Ahn et al. (USPN 2011/0175942 A1), and further in view of Agarwal et al. (USPN 2016/0092010 A1).
As to claim 10, the combination of Shepelev, Oh and Ahn teach the light emitting display device of claim 9 (see above rejection).
Shepelev, Oh and Ahn do not directly teach wherein in a refresh frame, the reference gamma voltage is input to the gamma reference voltage generator, and wherein at a beginning or end of operation of the light emitting display device, or in a blank section or skip frame, the reference gamma voltage is input to the input voltage generator.
Agarwal teaches wherein in a refresh frame, the reference gamma voltage is input to the gamma reference voltage generator, and wherein at a beginning or end of operation of the light emitting display device, or in a blank section or skip frame, the reference gamma voltage is input to the input voltage generator (see at least [0020] “sensing performance can be improved by performing sensing scans occur during periods of minimal interference between the sensor and display. … Examples of the disclosure can insert one or more full display frames or one or more display sub-frames of extended blanking … and can synchronize the various sensing scans with the display frames or sub-frames”; [0040], “During the intra-frame blanking periods, the display controller can temporarily stop driving display pixels to the display. .. during the vertical blanking period 510 at the end of the first frame, no pixels can be driven to the display”; [0041] “A variable refresh rate can be generated by inserting a period of extended blanking (i.e., no active refresh) between two display frames. .. adding a 60 Hz frame of extended blanking can change the display refresh rate to 30 Hz (i.e., refresh the display once every two frames)”; [0042] “first frame 600 and fourth frame 606 .. can include one or more active refresh periods 608... The third frame rate can be an extended blanking period 614.”; [0043] “The first and second synchronization signals can be used, for example, to synchronize the display blanking periods with scans requiring low noise for improved performance”; [0045] “during an extended blanking period, the touch, stylus and/or force scans can be performed at any time, as no active display refresh operations can be occurring”; [0071] “The system can blank the display for one or more frames or sub-frames between full display frames … At the conclusion of extended display blanking, the display can resume normal display operation”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the display gamma-voltage path of the modified Shepelev/Oh/Ahn device during an active refresh frame and to operate the strain-sensor input-voltage path during Agarwal’s blank or skipped-refresh period, in order to reduce interference between display driving and sensor sensing.
Conclusion
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/JENNIFER L ZUBAJLO/ Examiner, Art Unit 2627 8/20/2026
/KE XIAO/ Supervisory Patent Examiner, Art Unit 2627
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