DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the preliminary amendment dated, February 18, 2026, claims 1-4, 6, 11, 17, 19, 20, 25, 27, 28, 30, 31 and 46-49 are amended and claim(s) 5, 12, 13, 15, 16, 18, 22, 23, 26, 29, 32-45 and 51-69 are canceled. Currently claims 1-4, 6-11, 14, 17, 19-21, 24, 25, 27, 28, 30, 31 and 46-49 are presented for examination and are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 4, 6, 9, 11, 17, 21, 24, 25, and 27 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8, 10, 13, 14, 15 and 18 of U.S. Patent No. 12,518,676. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Current Application
U.S. Patent NO. 12,518,676
Claim 1. A hybrid display, comprising: a plurality of pixel clusters, each comprising: (i) a plurality of pixels; (ii) a pixel memory for storing pixel values for each of the plurality of pixels; and (iii) a cluster controller operable to: (a) control the plurality of pixels to emit light corresponding to the pixel values, (b) receive the pixel values, and (c) store the pixel values in the pixel memory; and a display controller operable to provide the pixel values to the cluster controller for each of the plurality of pixel clusters, wherein, for each of the plurality of pixel clusters, the cluster controller is operable to store one or more of the pixel values in the pixel memory at a same time that the cluster controller controls the plurality of pixels to emit the light using one or more of the pixel values.
Claim 1. A hybrid display, comprising: pixel clusters, each of the pixel clusters comprising (i) pixels; (ii) a pixel memory for storing pixel values for each of the pixels; and (iii) a cluster controller operable to (a) control the pixels to emit light corresponding to the pixel values, (b) receive the pixel values, and (c) store the pixel values in the pixel memory; and a display controller operable to provide the pixel values to the cluster controller for each of the pixel clusters, wherein, for each of the pixel clusters, the cluster controller is operable to store one or more of the pixel values in the pixel memory at a same time that the cluster controller controls the pixels to emit light using one or more of the pixel values,
and wherein the cluster controller is operable to (i) receive an input address of one or more input pixel values, (ii) compare the input address to an output address of a row, the output address being of one or more output pixel values that are used to control the pixels to emit light, and (iii) write the one or more input pixel values into the pixel memory only if the input address does not match the output address. wherein the second signal line, the third signal line and the fourth signal line overlap the pixel circuit of the first display sub-region in a thickness direction of the display panel.
Claim 3. The hybrid display of claim 1, wherein, for each of the plurality of pixel clusters, the cluster controller controls the plurality of pixels to emit light using pulse-width modulation control.
Claim 2. The hybrid display of claim 1, wherein, for each of the pixel clusters, the cluster controller controls the pixels to emit light using pulse-width modulation control.
Claim 4. The hybrid display of claim 3, wherein wherein it takes a first amount of time to write a pixel value into the pixel memory and a second amount of time to emit a shortest pulse of the pulse-width modulation control, wherein either: (i) the first amount of time is less than the second amount of time, or
(ii) the first amount of time is equal to or greater than the second amount of time.
Claim 3. The hybrid display of claim 1, wherein, for each of the pixel clusters, the cluster controller controls the pixels to emit light using pulse-width modulation control.
Claim 4. The hybrid display of claim 2, wherein an amount of time to write a pixel value into the pixel memory is equal to or greater than an amount of time of a shortest pulse of the pulse-width modulation control.
Claim 6. The hybrid display of claim 1, wherein, for each of the plurality of pixel clusters: each of the plurality of pixels comprises C light emitters; each of the pixel values comprises C luminance values, each corresponding to one of the C light emitters; each of the luminance values has D bits; the plurality of pixels are disposed in an array of M rows and N columns; wherein C, D, M, and N are positive integers, M is no less than two, N is no less than one, and C is no less than one; and the pixel memory has (i) a storage for pixel values of at least M×N×C×D bits and (ii) at least M row addresses.
Claim 5. The hybrid display of claim 1, wherein, for each of the pixel clusters: each of the pixels comprises C light emitters; each of the pixel values comprises C luminance values, each corresponding to one of the C light emitters; each of the luminance values has D bits; the pixels are disposed in an array of M rows and N columns; M is no less than two, N is no less than one, and C is no less than one; and the pixel memory has (i) a storage for pixel values of at least M×N×C×D bits and (ii) at least M row addresses.
Claim 9. The hybrid display of claim 6, wherein pixel data stored at any row address of the pixel memory can be accessed independently of pixel data stored at any other row address of the pixel memory so that pixel data can be read at any row address of the pixel memory at a same time that pixel data can be written to any row address of the pixel memory.
Claim 6. The hybrid display of claim 5, wherein pixel data stored at any row address of the pixel memory can be accessed independently of pixel data stored at any other row address of the pixel memory so that pixel data can be read at any row address of the pixel memory at a same time that pixel data can be written to any row address of the pixel memory.
Claim 11. The hybrid display of claim 6, wherein the cluster controller is operable to read output pixel data stored at row address I-OUTPUT of the pixel memory and control each of the pixels corresponding to row address I-OUTPUT to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at one or more row addresses I-INPUT of the pixel memory.
Claim 7. The hybrid display of claim 5, wherein the cluster controller is operable to read output pixel data stored at row address I-OUTPUT of the pixel memory and control each of the pixels corresponding to row address I-OUTPUT to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at row address I-INPUT of the pixel memory.
Claim 17. The hybrid display of claim 11, wherein I-INPUT≠ I-OUTPUT.
Claim 8. The hybrid display of claim 7, wherein I-OUTPUT does not equal I-INPUT.
Claim 21. The hybrid display of claim 6, wherein the cluster controller is operable to read output pixel data stored at row address I-OUTPUT of the pixel memory and copy the pixel data into the pixel memory at row address I-OUTPUT2, where I-OUTPUT≠ I-OUTPUT2.
Claim 10. The hybrid display of claim 5, wherein the cluster controller is operable to read output pixel data stored at row address I-OUTPUT of the pixel memory and copy the pixel data into the pixel memory at row address I-OUTPUT2, where I-OUTPUT≠ I-OUTPUT2
Claim 25. The hybrid display of claim 1, wherein, for each of the plurality of pixel clusters, the cluster controller is operable to receive rows of pixel values at an input rate and output rows of pixel values to display information at an output rate, wherein either: the input rate is greater than the output rate,
or the input rate is less than or equal to the output rate.
Claim 13. The hybrid display of claim 1, wherein, for each of the pixel clusters, the cluster controller is operable to receive rows of pixel values at an input rate and output rows of pixel values to display information at an output rate and the input rate is greater than the output rate.
Claim 14. The hybrid display of claim 1, wherein, for each of the pixel clusters, the cluster controller is operable to receive rows of pixel values at an input rate and output rows of pixel values to display information at an output rate and the input rate is less than or equal to the output rate.
Claim 27. The hybrid display of claim 1, wherein, for each of the plurality of pixel clusters, the cluster controller is operable to sequentially output single bits of each pixel value in a row of pixel values from the pixel memory and control the plurality of pixels to emit the light corresponding to the single bits.
Claim 15. The hybrid display of claim 1, wherein, for each of the pixel clusters, the cluster controller is operable to sequentially output single bits of each pixel value in a row of pixel values from the pixel memory and control the pixels to emit light corresponding to the single bits.
Claim 24. The hybrid display of claim 6, wherein:
the pixel memory storage is (M+1)×N×C×D bits in size and the pixel memory has row addresses having a range at least from zero to M, and the cluster controller is operable to read output pixel data stored at row address I-OUTPUT of the pixel memory (I-OUTPUT<(M+1)) and control the pixels corresponding to row address I-OUTPUT to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at one or more row addresses I-INPUT of the pixel memory, where I-INPUT≠I-OUTPUT and I-INPUT<(M+1).
Claim 18. A hybrid display, comprising: pixel clusters, each of the pixel clusters comprising (i) pixels; (ii) a pixel memory for storing pixel values for each of the pixels; and (iii) a cluster controller operable to (a) control the pixels to emit light corresponding to the pixel values, (b) receive the pixel values, and (c) store the pixel values in the pixel memory; and a display controller operable to provide the pixel values to the cluster controller for each of the pixel clusters, wherein, for each of the pixel clusters, the cluster controller is operable to store one or more of the pixel values in the pixel memory at a same time that the cluster controller controls the pixels to emit light using one or more of the pixel values, wherein, for each of the pixel clusters: each of the pixels comprises C light emitters; each of the pixel values comprises C luminance values, each corresponding to one of the C light emitters; each of the luminance values has D bits; the pixels are disposed in an array of M rows and N columns; M is no less than two, N is no less than one, and C is no less than one; and the pixel memory has (i)
a storage for pixel values of at least M×N×C×D bits and (ii) at least M row addresses, and wherein: the pixel memory storage is (M+1)×N×C×D bits in size and the pixel memory has row addresses having a range at least from zero to M, and the cluster controller is operable to read output pixel data stored at row address I-OUTPUT of the pixel memory (I-OUTPUT<(M+1)) and control the pixels corresponding to row address I-OUTPUT to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at one or more row addresses I-INPUT of the pixel memory, where I-INPUT≠I-OUTPUT and I-INPUT<(M+1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-9,6, 9, 11-13, 17, 21-23 and is/are rejected under 35 U.S.C. 103 as being unpatentable over Cok et al (PG Pub NO 2010/0123694) in view of Rotzoll et al (PG Pub NO 2018/0197471) .
As in claim 1; Cok et al discloses a hybrid display (Abstract), comprising:
a plurality of pixel clusters (Fig 1 item 32), each comprising
(i) a plurality of pixels (Fig 1 item 30);
(ii) a pixel memory for storing pixel values for each of the plurality of pixels (Fig 1, 2 item 70 and Par 0021) discloses storage element 70 storing a value representing a desired luminance for a pixel;
and (iii) a cluster controller (Fig 1 item 20) operable to;(a) control the plurality of pixels to emit light corresponding to the pixel values,(b) receive the pixel values, and (c) store the pixel values in the pixel memory; [0021] Referring to FIG. 2, each chiplet 20 has connections to each of the associated group row electrodes 40 and associated group column electrodes 42 and has a storage element 70 for at least as many pixels as are in either dimension of the pixel group 32, the storage element 70 storing a value representing a desired luminance for a pixel and the chiplet 20 using such value to control the desired luminance of each pixel 30 in its associated group 32.
(Par 0027 and Fig 1) discloses control chiplets (50) used to control the imaging device 5. But fails to explicitly disclose and a display controller operable to provide the pixel values to the cluster controller for each of the plurality of pixel clusters, wherein, for each of the plurality of pixel clusters, the cluster controller is operable to store one or more of the pixel values in the pixel memory at a same time that the cluster controller controls the plurality of pixels to emit the light using one or more of the pixel values. However, Rotzoll et al (Fig 1 items 70, 72) discloses display controller and [Par 0033] In some implementations, controllers provided in an improved display utilizing in-pixel memory to dictate individual pixel values and when these values should change (based on writes to these memory elements) may be comparatively simplified relative to traditional timing controllers and scaler controllers in conventional displays. For instance, a remote frame buffer (RFB) may be omitted from controller logic of the improved display (e.g., with in -pixel memory replacing the traditional frame buffer and RFB, etc.). Pixel-wise addressing may be performed, resulting in only a subset (and in some cases a very small subset) of in-pixel memory being signaled based on those pixels changing state. In some cases, the computing platform (e.g., SoC) generating the display data may be adapted to operate efficiently with such display architectures, sending display data that identifies (e.g., by coordinates) those pixels which are to have their respective in-pixel memory element overwritten to reflect the new, updated pixel value, among other example implementations. Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Cok et al display device with the teaching of Rotzoll et al display device having a well-known display controller used to drive said display device to yield same predictable outcome (i.e. drive display via display controller).
As in claim 2; Cok et al in view of Rotzoll et al discloses the hybrid display of claim 1, wherein, for each of the plurality of pixel clusters (Fig 1 item 32), the plurality of pixels in the pixel cluster are controlled by the cluster controller with passive-matrix control. Cok et al (Par 0018) discloses hybrid drive, as disclosed herein, is a means for controlling the luminance of an array of light-emitting elements that combines attributes of both passive-matrix and active-matrix control. Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to control pixel cluster via passive-matrix control to yield same predictable result.
As in claim 3; Cok et al in view of Rotzoll et al discloses the hybrid display of claim 1, wherein, for each of the plurality of pixel clusters (Fig 1 item 32), the cluster controller (fig 1 item 20 and Fig 1 item 40) controls the plurality of pixels to emit light using pulse-width modulation control. (Rotzoll et al, Par 0003, 0009) discloses display systems using digital pixel values driven by pulse-width modulation.
As in claim 4; Cok et al in view of Rotzoll et al discloses the hybrid display of claim 3, wherein it takes a first amount of time to write a pixel value into the pixel memory and a second amount of time [[of]] to emit a shortest pulse of the pulse-width modulation control, wherein either:(i) the first amount of time is less than the second amount of time, or (ii) the first amount of time is equal to or greater than the second amount of time. (Rotzoll et al, Par 0003, 0009) discloses display systems using digital pixel values driven by pulse-width modulation. Therefore it would have been obvious design choice to an ordinary skill person in the art to have write a pixel value into the pixel memory is no greater than an amount of time of a shortest pulse of the pulse-width modulation control
As in claim 6; Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 1, wherein, for each of the plurality of pixel clusters:
each of the plurality of pixels comprises C light emitters; (Cok et al, Fig 1 pixel group 32) discloses light emitters (30) and Rotzoll et al (Fig 1 item 22)
each of the pixel values comprises C luminance values, each corresponding to one of the C light emitters; (Par 0021) discloses light emitters having luminance values/levels and Rotzoll et al (Par 0007)
each of the luminance values has D bits; (Cok et al, Par 0029) The processed signal includes luminance information for each light-emitting pixel element in the pixel group corresponding to the chiplet. Chiplet controller stores the luminance information in a storage element corresponding to each light-emitting pixel element
the plurality of pixels are disposed in an array of M rows and N columns; wherein C, D, M, and N are positive integers, M is no less than two, N is no less than one, and C is no less than one; (Cok et al, Fig 1) discloses pixels disposed in an array of M rows and N columns; and Rotzoll et al (Fig 1-4) discloses plurality of pixels disposed in an array having rows, columns light emitters having luminance values with rows and columns no less than two.
and the pixel memory has (i) a storage for pixel values of at least M x N x C x D bits and (ii) at least M row addresses. (Cok et al, Par 0029) discloses Chiplet controller stores the luminance information in a storage element corresponding to each light-emitting pixel element. The controller then drives the luminance information from each storage element corresponding to pixels in a row through connection pads and group column electrodes to the light-emitting pixel elements in that row. Simultaneously a group row electrode is provided with power so that each light-emitting pixel element in the row simultaneously emits light according to the luminance information stored in the corresponding storage element. All of the chiplets can drive a row of its corresponding pixel group simultaneously. Subsequently, a second row in the pixel group can be driven, followed sequentially by other remaining rows of light-emitting pixel elements in the pixel group. Note that, in the present application, the designation of "rows" and "columns" is arbitrary and can be exchanged. And Rotzoll et al (Fig 2-3)
As in claim 7; the hybrid display of claim 6, wherein the pixel memory has M x D row addresses and each row address accesses C x N bits, each bit corresponding to a bit of a luminance value. (Cok et al, Par 0029) The processed signal includes luminance information for each light-emitting pixel element in the pixel group corresponding to the chiplet. Chiplet controller stores the luminance information in a storage element corresponding to each light-emitting pixel elements. The controller then drives the luminance information from each storage element corresponding to pixels in a row through connection pads and group column electrodes to the light-emitting pixel elements in that row. And Rotzoll et al (Fig 2-3 and Par 0070) discloses digital-drive display system 10 includes an array of pixels 20 arranged in rows and columns. Each pixel 20 has digital memory 24 responsive to a load timing signal for receiving and storing a multi-bit digital pixel value
As in claim 8; the hybrid display of claim 6, wherein the pixel memory has M row addresses and each row address accesses N pixel values equivalent to C x N luminance values and C x N x D bits. (Cok et al, Par 0029) The processed signal includes luminance information for each light-emitting pixel element in the pixel group corresponding to the chiplet. Chiplet controller stores the luminance information in a storage element corresponding to each light-emitting pixel element. And Rotzoll et al (Fig 2-3 and Par 0070) discloses digital-drive display system includes an array of pixels arranged in rows and columns. Each pixel has digital memory for receiving and storing a multi-bit digital pixel value in accordance with each pixel address and its value.
As in claim 9, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 6, wherein pixel data stored at any row address of the pixel memory can be accessed independently of pixel data stored at any other row address of the pixel memory so that pixel data can be read at any row address of the pixel memory at a same time that pixel data can be written to any row address of the pixel memory.
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As in claim 10, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 6, wherein the pixel memory storage is no greater than a storage of N x M pixel values. Obvious to an ordinary skill person in the art and Cok et al (Fig 2) discloses storage element 70 for at least as many pixels as are in either dimension of the pixel group 32. And Rotzoll et al (fig 1-3) discloses pixel memory storage is no greater than a storage of N x M pixel
As in claim 11, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 6, wherein the cluster controller is operable to read output pixel data stored at row address I-output of the pixel memory and control each of the pixels corresponding to row address I-output to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at one or more row address addresses I-input of the pixel memory. (Cok et al, Fig 1-2 and Par 0021) discloses group row electrodes 40 and associated group column electrodes 42 and has a storage element 70 for at least as many pixels as are in either dimension of the pixel group 32, the storage element 70 storing a value representing a desired luminance for a pixel and the chiplet 20 using such value to control the desired luminance of each pixel 30 in its associated group 32. A chiplet interconnection buss 52 can be employed to communicate signals to the chiplets 20 and a chiplet controller 72 can control the interconnection buss 52, storage elements 70, and the corresponding light-emitting elements through group row and group column electrodes 40, 42. [0022] the pixel group 32 has two rows and two columns so that the chiplet 20 must have at least two storage elements 70. Information, for example image information, is deposited in the storage elements 70 corresponding to the pixel 30 for the row (or column) that is to be activated. At least one row (or column) of information can be deposited and displayed in one communication step. In other words each pixel cluster are addressed separately from pixel memory control each of the pixels corresponding to row address to emit light (output) and controller stores input pixel data at row address of the pixel memory (input). And Rotzoll et al (Par 0096) The array of display pixels 20 can be controlled through the row-select lines 60 and column-data lines 62 by a display controller 30. The display controller 30 can be one or more integrated circuits and can, for example, include an image frame store, digital logic, input and output data signal circuits, and input and output control signal circuits such as loading circuits 32, control circuits 34, and provide load timing signals, PWM timing signals, and column-data signals. Other control signals can also be provided. The loading circuit 32 can provide sequential rows of digital pixel values to corresponding selected rows of display pixels 20. The display controller 30 can include an image frame store memory for storing digital pixel and calibration values. The display controller 30 can have a display controller substrate 36 separate and distinct from the display substrate 50 that is mounted on the display substrate 50 or is separate from the display substrate 50 and connected to it by wires, for example with ribbon cables, flex connectors, or the like.
As in claim 14, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 11, wherein the pixel memory has M row addresses and I-output < M and I-input < M. An Obvious design choice to an ordinary skill person in the art to have pixel memory row addresses be more than I-output and I-output in order to reduce size and cost of components.
As in claim 17, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 11, wherein I-input ≠ I-output. Obvious design choice to an ordinary skill person in the art to have output pixel data not equal to input pixel data.
As in claim 19, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 11, wherein the one or more row addresses I-output are two or more row addresses. Obvious design choice
As in claim 20, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 11, wherein the pixel memory has M row addresses and the one or more row addresses I-input are (M-1) row addresses. Obvious design choice
As in claim 21; the hybrid display of claim 6, wherein the cluster controller is operable to read output pixel data stored at row address I-output of the pixel memory and copy the pixel data into the pixel memory at row address I-output 2, where I-output ≠ I-output 2. Obvious to an ordinary skill person in the art to have output pixel data not equal to input pixel data and Rotzoll et al (Par 0077-0078) discloses pixel value during the load time period and output time period
As in claim 25, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 1, wherein, for each of the plurality of pixel clusters, the cluster controller is operable to receive rows of pixel values at an input rate and output rows of pixel values to display information at an output rate, wherein either: the input rate is greater than the output rate, or the input rate is less than or equal to the output rate. Rotzoll et al [0099] pixel controller 40 decodes the load signal together with sequentially provided multi-bit data on the column-data line 62 to load the multi-bit digital pixel value into the multi-bit serial digital memory 24. The PWM timing signal then provides the timing necessary for the pixel controller 40 to output light from the light emitters 22 and Claim 24 discloses he pixel controller is responsive to the load timing signal and the multi-bit digital pixel value during the load time period and the PWM timing signal during the output time period. Therefore, said controller has an output rate and input rate, therefore it would have been obvious design choice to have input rate is greater than the output rate. Write
As in claim 27, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 1, wherein, for each of the plurality of pixel clusters, the cluster controller is operable to sequentially output single bits of each pixel value in a row of pixel values from the pixel memory and control the plurality of pixels to emit the light corresponding to the single bits. Rotzoll et al [0077] digital memory 24 can be a three-bit memory with eight addressable locations. One bit is provided for each color of output device 22. The state machine sequentially generates the addresses for the RAM corresponding to the bits provided on the column-data line 62 to store the multi-bit digital pixel value during the load time period.
As in claim 28, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 1, wherein, for each of the plurality of pixel clusters, the cluster controller is operable to write a pixel value into the pixel memory between or during output of single bits in a pixel value. Rotzoll et al [Fig 7 and Par 0089-0090]
As in claim 30, Cok et al in view of Rotzoll et al discloses the hybrid display (Abstract) of claim 1, wherein the cluster controller is operable to input a pixel value into the pixel memory in a blanking interval after controlling the plurality of pixels to emit light corresponding or to emit light corresponding to an entire pixel value. Rotzoll et al [0085] Once the multi-bit digital pixel value is loaded into the multi-bit serial digital memory 24 of each pixel 20 in the row, the PWM timing signal is provided on the row-select line 60, enabling the pixels 20 in the row to output from the output devices 22 in the pixels 20. At the same time, a different row of pixels 20 can be addressed by the row controller 70 to load the multi-bit digital pixel values into the corresponding multi-bit serial digital memories 24 of the different row of pixels 20. Thus, one row of pixels 20 is loaded while the other rows of pixels 20 output light corresponding to the stored multi-bit digital pixel values and at least two of the separate timing signals can be provided to different rows of pixels 20 at different times. Thus, the rows of pixels 20 can operate asynchronously, independently, or out-of-phase with each other. [0089] The output time period can include multiple PWM timing signals so that the multi-bit digital pixel value is output multiple times (in this case two times) for each frame.
As in claim 46, Cok et al discloses a method of controlling a hybrid display comprising a plurality of pixel clusters (Fig 1 item 32), each comprising
a plurality of pixels, (Fig 1 item 30)
(ii) a pixel memory for storing digital pixel values for the plurality of pixels, (Fig 1, 2 item 70 and Par 0021) discloses storage element 70 storing a value representing a desired luminance for a pixel
and (iii) a cluster controller (Fig 1 item 20), the method comprising: receiving one or more first digital pixel values at the cluster controller; storing the one or more first digital pixel values in the pixel memory; ; [0021] Referring to FIG. 2, each chiplet 20 has connections to each of the associated group row electrodes 40 and associated group column electrodes 42 and has a storage element 70 for at least as many pixels as are in either dimension of the pixel group 32, the storage element 70 storing a value representing a desired luminance for a pixel and the chiplet 20 using such value to control the desired luminance of each pixel 30 in its associated group 32.
(Par 0027 and Fig 1) discloses control chiplets (50) used to control the imaging device 5. But fails to explicitly disclose emitting light from the plurality of pixels using one or more second digital pixel values while the one or more first pixel values are being stored. However, Rotzoll et al (Fig 1 items 70, 72) discloses display controller and [Par 0033] In some implementations, controllers provided in an improved display utilizing in-pixel memory to dictate individual pixel values and when these values should change (based on writes to these memory elements) may be comparatively simplified relative to traditional timing controllers and scaler controllers in conventional displays. For instance, a remote frame buffer (RFB) may be omitted from controller logic of the improved display (e.g., with in -pixel memory replacing the traditional frame buffer and RFB, etc.). Pixel-wise addressing may be performed, resulting in only a subset (and in some cases a very small subset) of in-pixel memory being signaled based on those pixels changing state. In some cases, the computing platform (e.g., SoC) generating the display data may be adapted to operate efficiently with such display architectures, sending display data that identifies (e.g., by coordinates) those pixels which are to have their respective in-pixel memory element overwritten to reflect the new, updated pixel value, among other example implementations. Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Cok et al display device with the teaching of Rotzoll et al display device having a well-known display controller used to drive said display device to yield same predictable outcome (i.e. drive display via display controller).
As in claim 49; Cok et al in view of Rotzoll et al discloses the method of claim 46, comprising: reading pixel data from a row address of the pixel memory; and simultaneously writing pixel data to any row address of the pixel memory. (Cok et al, Par 0029) The controller then drives the luminance information from each storage element corresponding to pixels in a row through connection pads and group column electrodes to the light-emitting pixel elements in that row. Simultaneously a group row electrode is provided with power so that each light-emitting pixel element in the row simultaneously emits light according to the luminance information stored in the corresponding storage element. All of the chiplets can drive a row of its corresponding pixel group simultaneously. Subsequently, a second row in the pixel group can be driven, followed sequentially by other remaining rows of light-emitting pixel elements in the pixel group. [0011] the pixels associated into a plurality of pixel groups, each pixel group including at least four pixels and including a separate set of group row electrodes and group column electrodes connected to and driving only the pixels in the corresponding group, each of the group row electrodes connected to two or more pixels and each of the group column electrodes connected to two-or-more pixels, so that a single group row electrode together with a single group column electrode drives a single pixel;
Allowable Subject Matter
Claim(s) 24, 31, 47 and 48 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 24 prior art of record singularly or in combination thereon fails to disclose the pixel memory storage is (M+1) x N x C x D bits in size and the pixel memory has row addresses having a range at least from zero to M, and the cluster controller is operable to read output pixel data stored at row address I-output of the pixel memory (I-output < (M+1)) and control the pixels corresponding to row address I-output to emit light corresponding to the output pixel data at a same time that the cluster controller stores input pixel data at one or more row addresses I-input of the pixel memory, where I-input ≠ I-output and I-input < (M+1)as recited in claim 24.
Conclusion
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/BENYAM KETEMA/Primary Examiner, Art Unit 2626
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