Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
SUMMARY
2. The patent application amendment for reconsideration after Non-Final Office Action filed on September 21, 2026, has been received and recorded. In response to the Non-Final Rejection mailed on July 01, 2026, Applicant amended claims 1, 6, 10-12, 17, and 20 of which claims 1 and 20 are independent claims. Claims 2-5, 7-8, 13-17 and 18-19 are maintained. Applicant cancelled claims 9. NO claim has been added as new claim after the Non-Final Office Action. Therefore, claims 1-8, and 10-20 have been pending for consideration.
Response to Arguments
3. Applicant's arguments in "REMARKS" filed on September 21, 2026, with respect to independent claims 1, and 20 have been considered but are moot in view of new ground of rejection as necessitated by the applicant's amendment. In the Non-Final Office Action, claim 9 was objected and it was depended on claim 6. Applicant incorporated limitations partially from claim 6 and added the limitations from claim 9 with adding “OR” logic instead of logic “AND”. Therefore, amendment changes the scope of the claim and it is a new ground of rejection.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
7. Claims 1-3, 11, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over TANAKA et al.(US 2018/0108309 A1)(herein after TANAKA) in view of Zheng et al.(US 2021/0217339 A1)(herein after Zheng).
Regarding claim 1, TANAKA teaches a display panel(shift register circuit and display device), comprising a substrate (active matrix substrate 20a, figs.1-3, Para-75, 78) and a display region(display region 201, fig.3, Para-78), wherein
the display region(201) comprises a plurality of shift register circuit groups(gate drivers 11A, 11B, fig.3, Para-78), a shift register circuit group(11a, 11B) of the plurality of shift register circuit groups comprises a plurality of shift register units(plurality of driving circuits 11) disposed sequentially in a first direction(vertical direction), the plurality of shift register circuit groups are arranged in a second direction(horizontal direction), the first direction and the second direction intersect(figs.2-3), a shift register circuit group of the plurality of shift register circuit groups is configured to output a first scan signal(Para-79: The driving circuit 11 outputs a voltage signal that indicates either a selected state or a non-selected state to the gate lines 13G connected therewith, according to the supplied signal), the plurality of shift register circuit groups(11a, 11B) at least comprises a first shift register circuit group(11A) and a second shift register circuit group(11B), and the first shift register circuit group(11A) and the second shift register circuit group(11B) are respectively connected to first scan signal lines of different rows(13G(1), 13G(2), 13G(3), ----, 13G(M), fig.3); and
the display region(201, fig.1) further comprises a plurality of signal lines extending in the first direction(lines 15L, fig.3, Para-78), the plurality of signal lines comprises a plurality of signal line groups(figs.3, 6A-6D), a signal line group of the plurality of signal line groups is electrically connected to a respective shift register circuit group of the plurality of shift register circuit groups(figs.3, 6A-6D), and different signal line groups among the plurality of signal line groups are electrically connected to different shift register circuit groups among the plurality of shift register circuit groups(figs.3, 6A-6D)(all components in an electrical circuit and/or device are electrically connected to each other, otherwise the circuit and/or device would be non-functional);
PNG
media_image1.png
549
501
media_image1.png
Greyscale
Fig.3
wherein the plurality of shift register units(11) in the first shift register circuit group(11A) are first shift register units(11), the plurality of shift register units in the second shift register circuit group(11B) are second shift register units(11), the first shift register circuit group further comprises at least one first auxiliary shift register unit (fig.3)(any one of a middle driving circuit 11 between two driving circuits 11 in 11A is regarded as first auxiliary circuit, since no different criteria is defined in the claim), and the second shift register circuit group(11B) further comprises at least one second auxiliary shift register unit(fig.3)(any one of a middle driving circuit 11 between two driving circuits 11 in 11B is regarded as second auxiliary circuit, since no different criteria is defined in the claim);
in the first direction(vertical direction), two adjacent first shift register units(11) are connected in cascade through at least one first auxiliary shift register unit(one of 11 in the middle in 11A, fig.3); or
in the first direction, two adjacent second shift register units are connected in cascade through at least one second auxiliary shift register unit(one of 11 in the middle in 11B, fig.3)(optionally considered as the limitations are connected through “OR” logic);
If it is considered that TANAKA is not found to teach expressly all the limitations, especially the limitations, “in the first direction, two adjacent first shift register units are connected in cascade through at least one first auxiliary shift register unit” in his/her disclosure, then it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to use the teaching of Zheng related to figs.11-13 and related texts in TANAKA’s teaching in order to get claim limitations.
PNG
media_image2.png
619
470
media_image2.png
Greyscale
Zheng teaches gate driving circuits in a display device, where plurality of individual gate driving unit are connected by auxiliary control circuit 52. Such a combination is desirable as it provides a display panel in a foldable display device capable of improving display split screen phenomenon.
Regarding claim 2, TANAKA as modified by Zheng teaches the display panel of claim 1, wherein the plurality of signal line groups are disposed in one-to-one correspondence with the plurality of shift register circuit groups(fig.3, TANAKA; figs.5-12, Zheng).
Regarding claim 3, TANAKA as modified by Zheng teaches the display panel of claim 2, wherein the display region comprises M shift register circuit groups(11A, 11B), wherein M is an integer greater than 1(two groups, figs.3, TANAKA); and
the plurality of signal lines comprises N first signal lines, and the N first signal lines are divided into M signal line groups, wherein N>M, and N is an integer(figs.5-12, Zheng).
Regarding claim 11, TANAKA as modified by Zheng teaches the display panel of claim 1, wherein in the first direction, among the plurality of pixel circuit rows, a shift register unit connected to an i-th pixel circuit row is the first shift register unit(fig.3, TANAKA), and a shift register unit connected to an (i+1)-th pixel circuit row is connected the second shift register unit(fig.3, TANAKA)(as seen from figure, first driving circuit is connected to odd number of rows and second driving circuit connected to even number of rows), wherein i is an integer greater than zero; and
in the first direction, two adjacent first shift register units are connected in cascade through the first auxiliary shift register unit(fig.11-13, Zheng); and
in the first direction, two adjacent second shift register units are connected in cascade through the second auxiliary shift register unit(fig.11-13, Zheng)(TANAKA teaches two groups of gate driving circuits and Zheng teaches auxiliary driving circuit, therefore, it is obvious to one of ordinary skill in the art could use the concept of Zheng to include second auxiliary driving circuit between two adjacent second shift register).
Claim 20 is rejected for the same reason as mentioned in the rejection of claim 1 since both claims 1 and 20 recite identical claim limitations except claim presentation in different formats.
8. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over TANAKA et al.(US 2018/0108309 A1) in view of Zheng et al.(US 2021/0217339 A1) and further in view of JEONG et al.(US 2020/0159 054 A1) (herein after JEONG).
Regarding claim 4, TANAKA as modified by Zheng teaches the display panel of claim 3, wherein the display region further comprises a plurality of pixel circuits, and the plurality of pixel circuits are arranged in the first direction to form a plurality of pixel circuit columns sequentially arranged in the second direction(figs.6A-6C, TANAKA) but fails to teach expressly a shift register circuit group of the plurality of shift register circuit groups is disposed in a first spacing region between two adjacent pixel circuit columns among the plurality of pixel circuit columns.
However, JEONG teaches a display device, wherein the display region further comprises a plurality of pixel circuits, and the plurality of pixel circuits are arranged in the first direction to form a plurality of pixel circuit columns sequentially arranged in the second direction(pixels PX, figs.1-3); and
a shift register circuit group of the plurality of shift register circuit groups(STA1-STA4, STB1-STB4, STC1-STC4, fig.9) is disposed in a first spacing region between two adjacent pixel circuit columns among the plurality of pixel circuit columns(figs.3, 9 and related texts).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified TANAKA further with the teaching of JEONG to include the feature in order to minimize a dead space outside a display area.
9. Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over TANAKA et al.(US 2018/0108309 A1) in view of Zheng et al.(US 2021/0217339 A1) and further in view of SHIN et al.(US 2022/0302175 A1)(herein after SHIN).
Regarding claim 5, TANAKA as modified by Zheng is not found to teach expressly the display panel of claim 3, wherein the N first signal lines comprise a first signal line group and a second signal line group; and the first signal line group comprises R first signal lines, the second signal line group comprises (N−R) first signal lines, the first signal line group is electrically connected to the first shift register circuit group, and the second signal line group is electrically connected to the second shift register circuit group, wherein N>R, and R is an integer.
However, SHIN teaches a tiled display device, wherein the N first signal lines comprise a first signal line group(STRL1, CKL1-CKL4, fig.5) and a second signal line group(CBL1-CBL4, fig.5, Para-149); and
the first signal line group comprises R first signal lines (5 signal lines, fig.5), the second signal line group comprises (N−R) first signal lines(4 signal lines CBL1-CBL4, fig.5), the first signal line group is electrically connected to the first shift register circuit group, and the second signal line group is electrically connected to the second shift register circuit group(fig.5), wherein N>R, and R is an integer(5>4)(all components in electrical circuit are connected to each other electrically, otherwise the electrical circuit would be non-functional).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified TANAKA further with the teaching of SHIN to include the feature in order to provide a display device and a tiled display device capable of displaying images that appear seamless.
Regarding claim 6, TANAKA as modified by Zheng and SHIN teaches the display panel of claim 5, wherein
the display region further comprises a plurality of pixel circuits(figs.6A-6D, TANAKA), and the plurality of pixel circuits are arranged in the second direction to form a plurality of pixel circuit rows sequentially arranged in the first direction(figs.6A-6D, TANAKA);
the plurality of pixel circuit rows are electrically connected to the plurality of shift register units(fig.3, TANAKA); and
the shift register unit is disposed in a second spacing region between two adjacent pixel circuit rows among the plurality of pixel circuit rows(fig.4, SHIN).
Regarding claim 7, TANAKA as modified by Zheng and SHIN teaches the display panel of claim 6, wherein in the first direction, among the plurality of pixel circuit rows, a shift register unit between an i-th pixel circuit row and an (i+1)-th pixel circuit row is electrically connected to a shift register unit between the (i+1)-th pixel circuit row(fig.5, SHIN) and an (i+2)-th pixel circuit row through a first cascade wire, wherein i is a positive integer, i≤P−2, and P is a total number of the plurality of pixel circuit rows(fig.5, SHIN).
Regarding claim 8, TANAKA as modified by Zheng and SHIN’175 teaches the display panel of claim 7, wherein the first cascade wire and the (i+1)-th pixel circuit row overlap in a direction perpendicular to the substrate(fig.3, TANAKA); or
the first cascade wire comprises a first branch portion extending in the first direction, a second branch portion extending in the second direction, and a third branch portion extending in the first direction, and the first branch portion, the second branch portion and the third branch portion are electrically connected in sequence; and the first cascade wire and the plurality of pixel circuits do not overlap in a direction perpendicular to the substrate.
10. Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over TANAKA et al.(US 2018/0108309 A1) in view of Zheng et al.(US 2021/0217339 A1) and further in view of LEE et al. (US 2017/0193893 A1)(herein after LEE).
Regarding claim 12, TANAKA as modified by Zheng teaches the display panel of claim 1, wherein the first shift register unit(11, 11A, fig.3, TANAKA), the first auxiliary shift register unit(fig.3, TANAKA), the second shift register unit (11, 11B, fig.3, TANAKA) and the second auxiliary shift register (fig.3, TANAKA) unit each comprise a cascade output terminal (fig.3, TANAKA; figs.11-13, Zheng); but fails to teach expressly at least one of the following is satisfied: in the second direction, among the plurality of pixel circuit rows, cascade output terminals of the first shift register unit and the second auxiliary shift register unit located between a t-th pixel circuit row and a (t+1)-th pixel circuit row are electrically connected through a first horizontal wire; or in the second direction, among the plurality of pixel circuit rows, cascade output terminals of the first auxiliary shift register unit and the second shift register unit located between a (t+1)-th pixel circuit row and a (t+2)-th pixel circuit row are electrically connected through a second horizontal wire.
However, LEE teaches a display device, at least one of the following is satisfied:
in the second direction, among the plurality of pixel circuit rows(fig.3), cascade output terminals of the first shift register unit and the second auxiliary shift register unit located between a t-th pixel circuit row and a (t+1)-th pixel circuit row are electrically connected through a first horizontal wire(fig.4, Para 57-61); or
in the second direction, among the plurality of pixel circuit rows, cascade output terminals of the first auxiliary shift register unit and the second shift register unit located between a (t+1)-th pixel circuit row and a (t+2)-th pixel circuit row are electrically connected through a second horizontal wire.
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified TANAKA further with the teaching of LEE to include the feature in order to prevent aperture ratio from being lowered by the GIP circuit as the transistor for the GIP circuit is arranged in the area corresponding to the boundaries between the pixels, the area in which the data line is not formed.
Regarding claim 14, TANAKA as modified by Zheng and LEE teaches the display panel of claim 12, wherein at least one of the following is satisfied:
in the second direction, at least part of signal lines electrically connected to the first shift register circuit group are disposed between the first shift register circuit group and the second shift register circuit group(figs.3-4, LEE); or
in the second direction, at least part of signal lines electrically connected to the second shift register circuit group are disposed between the first shift register circuit group and the second shift register circuit group.
11. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over TANAKA et al.(US 2018/0108309 A1), Zheng et al.(US 2021/0217 339 A1), LEE et al.(US 2017/0193893 A1) and further in view of CHENG et al.(US 2017/0316730 A1)(herein after CHENG).
Regarding claim 13, TANAKA as modified by Zheng and LEE is not found to teach the display panel of claim 12, wherein in the second direction, signal lines electrically connected to the first shift register circuit group are located on a side of the first shift register circuit group facing away from the second shift register circuit group; and in the second direction, signal lines electrically connected to the second shift register circuit group are located on a side of the second shift register circuit group facing away from the first shift register circuit group(though it is obvious to one of ordinary skill in the art left side gate driver group signal lines would be in left hand side and right side gate driver group signal lines would be right side of the display panel, examiner broad new prior art to prove the obviousness of the claim limitations).
However, CHENG teaches display panel with a gate driver circuit disposed in the active area, wherein
in the second direction, signal lines electrically connected to the first shift register circuit group are located on a side of the first shift register circuit group facing away from the second shift register circuit group(fig.13A); and
in the second direction, signal lines electrically connected to the second shift register circuit group are located on a side of the second shift register circuit group facing away from the first shift register circuit group(fig.13A).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified TANAKA further with the teaching of CHENG to include the feature in order to reduce time for transistors to suffer from stress of the bias voltage, and to increase reliability of the circuit.
Allowable Subject Matter
12. Claims 10, and 15-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
13. The following is a statement of reasons for the indication of allowable subject matter:
Claim 10: None of the cited prior arts, on record, taken alone or in combination, provides a reasonable motivation to fairly teach or suggest applicant claimed invention, "the display panel of claim 1, wherein among the plurality of pixel circuit rows, the first shift register unit and the second auxiliary shift register unit are located between a t-th pixel circuit row and a (t+1)-th pixel circuit row, and the second shift register unit and the first auxiliary shift register unit are located between the (t+1)-th pixel circuit row and a (t+2)-th pixel circuit row, wherein 1≤t≤P-2, and P is a total number of the plurality of pixel circuit rows”.
Claim 15: None of the cited prior arts, on record, taken alone or in combination, provides a reasonable motivation to fairly teach or suggest applicant claimed invention, "the display panel of claim 14, wherein a signal line disposed between the first shift register circuit group and the second shift register circuit group is a second signal line; the first horizontal wire and the second signal line are located in different film layers, and the second horizontal wire and the second signal line are located in different film layers; or the second signal line, the first horizontal wire and the second horizontal wire are located on a first film layer, and the first horizontal wire and the second horizontal wire are each provided with a cross-bridge disposed on a second film layer”.
Claim 16: None of the cited prior arts, on record, taken alone or in combination, provides a reasonable motivation to fairly teach or suggest applicant claimed invention, "the display panel of claim 14, wherein the plurality of signal lines further comprise third signal lines, and a third signal line of the third signal lines comprises a first clock signal line, a second clock signal line, a first level signal line, a second level signal line, and a start signal line; the third signal lines are electrically connected to the plurality of shift register circuit groups in one-to-one correspondence, or the first shift register circuit group and the second shift register circuit group share the third signal lines; and a signal line disposed between the first shift register circuit group and the second shift register circuit group is the first level signal line and the second level signal line”.
Claim 17: None of the cited prior arts, on record, taken alone or in combination, provides a reasonable motivation to fairly teach or suggest applicant claimed invention, "the display panel of claim 1, wherein each of the first auxiliary shift register unit and the second auxiliary shift register unit comprises a first control module, a second control module and a lower-level trigger module; wherein the first control module is electrically connected to a signal input terminal, a first clock terminal, a second clock terminal, a first level terminal and a second level terminal, separately, and the first control module is electrically connected to the lower-level trigger module at a first node, to control a potential of the first node; the second control module is electrically connected to a reset terminal, the signal input terminal, the first clock terminal, the second clock terminal, the first level terminal and the second level terminal, separately, and the second control module is electrically connected to the lower-level trigger module at a second node, to control a potential of the second node; and the lower-level trigger module is configured to control a cascade signal terminal to output a trigger signal according to the potential of the first node and the potential of the second node; or each of the first shift register unit and the second shift register unit comprises a first control module, a second control module, a lower-level trigger module and an output module; wherein the first control module is electrically connected to a signal input terminal, a first clock terminal, a second clock terminal, a first level terminal and a second level terminal, separately, and the first control module is electrically connected to the lower-level trigger module at a first node, to control a potential of the first node; the second control module is electrically connected to a reset terminal, the signal input terminal, the first clock terminal, the second clock terminal, the first level terminal and the second level terminal, separately, and the second control module is electrically connected to the lower-level trigger module at a second node, to control a potential of the second node; the lower-level trigger module is configured to control a cascade signal terminal to output a trigger signal according to the potential of the first node and the potential of the second node; and the output module is electrically connected to a third level terminal and a sweep clock signal, separately, and the output module is configured to output a sweep signal according to the trigger signal”.
Claim 19: None of the cited prior arts, on record, taken alone or in combination, provides a reasonable motivation to fairly teach or suggest applicant claimed invention, "the display panel of claim 5, wherein the display region comprises a first display region and a second display region, a first central axis of the display region is located between the first display region and the second display region, and the first central axis extends in the first direction; and the first display region comprises H1 first shift register circuit groups and G1 second shift register circuit groups, and the second display region comprises H2 first shift register circuit groups and G2 second shift register circuit groups, wherein H1, G1, H2 and G2 are each a positive integer; wherein H1=H2, and G1=G2; and a distance between a q1-th first shift register circuit group of the H1 first shift register circuit groups and the first central axis is the same as a distance between a ql-th first shift register circuit group of the H2 first shift register circuit groups and the first central axis, and a distance between a q2-th second shift register circuit group of the G1 second shift register circuit groups and the first central axis is the same as a distance between a q2-th second shift register circuit group of the G2 second shift register circuit groups and the first central axis”.
Claim 18 is also objected because of their dependency on the objected base claim.
Conclusion
14. Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner Note
15. The Examiner cites particular figures, paragraphs, columns and line numbers in the references, as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the references or as disclosed by the Examiner.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached on Mon-Fri: 9:00AM - 5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached on (571)272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2626
