Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
SUMMARY
2. The patent application filed on December 03, 2025, has been received and recorded. There were 1-20 claims in the application which claims 1 and 20 is independent claims. Therefore, claims 1-20 have been pending for consideration.
Information Disclosure Statement
3. The information disclosure statements(IDS) submitted was filed on January 20, 2026 after the mailing date of the application on December 03, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
7. Claims 1-4, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over SHIN et al.(US 2018/0068629 A1)(herein after SHIN) in view of LEE(US 2017/0193893 A1).
Regarding claim 1, SHIN teaches a display panel(display panel 100, display device 500, fig.1, Para-36), comprising a substrate (lower substrate 110, fig.2, Para-37) and a display region (display area DA, fig.1, Para-48), wherein
the display region(display area DA) comprises a plurality of shift register circuit groups(first to third sub-gate drivers 210, 220, 230, fig.1, Para-51), a shift register circuit group (210 or 220 or 230) of the plurality of shift register circuit groups comprises a plurality of shift register units(plurality of stages S1_1 to S1_2n) disposed sequentially in a first direction(DR2), the plurality of shift register circuit groups are arranged in a second direction(DR1), the first direction and the second direction intersect(fig.1), a shift register circuit group of the plurality of shift register circuit groups is configured to output a first scan signal(gate signal), the plurality of shift register circuit groups at least comprises a first shift register circuit group and a second shift register circuit group(fig.12 and related texts), [and the first shift register circuit group and the second shift register circuit group are respectively connected to first scan signal lines of different rows]; and
the display region(display area DA, fig.1) further comprises a plurality of signal lines extending in the first direction (Para-47), the plurality of signal lines comprises a plurality of signal line groups(figs.12-15), a signal line group of the plurality of signal line groups is electrically connected to a respective shift register circuit group of the plurality of shift register circuit groups(figs.12-15), and different signal line groups among the plurality of signal line groups are electrically connected to different shift register circuit groups among the plurality of shift register circuit groups(figs.12-15)(all components in an electrical circuit and/or device are electrically connected to each other, otherwise the circuit and/or device would be non-functional).
Nevertheless, SHIN is not found to teach expressly the display panel, wherein the first shift register circuit group and the second shift register circuit group are respectively connected to first scan signal lines of different rows.
However, LEE teaches expressly a display panel, wherein the first shift register circuit group(GIP1, GIP3, ---, figs.2-3) and the second shift register circuit group(GIP2, GIP4, ---, figs.2-3) are respectively connected to first scan signal lines of different rows(gate lines GL1-GL6, figs.2-3).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified SHIN with the teaching of LEE to include the feature in order to provide a display device that prevents decrease in an aperture ratio when an additional area for data signal lines is provided in areas between columns of pixels where the data lines are not arranged in the display area.
Regarding claim 2, SHIN as modified by LEE teaches the display panel of claim 1, wherein the plurality of signal line groups are disposed in one-to-one correspondence with the plurality of shift register circuit groups(Para-52, 141, SHIN; figs.2-3, LEE).
Regarding claim 3, SHIN as modified by LEE teaches the display panel of claim 2, wherein the display region comprises M shift register circuit groups, wherein M is an integer greater than 1(figs.1, 12-15, SHIN); and
the plurality of signal lines comprises N first signal lines, and the N first signal lines are divided into M signal line groups, wherein N>M, and N is an integer(figs.12-15, SHIN).
Regarding claim 4, SHIN as modified by LEE teaches the display panel of claim 3, wherein the display region further comprises a plurality of pixel circuits, and the plurality of pixel circuits are arranged in the first direction to form a plurality of pixel circuit columns sequentially arranged in the second direction(figs.1, 12-15, SHIN); and
a shift register circuit group of the plurality of shift register circuit groups is disposed in a first spacing region between two adjacent pixel circuit columns among the plurality of pixel circuit columns(Para-55, SHIN).
Claim 20 is rejected for the same reason as mentioned in the rejection of claim 1 since both claims 1 and 20 recite identical claim limitations except claim presentation in different formats.
8. Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over SHIN et al.(US 2018/0068629 A1) in view of LEE(US 2017/0193893 A1) and further in view of SHIN et al.(US 2022/0302175 A1)(herein after SHIN’175).
Regarding claim 5, SHIN as modified by LEE is not found to teach expressly the display panel of claim 3, wherein the N first signal lines comprise a first signal line group and a second signal line group; and the first signal line group comprises R first signal lines, the second signal line group comprises (N−R) first signal lines, the first signal line group is electrically connected to the first shift register circuit group, and the second signal line group is electrically connected to the second shift register circuit group, wherein N>R, and R is an integer.
However, SHIN’175 teaches a tiled display device, wherein the N first signal lines comprise a first signal line group(STRL1, CKL1-CKL4, fig.5) and a second signal line group(CBL1-CBL4, fig.5, Para-149); and
the first signal line group comprises R first signal lines (5 signal lines, fig.5), the second signal line group comprises (N−R) first signal lines(4 signal lines CBL1-CBL4, fig.5), the first signal line group is electrically connected to the first shift register circuit group, and the second signal line group is electrically connected to the second shift register circuit group(fig.5), wherein N>R, and R is an integer(5>4)(all components in electrical circuit are connected to each other electrically, otherwise the electrical circuit would be non-functional).
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the application, to have modified SHIN further with the teaching of SHIN’175 to include the feature in order to provide a display device and a tiled display device capable of displaying images that appear seamless.
Regarding claim 6, SHIN as modified by LEE and SHIN’175 teaches the display panel of claim 5, wherein
the display region further comprises a plurality of pixel circuits (figs.1&4, SHIN), and the plurality of pixel circuits are arranged in the second direction to form a plurality of pixel circuit rows sequentially arranged in the first direction(figs.1&4, Para-69, SHIN);
the plurality of pixel circuit rows are electrically connected to the plurality of shift register units(fig.1, SHIN), and a shift register unit of the plurality of shift register units is a first shift register unit or a second shift register unit(fig.1, SHIN); and
the shift register unit is disposed in a second spacing region between two adjacent pixel circuit rows among the plurality of pixel circuit rows(Para-70, SHIN).
Regarding claim 7, SHIN as modified by LEE and SHIN’175 teaches the display panel of claim 6, wherein in the first direction, among the plurality of pixel circuit rows, a shift register unit between an i-th pixel circuit row and an (i+1)-th pixel circuit row is electrically connected to a shift register unit between the (i+1)-th pixel circuit row(fig.5, SHIN’175) and an (i+2)-th pixel circuit row through a first cascade wire, wherein i is a positive integer, i≤P−2, and P is a total number of the plurality of pixel circuit rows(fig.5, SHIN’175).
Regarding claim 8, SHIN as modified by LEE and SHIN’175 teaches the display panel of claim 7, wherein the first cascade wire and the (i+1)-th pixel circuit row overlap in a direction perpendicular to the substrate(fig.1, SHIN); or
the first cascade wire comprises a first branch portion extending in the first direction, a second branch portion extending in the second direction, and a third branch portion extending in the first direction, and the first branch portion, the second branch portion and the third branch portion are electrically connected in sequence; and the first cascade wire and the plurality of pixel circuits do not overlap in a direction perpendicular to the substrate.
Allowable Subject Matter
9. Claims 9-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter:
Claim 9: None of the cited prior arts, on record, taken alone or in combination, provides a reasonable motivation to fairly teach or suggest applicant claimed invention, "the display panel of claim 6, wherein the first shift register circuit group further comprises a first auxiliary shift register unit, and the second shift register circuit group further comprises a second auxiliary shift register unit; in the first direction, two adjacent first shift register units are connected in cascade through at least one first auxiliary shift register unit; and in the first direction, two adjacent second shift register units are connected in cascade through at least one second auxiliary shift register unit.
Claim 19: None of the cited prior arts, on record, taken alone or in combination, provides a reasonable motivation to fairly teach or suggest applicant claimed invention, "the display panel of claim 5, wherein the display region comprises a first display region and a second display region, a first central axis of the display region is located between the first display region and the second display region, and the first central axis extends in the first direction; and the first display region comprises H1 first shift register circuit groups and G1 second shift register circuit groups, and the second display region comprises H2 first shift register circuit groups and G2 second shift register circuit groups, wherein H1, G1, H2 and G2 are each a positive integer; wherein H1=H2, and G1=G2; and a distance between a q1-th first shift register circuit group of the H1 first shift register circuit groups and the first central axis is the same as a distance between a ql-th first shift register circuit group of the H2 first shift register circuit groups and the first central axis, and a distance between a q2-th second shift register circuit group of the G1 second shift register circuit groups and the first central axis is the same as a distance between a q2-th second shift register circuit group of the G2 second shift register circuit groups and the first central axis”.
Claims 10-18 are also objected because of their dependency on the objected base claims respectively.
Examiner Note
11. The Examiner cites particular figures, paragraphs, columns and line numbers in the references, as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the references or as disclosed by the Examiner.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached on Mon-Fri: 9:00AM - 5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached on (571)272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2626
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