DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 15, and 17 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 16, and 18 of U.S. Patent No. 12,512,029 B1. Although the claims at issue are not identical, they are not patentably distinct from each other. Shown The italicized elements below highlight the differences between the independent claims.
Application # 19/408676
US Patent 12,512,029 B2
1. A gate driving circuit, comprising a plurality of cascaded shift registers, wherein:
1. A gate driving circuit, comprising a plurality of cascaded shift registers, wherein:
a shift register of the plurality of shift registers includes an input module, a node control module, a first coupling module, a second coupling module and an output module;
a shift register of the plurality of shift registers includes an input module, a node control module, a first coupling module, a second coupling module and an output module;
the input module is respectively connected to a first power supply end, a first clock end, a trigger signal end, a first node and a second node, and is configured to adjust potentials of the first node and the second node;
the input module is respectively connected to a first power supply end, a first clock end, a trigger signal end, a first node and a second node, and is configured to adjust potentials of the first node and the second node;
the node control module is respectively connected to the first node, the second node, the first power supply end, a second power supply end, the first clock end, a second clock end, a third node and a fourth node, and is configured to adjust potentials of the third node and the fourth node;
the node control module is respectively connected to the first node, the second node, the first power supply end, a second power supply end, the first clock end, a second clock end, a third node and a fourth node, and is configured to adjust potentials of the third node and the fourth node;
the first coupling module includes a first switch unit and a first capacitor, the first switch unit is respectively connected to the second clock end, the second power end and a fifth node, and the first capacitor is placed between, and connected to, the fifth node and the fourth node;
the first coupling module includes a first switch unit and a first capacitor, the first switch unit is respectively connected to the second clock end, the second power end and a fifth node, and the first capacitor is placed between, and connected to, the fifth node and the fourth node;
the second coupling module includes a second capacitor placed between, and connected to, the fourth node and a shift output end;
the second coupling module includes a second capacitor placed between, and connected to, the fourth node and a shift output end;
the output module is respectively connected to the third node, the fourth node, the first power supply end, the second power supply end and the shift output end, and is configured to control a signal at the shift output end; and
the output module is respectively connected to the third node, the fourth node, the first power supply end, the second power supply end and the shift output end, and is configured to control a signal at the shift output end; and
a capacitance of the second capacitor is smaller than a capacitance of the first capacitor.
a capacitance of the second capacitor differs from a capacitance of the first capacitor, wherein C21=a*C11, 1<a≤1.16, or C21=b*C11, 0<b≤0.5, C21 is the capacitance of the second capacitor and C11 is the capacitance of the first capacitor.
It is clear that all the elements of the application claim 1 are to be found in patent claim 1 (as the application claim 1 fully encompasses patent claim 1). The difference between the application claim 1 and the patent claim 1 lies in the fact that the patent claim includes many more elements and is thus much more specific. Thus the invention of claim 1 of the patent is in effect a “species” of the “generic” invention of the application claim 1. It has been held that the generic invention is “anticipated” by the “species”. See In re Goodman, 29 USPQ2d 2010 (Fed. Cir. 1993). Since application claim 1 is anticipated by claim 1 of the patent, it is not patentably distinct from claim 1 of the patent.
Specifically the Patent discloses the embodiment:
a capacitance of the second capacitor differs from a capacitance of the first capacitor, wherein C21=a*C11, 1<a≤1.16, or C21=b*C11, 0<b≤0.5, C21 is the capacitance of the second capacitor and C11 is the capacitance of the first capacitor.
The bolded statement includes a mathematical formula which makes the second capacitor is smaller than the first capacitor. Therefore reading on Claim 1 of the Application.
With respect to dependent claims:
Claim 2 is related to claim 1 of US Patent.
Claim 3 is related to claim 4 of US Patent.
Claim 4 is related to claim 6 of US Patent.
Claim 5 is related to claim 8 of US Patent.
Claim 6 is related to claim 9 of US Patent.
Claim 7 is related to claim 10 of US Patent.
Claim 8 is related to claim 11 of US Patent.
Claim 9 is related to claim 12 of US Patent.
Claim 10 is related to claim 5 of US Patent.
Claim 11 is related to claim 7 of US Patent.
Claim 12 is related to claim 13 of US Patent.
Claim 13 is related to claim 14 of US Patent.
Claim 14 is related to claim 15 of US Patent.
Claim 16 is related to claim 17 of US Patent.
If Applicant agrees that there exists a Non-Statutory Double Patenting between Application # 19/408676 and US Patent 12,512,029 B1.
Then, the Examiner request Applicant to provide a terminal disclaimer between Application and US Patent.
Allowable Subject Matter
Claims 1, 15, and 17 are rejected on the ground of nonstatutory double patenting, but would be allowable after the filling of the terminal disclaimer.
The following is a statement of reasons for the indication of allowable subject matter:
The claims 1, 15, and 17 are directed to the second capacitor being smaller than the first capacitor. The prior art reference of Park teaches the opposite in which the second capacitor is greater than the first capacitor. Therefore as indicated in the office action dated 06/09/205 of case # 18/930143 the claim limitation was indicated to include allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam J Snyder/ Primary Examiner, Art Unit 2623 06/12/2026
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