Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
SUMMARY
2. The application filed on December 05, 2025, has been received and made of record. There are 1-20 claims in the application of which claims 1, and 19 are independent claims. claims 2-18 and 20 are dependent claims. Therefore, claims 1-20 are pending for consideration.
Information Disclosure Statement
3. The information disclosure statement(IDS) submitted was filed along with the mailing date of the application on December 05, 2025. Another IDS submitted was filed on May 21, 2026 after mailing date of the application. Both the IDS submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
4. The drawings are objected to under 37 CFR 1.83(a) because they fail to show details circuit diagram as described in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and 19 recite the limitations, “a corresponding data line”. A first pixel electrode and a second pixel electrode respectively connected to corresponding data line and adjacent to each other. It is not clear from the claim language that the “corresponding data line” is one data line connected to both the first pixel electrode and the second pixel electrode or two individual data lines are connected to the first pixel electrode and the second pixel electrode independently. Applicant is suggested to clearly define the limitations “corresponding data line” recited in each claim of the claim set. For the purpose of prosecution of the application, examiner interpreted both first pixel electrode and second pixel electrode connected to one data line (corresponding data line). Having considered corresponding data line a single data line connected to both first pixel electrode and second pixel electrode, there is insufficient antecedent in the claim for the limitations.
The same arguments are applied to claims 2, and 11.
Claims 3-10, 12-18 and 20 are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph because of their dependency on the rejected base claims respectively.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
10. Claims 1-5, 7, 9-11, and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over XIONG(US 2021/0020131 A1) in view of Aoki et al.(US 2010/0171129 A1)(herein after Aoki).
Regarding claim 1, XIONG teaches a display module(display panel, fig.1, Para-21), comprising:
pixel units(sub-pixel group 300, fig.1, Para-21); wherein each pixel unit comprises a pixel electrode(Para-23), a common electrode(Para-23), and a microcapsule structure(liquid crystal molecules, Para-23); the pixel electrode is disposed opposite the common electrode(Para-23), and the microcapsule structure is disposed between the pixel electrode and the common electrode(Para-23); [the microcapsule structure comprises charged particles];
drive transistors(fig.1, Para-23); wherein each drive transistor comprises a control end(gate, fig.1, Para-23), a first end(drain or source end, fig.1, Para-23), and a second end (source or drain end, fig.1, Para-23); the second end is electrically connected to a corresponding pixel electrode for driving the corresponding pixel electrode(Para-23);
scan lines(scan lines 100, fig.1, Para-22); wherein each scan line is electrically connected to the control end of a corresponding drive transistor(Para-23), for supplying a scanning signal to a corresponding pixel unit(Para-22); and
data lines(data lines 200, fig.1, Para-22/23); wherein each data line is electrically connected to the first end of a corresponding drive transistor(Para-22/23), for supplying a data signal to a corresponding pixel unit(Para-22/23);
wherein each pixel unit(sub-pixels group 300) comprises a first pixel unit(first sub-pixel 310 or second sub-pixel 320, fig.1, Para-23) and a second pixel unit(second sub-pixel 320, or first sub-pixel 310, fig.1, Para-23) that are adjacent to each other (fig.1, Para-23);
within each display cycle(fig.6):
in a first phase(first drive mode or second drive mode, fig.6, Para-44), the first pixel unit is configured to receive the data signal corresponding to a frame pushed by a corresponding data line(Para-44);
in a second phase(second drive mode, or first drive mode, fig.6, Para-44), the second pixel unit is configured to receive the data signal corresponding to a next frame pushed by a corresponding data line(Para-44); the first phase is prior to the second phase(fig.6).
Nevertheless, XIONG is not found to teach expressly the display module, wherein the microcapsule structure comprises charged particles.
However, Aoki teaches an active-matrix electrophoretic display apparatus, wherein the microcapsule structure comprises charged particles(fig.5, Para-87).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the application, to have modified XIONG with the teaching of Aoki to include the features in order to provide an electronic device having a higher operation speed.
Regarding claim 2, XIONG as modified by Aoki teaches the display module according to claim 1, wherein the pixel units are arranged in an array(fig.1, XIONG; active matrix substrate and an electrophoretic display apparatus, Para-7, Aoki);
within the display cycle:
in the first phase(first drive mode or second drive mode, fig.6, Aoki) the drive transistors, corresponding to the first pixel units of the pixel units in multiple rows (figs.1-7, Aoki), are turned on sequentially(fig.2, Aoki), and the first pixel units in the multiple rows are caused to receive the data signals corresponding to the frame pushed by corresponding data lines to display an image corresponding to the frame (Para-44, XIONG; Para-49/50, Aoki);
in the second phase(second drive mode, or first drive mode, fig.6, Para-44, XIONG), the drive transistors, corresponding to the second pixel units of the pixel units in the multiple rows, are turned on sequentially(figs.2-4, XIONG), and the second pixel units in the multiple rows are caused to receive the data signals corresponding to the next frame pushed by corresponding data lines to display another image corresponding to the next frame(Para-44, XIONG; ; Para-49/50, Aoki).
Regarding claim 3, XIONG as modified by Aoki teaches the display module according to claim 2, wherein for each pixel unit:
in the pixel unit(300, fig.1, XIONG), the pixel electrode comprises a first pixel electrode and a second pixel electrode that are adjacent to each other(Para-23, XIONG); the first pixel electrode forms the first pixel unit with the common electrode(Para-23, XIONG) and the microcapsule structure(liquid crystal, XIONG; electrophoretic particles 26-27, fig.5A, Aoki), and the second pixel electrode forms the second pixel unit with the common electrode(Para-23, XIONG) and the microcapsule structure(liquid crystal, XIONG; electrophoretic particles 26-27, fig.5A, Aoki);
the drive transistors(fig.1, XIONG) comprise a first transistor(fig.1, XIONG) and a second transistor(fig.1, XIONG) corresponding to the pixel unit(300, fig.1, XIONG), the second end of the first transistor being electrically connected to the first pixel electrode, and the second end of the second transistor being electrically connected to the second pixel electrode(fig.1, XIONG; fig.1, Aoki).
Regarding claim 4, XIONG as modified by Aoki teaches the display module according to claim 3, wherein the first end of the first transistor and the first end of the second transistor are each electrically connected to a same corresponding data line(D1, fig.1, XIONG);
the scan lines comprise a first scan line(G1, fig.1, XIONG) and a second scan line(G2, fig.1, XIONG) corresponding to the pixel unit(300), the first scan line(G1) being electrically connected to the control end of the first transistor(fig.1), the second scan line(G2) being electrically connected to the control end of the second transistor;
within the display cycle:
in the first phase(first drive mode, or second drive mode, Para-44, XIONG), the first scan line(G1) is configured to push the scanning signal to the first transistor(fig.6, XIONG), and the first pixel unit is configured to receive the data signal(D1) corresponding to the frame(frame 1) pushed by the same corresponding data line(D1, figs.1&6, Para-44, XIONG);
in the second phase(second drive mode or first drive mode, Para-44, XIONG), the second scan line(G2) is configured to push the scanning signal to the second transistor, and the second pixel unit is configured to receive the data signal(D1) corresponding to the next frame(frame 2) pushed by the same corresponding data line(D2, figs.1&6, Para-44, XIONG).
Regarding claim 5, XIONG as modified by Aoki teaches the display module according to claim 4, wherein within the display cycle:
in the first phase(first drive mode, XIONG), the first scan lines(G1, G3, G5, G7) corresponding to the pixel units are configured to push the scanning signals corresponding to the frame row by row(figs.6-7 and related texts, XIONG), and the first transistors corresponding to the pixel units are caused to be turned on row by row(figs.6-7 and related texts, XIONG); the data lines(200) are configured to push the data signals corresponding to the frame to the first pixel units of the pixel units column by column(figs.6-7 and related texts, XIONG), for displaying an image corresponding to the frame(Para-44, XIONG; Para-49/50, Aoki);
in the second phase(second drive mode, XIONG), the second scan lines(G2, G4, G6, G8) corresponding to the pixel units are configured to push the scanning signals corresponding to the next frame row by row(figs.6-7 and related texts, XIONG), and the second transistors corresponding to the pixel units are caused to be turned on row by row(figs.6-7); the data lines are configured to push the data signals corresponding to the next frame to the second pixel units of the pixel units column by column, for displaying another image corresponding to the next frame(Para-44, XIONG; Para-49/50, Aoki).
Regarding claim 7, XIONG as modified by Aoki teaches the display module according to claim 3, wherein the control end of the first transistor and the control end of the second transistor are each electrically connected to a same corresponding scan line(G1, fig.1, Aoki);
the data lines comprise a first data line(S1) and a second data line(S2) corresponding to the pixel unit(40), the first data line(S1) being electrically connected to the first end of the first transistor(41), and the second data line(S2) being electrically connected to the first end of the second transistor(41);
within the display cycle:
in the first phase(first drive mode, XIONG), the same corresponding scan line(G1) is configured to push the scanning signal to the first transistor, and the first data line(S1) is configured to push the data signal corresponding to the frame to the first pixel unit via the first transistor(41);
in the second phase(second drive mode, XIONG), the same corresponding scan line(G1) is configured to push the scanning signal to the second transistor(41, first row and second column), and the second data line(S2) is configured to push the data signal corresponding to the next frame to the second pixel unit via the second transistor(41).
Claim 9 is rejected for the same reason as mentioned in the rejection of claim 4, since claim 9 recites the same limitations as in claim 4 except minor change in wording and terminology.
Claim 10 is rejected for the same reason as mentioned in the rejection of claim 5, since claim 10 recites the same limitations as in claim 5 except minor change in wording and terminology.
Regarding claim 11, XIONG as modified by Aoki teaches the display module according to claim 2, where the common electrode comprises a first common electrode and a second common electrode that are adjacent to each other(Para-23, XIONG); the pixel electrode forms the first pixel unit with the first common electrode and the microcapsule structure, and the pixel electrode forms the second pixel unit with the second common electrode and the microcapsule structure(Para-23, XIONG);
for each pixel unit, within the display cycle, a corresponding scan line is configured to push the scanning signal to the drive transistors corresponding to the first pixel units in the first phase and the second phase(Para-23, 44, XIONG);
in the first phase(first drive mode, XIONG), a corresponding data line is configured to push the data signal corresponding to the frame to the pixel electrode via the first end, the first common electrode is configured to push a first common voltage signal, and the first pixel unit is caused to receive the data signal corresponding to the frame(fig.6, Para-44, XIONG);
in the second phase(second drive mode), the corresponding data line is configured to push the data signal corresponding to the next frame to the pixel electrode via the first end, the second common electrode is configured to push a second common voltage signal, and the second pixel unit is caused to receive the data signal corresponding to the next frame(fig.6, Para-44, XIONG).
Claim 13 is rejected for the same reason as mentioned in the rejection of claim 3, since claim 13 recites the same limitations as in claim 3 except minor change in wording and terminology.
Claim 14 is rejected for the same reason as mentioned in the rejection of claim 7, since claim 14 recites the same limitations as in claim 7 except minor change in wording and terminology.
Claim 15 is rejected for the same reason as mentioned in the rejection of claim 5, since claim 15 recites the same limitations as in claim 5 except minor change in wording and terminology.
Regarding claim 16, XIONG as modified by Aoki teaches the display module according to claim 13, wherein the first end of the first transistor and the first end of the second transistor are each electrically connected to a same corresponding data line(figs.1,3&5-7, XIONG);
the scan lines comprise a first scan line(G1, G3, G5, G7) and a second scan line(G2, G4, G6, G8) corresponding to the pixel unit(300), the first scan line being electrically connected to the control end of the first transistor, the second scan line being electrically connected to the control end of the second transistor(figs.1,3&5-7, XIONG);
within the display cycle:
in the first phase(first drive mode, XIONG), the first scan line is configured to push the scanning signal to the first transistor, the same corresponding data line is configured to push the data signal corresponding to the frame to the first pixel electrode via the first transistor, the first common electrode is configured to push a first common voltage signal, and the first pixel unit is caused to receive the data signal corresponding to the frame(figs.6-7, and related texts, XIONG);
in the second phase(first drive mode, XIONG), the second scan line is configured to push the scanning signal to the second transistor, the same corresponding data line is configured to push the data signal corresponding to the next frame to the second pixel electrode via the second transistor, the second common electrode is configured to push a second common voltage signal, and the second pixel unit is caused to receive the data signal corresponding to the next frame(figs.6-7, and related texts, XIONG).
Claim 17 is rejected for the same reason as mentioned in the rejection of claim 5, since claim 17 recites the same limitations as in claim 5 except minor change in wording and terminology.
Regarding claim 18, XIONG as modified by Aoki teaches the display module according to claim 1, wherein the microcapsule structure comprises an electrophoresis medium, and positive-charged particles and negative-charged particles suspended in the electrophoresis medium(Para-71, 87-88, Aoki); the positive-charged particles and the negative-charged particles are the charged particles of different colors(Para-71, 87-88, Aoki).
Claim 19 is rejected for the same reason as mentioned in the rejection of claims 1 and 5, since claim 19 recites substantially the same limitations as in claims 1, and 5 in combination except minor change in wording and terminology at the preamble.
Claim 20 is rejected for the same reason as mentioned in the rejection of claim 2, since claim 20 recites the same limitations as in claim 2 except minor change in wording and terminology.
Allowable Subject Matter
11. Claims 6, 8 and 12 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
12. The following is a statement of reasons for the indication of allowable subject matter:
Claim 6: None of the prior art, on record, taken along or in combination, provides a reasonable motivation and/or reason to fairly teach or suggest the applicant’s claim invention, “the display module according to claim 5, wherein after the first phase ends, the second phase is entered after a preset period of time”.
Claim 8: None of the prior art, on record, taken along or in combination, provides a reasonable motivation and/or reason to fairly teach or suggest the applicant’s claim invention, “the display module according to claim 7, wherein within the display cycle: in the first phase, the scan lines are configured to push the scanning signals corresponding to the frame row by row, and the drive transistors are caused to be turned on row by row; the first data lines corresponding to the pixel units are configured to push the data signals corresponding to the frame to the first pixel units of the pixel units column by column, for displaying an image corresponding to the frame; after each of the first data lines has pushed for a period of time, a corresponding second data line is configured to push the data signal corresponding to the next frame to a corresponding second pixel unit in advance; in the second phase, the scan lines are configured to push the scanning signals corresponding to the next frame row by row, and the second pixel units of the pixel units are configured to receive the data signals corresponding to the next frame, for displaying another image corresponding to the next frame”.
Claim 12: None of the prior art, on record, taken along or in combination, provides a reasonable motivation and/or reason to fairly teach or suggest the applicant’s claim invention, “the display module according to claim 11, wherein for the pixel units, within the display cycle, the scan lines are configured to push the scanning signals row by row, and the drive transistors are caused to be turned on row by row; in the first phase, the first common electrodes of the pixel units are configured to push the first common voltage signals; the data lines are configured to push the data signals corresponding to the frame to the pixel electrodes of the pixel units column by column, such that a corresponding electric field is formed in each of the first pixel units of the pixel units, for displaying an image corresponding to the frame; after the data lines have pushed the data signals corresponding to the frame for a period of time, the second common electrodes of the pixel units are configured to push the second common voltage signals; after another period of time, the second phase is entered; in the second phase, the data lines are configured to push the data signals corresponding to the next frame to the pixel electrodes of the pixel units column by column, such that a corresponding electric field is formed in each of the second pixel units of the pixel units, for displaying another image corresponding to the next frame”.
Examiner Note
13. The Examiner cites particular figures, paragraphs, columns and line numbers in the references, as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the references or as disclosed by the Examiner.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached Mon-Fri: 9:00AM - 5:30PM.
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/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2626
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