DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/0/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou (US 2019/0267435).
As to Claim 1, Zhou discloses A pixel comprising: a light emitting element positioned between a first power line and a second power line (fig.1, light emitting diode D1 positioned between power source VDD and VSS);
a first transistor (fig.1, transistor M1) connected to the first power line via a first node (fig.15, transistor M1 connected to VDD via first node (node formed source of M1 connected to drain of M5); para.0049), connected to the second power line via a second node and the light emitting element (fig.1, transistor M1 connected to VSS via a second node (node formed drain of M1 connected to source of M6) and light emitting diode D1), and having a gate electrode connected to a third node (fig.1, gate of M1 connected third node (node D));
a second transistor (fig.1, transistor M2) connected between a data line (fig.1, Vdata) and the first node (fig.1, first node (node formed source of M1 connected to drain of M5)) and having a gate electrode connected to a scan line (fig.1, gate of M2 connected to scan line S2);
a third transistor (fig.1, transistor M3) connected between the second node (fig.1, second node (node formed drain of M1 connected to source of M6)) and the third node (fig.1, third node (node D)), and having a gate electrode connected to the scan line (fig.1, gate of M3 connected to scan line S2); and
a first capacitor (fig.1, capacitor C2) having a first electrode connected to the first node (fig.1, electrode of C2 connected to first node via transistor M2) and a second electrode connected to the second node (fig.1, electrode of C2 connected to second node via transistor M3).
As to Claim 2, Zhou discloses a fourth transistor (fig.1, transistor M5) connected between the first power line (fig.1, VDD) and the first node (fig.1, first node (node formed source of M1 connected to drain of M5)) and having a gate electrode connected to a light emission control line (fig.1, emission line EM); and a fifth transistor (fig.1, transistor M6) connected between the second node (fig.1, second node (node formed drain of M1 connected to source of M6)) and an anode electrode of the light emitting element (fig.1, anode of light emitting D1) and having a gate electrode connected to the light emission control line (fig.1, gate of M6 connected emission line EM).
As to Claim 3, Zhou discloses wherein: the second transistor and the third transistor are set to a turn-on state during a first period of a frame period (fig.2, period t2, transistors M2 and M3 are on-state; para.0082), and the fourth transistor and the fifth transistor are set to a turn-off state during the first period (fig.2, transistors M5 and M6 are off-state; para.0082).
As to Claim 4, Zhou discloses wherein the first period is a first horizontal period (fig.2).
As to Claim 5, Zhou discloses a second capacitor connected between the first power line and the third node (fig.1, capacitor Cst connected between VDD and third node (node D)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, 12-17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 2019/0267435) in view of Kim et al. (US 2019/0266928).
As to Claim 6, Zhou does not expressly disclose, but Kim et al. discloses: a second capacitor connected between the first power line and the second node (fig.15, capacitor C11” connected between ELVDD and node N13; para.0122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhou with the teachings of Kim et al., the motivation being to control the emission timing of the light emitting diode according to the second capacitor (para.0122).
As to Claim 12, Zhou discloses A display device comprising: pixels connected to scan lines, data lines, and light emission control lines (fig.1; para.0058, 0061, 0096); a scan driver which drives the scan lines; a light emission driver which drives the light emission control lines; and a data driver which drives the data lines,
wherein a pixel among the pixels comprises: a light emitting element positioned between a first power line and a second power line (fig.1, light emitting diode D1 positioned between power source VDD and VSS);
a first transistor (fig.1, transistor M1) connected to the first power line via a first node (fig.15, transistor M1 connected to VDD via first node (node formed source of M1 connected to drain of M5); para.0049), connected to the second power line via a second node and the light emitting element (fig.1, transistor M1 connected to VSS via a second node (node formed drain of M1 connected to source of M6) and light emitting diode D1), and having a gate electrode connected to a third node (fig.1, gate of M1 connected third node (node D));
a second transistor (fig.1, transistor M2) connected between a data line among the data lines (fig.1, Vdata) and the first node (fig.1, first node (node formed source of M1 connected to drain of M5)) and having a gate electrode connected to a scan line among the scan lines (fig.1, gate of M2 connected to scan line S2);
a third transistor (fig.1, transistor M3) connected between the second node (fig.1, second node (node formed drain of M1 connected to source of M6)) and the third node (fig.1, third node (node D)), and having a gate electrode connected to the scan line (fig.1, gate of M3 connected to scan line S2); and
a first capacitor (fig.1, capacitor C2) having a first electrode connected to the first node (fig.1, electrode of C2 connected to first node via transistor M2) and a second electrode connected to the second node (fig.1, electrode of C2 connected to second node via transistor M3).
Zhou does not expressly disclose a scan driver which drives the scan lines; a light emission driver which drives the light emission control lines; and a data driver which drives the data lines.
Kim et al. discloses a display device comprising: pixels connected to scan lines, data lines, and light emission control lines (fig.1, pixels PX, para.0049); a scan driver which drives the scan lines (fig.1, gate driver 200; para.0050); a light emission driver which drives the light emission control lines (fig.1, emission control driver 400; para.0052); and a data driver which drives the data lines (fig.1, data driver 300; para.0051).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhou with the teachings of Kim et al. in order to perform and control the drive operations of the display device.
As to Claim 13, Zhou in view of Kim et al. disclose a fourth transistor (Zhou-fig.1, transistor M5) connected between the first power line (Zhou-fig.1, VDD) and the first node (Zhou-fig.1, first node (node formed source of M1 connected to drain of M5)) and having a gate electrode connected to a light emission control line among the light emission control lines (Zhou-fig.1, emission line EM); and a fifth transistor (Zhou-fig.1, transistor M6) connected between the second node (Zhou-fig.1, second node (node formed drain of M1 connected to source of M6)) and an anode electrode of the light emitting element (Zhou-fig.1, anode of light emitting D1) and having a gate electrode connected to the light emission control line (Zhou-fig.1, gate of M6 connected emission line EM).
As to Claim 14, Zhou in view of Kim et al. disclose wherein: the scan driver supplies an enable scan signal to the scan line such that the second transistor and the third transistor are turned on during a first period of a frame period (Zhou-fig.2, period t2, transistors M2 and M3 are on-state; para.0082; Kim-fig.1), and the light emission driver supplies a disable light emission control signal to the light emission control line such that the fourth transistor and the fifth transistor are turned off during the first period (Zhou-fig.2, period t2, transistors M5 and M6 are off-state; para.0082; Kim-fig.1).
As to Claim 15, Zhou in view of Kim et al. disclose wherein: the first period is a first horizontal period; and the data driver supplies a data signal to the data line during the first period (Zhou-fig.2, period t2, transistor M2 is on; para.0068).
As to Claim 16 Zhou in view of Kim et al. disclose wherein the pixel further comprises a second capacitor connected between the first power line and the third node (Zhou- fig.1, capacitor Cst connected between VDD and third node (node D)).
As to Claim 17, Zhou in view of Kim et al. disclose wherein the pixel further comprises a second capacitor connected between the first power line and the second node (Kim-fig.15, capacitor C11” connected between ELVDD and node N13; para.0122).
As to Claim 20, has limitations similar to those of Claim 12 and are met by the references as set forth above. Claim 20, further recites a processor; and a display module which displays an image based on image data supplied from the processor (Kim-fig.1, para.0047-0049).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 2019/0267435) in view of Feng et al. (US 2025/0246136).
As to Claim 7, Zhou does not expressly disclose, but Feng et al. discloses: a second capacitor connected between the second node and the second power line (fig.6, capacitor c2 connected between second node N2 and power source VSS; para.0137; fig.17A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhou with the teachings of Feng et al., the motivation being to aid in making the driving current of flowing through the light emitting element more stable and making the brightness of the display more uniform.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 2019/0267435) in view of Kim et al. (US 2019/0266928), further in view of Feng et al. (US 2025/0246136).
As to Claim 18, Zhou in view of Kim et al., do not expressly disclose, but Feng et al. discloses: wherein the pixel further comprises a second capacitor connected between the second node and the second power line (fig.6, capacitor c2 connected between second node N2 and power source VSS; para.0137; fig.17A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Zhou in view of Kim et al., with the teachings of Feng et al., the motivation being to aid in making the driving current of flowing through the light emitting element more stable and making the brightness of the display more uniform.
Allowable Subject Matter
Claims 8-11, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 8, 19 is allowable over the prior art of record since the cited references alone or in combination do not teach or suggest “a sixth transistor connected between the second electrode of the first capacitor and the second node and having a gate electrode connected to the scan line; and a seventh transistor connected between the second electrode of the first capacitor and the second power line and having a gate electrode connected to the light emission control line” along with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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