DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE HAVING A GATE DRIVER WITH DIFFERENT TRANSISTOR CHARACTERISTICS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn (U.S. Patent Pub. No. 2023/0215381).
Regarding claim 1, Ahn discloses a display device (100), (fig. 1, [0054]), comprising:
a display panel (120) in which a plurality of pixels (P) are disposed, (fig. 1, [0055-0056]); and
a gate driver (140) configured to supply a gate signal (GL) to the display panel (120), (fig. 1, [0067]), wherein the gate driver comprises:
a pull-up transistor (T1) configured to pull up an output terminal (Output) in response to a signal of a Q node (Q), (fig. 5, [0127]);
a pull-down transistor (T2) configured to pull down the output terminal (Output) in response to a signal of a QB node (QB), (fig. 5, [0128]);
a first gate transistor (T3) configured to transmit a start signal (GVST) to a first node (Q2) in response to a first clock signal (GCLK), (fig. 5, [0122]);
a transfer transistor (TA) configured to transmit a signal of the first node (Q2) to the Q node (Q) in response to a gate low voltage (VGL), (fig. 5, [0124-0125]); and
a second gate transistor (T5) configured to transmit a gate high voltage (VGH) to the QB node (QB) in response to the signal of the first node (Q2), (fig. 5, [0148]).
Regarding claim 2, Ahn discloses wherein the gate driver further comprises a third gate transistor (T4) configured to transmit the gate low voltage (VGL) to the QB node (QB) in response to the signal of the Q node (Q), (fig. 5, [0147]).
Regarding claim 8, Ahn discloses further comprising a first capacitor (CQ) connected between the Q node (Q) and the output terminal (Output), (fig. 5, [0129]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Kim et al (U.S. Patent Pub No. 2019/0057978).
Regarding claim 9, Ahn discloses everything as specified above in claim 8. However, Ahn does not mention a second capacitor.
In a similar field of endeavor, Kim teaches further comprising a second capacitor (CQB) connected between the QB node (QB) and the gate high voltage (VGH), (fig. 6, [0105]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ahn, by specifically providing the second capacitor, as taught by Kim, for the purpose of having a fast response time, [0003].
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Liu et al (U.S. Patent Pub. No. 2024/0169904).
Regarding claim 10, Ahn discloses everything as specified above in claim 1. However, Ahn does not mention the pixels comprising a light-emitting element.
In a similar field of endeavor, Liu teaches wherein each of the plurality of pixels (fig. 1) comprises:
a light-emitting element (OLED), (fig. 1, [0108]);
a capacitor (C) configured to sample a data voltage (Da), (fig. 1, [0109]);
a driving transistor (T3) configured to drive the light-emitting element (OLED) with a driving current corresponding to the data voltage (Vdata), (fig. 1, [0108-0109]); and
at least one first transistor (T4) and at least one second transistor (T2) having characteristics different from those of the at least one first transistor (i.e. T4 is a p-type transistor and T2 is n-type transistor), (fig. 1, [0108]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ahn, by specifically providing the pixel circuit, as taught by Liu, for the purpose of emitting light for the display device.
Regarding claim 11, Liu discloses wherein the driving transistor (T3) and the at least one first transistor (T4) include a polysilicon semiconductor layer (i.e. polycrystalline silicon transistors), (fig. 1, [0108]), and
the at least one second transistor (T2) includes an oxide semiconductor layer (i.e. metal oxide transistors), (fig. 1, [0108]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ahn, by specifically providing the pixel circuit, as taught by Liu, for the purpose of emitting light for the display device.
Regarding claim 12, Liu discloses wherein the driving transistor (T3) and the at least one first transistor (T4) are P-type thin-film transistors (P-type) , and the at least one second transistor (T2) is an N-type thin-film transistor (N-type), (fig. 1, [0108]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ahn, by specifically providing the pixel circuit, as taught by Liu, for the purpose of emitting light for the display device.
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claim 3, none of the prior art of record teaches alone or in combination the limitation “wherein the gate driver further comprises a fourth gate transistor configured to transmit the signal of the Q node to the third gate transistor in response to a second clock signal.”
Claims 4-7 are dependent upon claim 3 and are allowed for the reason mentioned above in claim 3.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG D PHAM whose telephone number is (571)270-5573. The examiner can normally be reached Monday - Friday: 9am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LONG D PHAM/Primary Examiner, Art Unit 2623
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