DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1-2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by [Kim; Sunghwan et al., US 20220285474 A1].
Regarding claim 1:
Kim discloses:
1. A display panel [Kim: Fig.1: display portion 110], comprising:
a base substrate (61) [Kim: Fig.9: substrate 200];
and a pixel driving circuit [Kim: Fig.4: pixel circuit PCij comprising transistors T1-T7 and storage capacitor Cst];
and a light-emitting unit (OLED) [Kim: Fig.4: light-emitting element OLED];
wherein the pixel driving circuit [Kim: Fig.4: pixel circuit PCij comprising transistors T1-T7 and storage capacitor Cst] is electrically connected to a first electrode of the light-emitting unit (OLED) [Kim: Fig.4: initialization transistor T7 and emission transistor T6 are connected to the anode of OLED; Examiner: The anode of the OLED is the claimed “first electrode.”], and the pixel driving circuit [Kim: Fig.4: pixel circuit PCij comprising transistors T1-T7 and storage capacitor Cst] is used to drive the light-emitting unit (OLED) [Kim: Fig.4: driving transistor T1 supplies drive current Id through T6 to the light-emitting element OLED to ELVSS];
wherein the display panel [Kim: Fig.1: display portion 110] further comprises an active layer [Kim: Fig.6: semiconductor layer Act], and the active layer [Kim: Fig.6: semiconductor layer Act] comprises a first initialization signal line (Vinit1) [Kim: Fig.6: horizontal voltage line VLh; Fig.9: VLh] and a second initialization signal line (Vinit2) [Kim: Fig.6: horizontal voltage line VLh; Fig.9: VLh; Examiner: The VLh serving one row and the VLh serving an adjacent row are construed as the claimed first and second initialization signal line.];
wherein the active layer [Kim: Fig.6: semiconductor layer Act] further comprises a tenth active portion (510) [Kim: Fig.6: driving channel region C1], a second active portion (52) [Kim: Fig.6: switching channel region C2] and a fourth active portion (54) [Kim: Fig.6: first gate initialization channel region C4a], the tenth active portion (510) [Kim: Fig.6: driving channel region C1] is used to form a channel region [Kim: Fig.6: driving channel region C1] of a driving transistor (DTFT) [Kim: Fig.4: driving transistor T1; Fig.6: C1; ¶ 0155: “the driving thin-film transistor T1 includes a driving channel region C1”] in the pixel driving circuit [Kim: Fig.4: pixel circuit PCij comprising transistors T1-T7 and storage capacitor Cst],
the second active portion (52) [Kim: Fig.6: switching channel region C2] is used to form a channel region [Kim: Fig.6: switching channel region C2] of a second transistor (T2) [Kim: Fig.4: switching transistor T2; ¶ 0159: “the switching thin-film transistor T2 includes a switching channel region C2”] in the pixel driving circuit [Kim: Fig.4: pixel circuit PCij comprising transistors T1-T7 and storage capacitor Cst], and
the fourth active portion (54) [Kim: Fig.6: first gate initialization channel region C4a] is used to form a channel region [Kim: Fig.6: first gate initialization channel region C4a] of a fourth transistor (T4) [Kim: Fig.4: gate initialization thin-film transistor T4; ¶ 0161: “The first gate initialization thin-film transistor T4a includes a first gate initialization channel region C4a”] in the pixel driving circuit [Kim: Fig.4: pixel circuit PCij comprising transistors T1-T7 and storage capacitor Cst].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is AUTO-PROCESSED AND APPROVED IMMEDIATELY upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12-15 of U.S. Patent No. 12,170,060 B2 (herein ‘060). Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated, or obvious over, the patent claims as set forth below.
Instant claim 1 is not patentably distinct from patent claims 12, 13 and 15. The 060’ patent
claims a display panel comprising a pixel driving circuit having a driving transistor, and an active layer comprising a tenth active portion forming the driving transistor channel and second active portion forming the second transistor channel, together with a fourth transistors (claims 12, 13, 15). The instant recitation that the active layer comprises a first and second initialization signal line differs from the ‘060 claims, if at all, only in an obvious manner: the common specificiation form the fist and second initialization signal lines (Vinit1, Vinit2) of the polysilicon active layer, such that the difference would have been obvious to one of ordinary skill.
Instant claim 2 is not patentably distinct from patent claim 15 which depends from claims 12-14. The ‘060 patent claims the tenth conductive portion forming the driving transistor gate (claim 12), and the fourth conductive portion, a partial structure of which forms the second transistor gate in a first pixel driving circuit and another partial structure of which forms the fourth transistor gate in a second pixel driving circuit apart in the first direction (claim 16). Instant claim 2 recites the same tenth conductive portion and the same shared fourth conductive portion, without the “apart in the first direction” limitation, and is therefore broader than and encompassed by claim 15.
Instant claims 4 is not patentably distinct from ‘060 claim 15, which recites the third conductive layer comprising the first gate line connected to the plurality of fourth conductive portions.
Instant claim 10 is not patentably distinct from ‘060 claim 14, which recites the third conductive layer comprising the reference voltage line in the first direction and connected to the thirteenth active portion through a via.
Allowable Subject Matter
Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if to overcome the double patenting rejection above (e.g., via an eTerminal Disclaimer).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the active layer comprises a first active portion, the first active portion is used to form a channel region of a first transistor in the pixel driving circuit, the first active portion comprises two sub-active portions, the first conductive layer comprises a first conductive portion, and the first conductive portion is used to form a gate electrode of the first transistor”, in combination with the other recited claim features.
Regarding claims 3-11:
Claim(s) 3-11 depend(s) on claim 2 and is/are found allowable for at least the same reason as discussed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[Chen; Yipeng et al., US 20220406874 A1] discloses:
“The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The initialization signal line layer in the display panel includes an initialization signal line pattern arranged in each sub-pixel area; the anode layer includes a plurality of anode patterns, and an anode spacing area is formed between adjacent anode patterns; the first auxiliary signal line layer is a grid structure, at least part of the first auxiliary signal line layer is located in the anode spacing area, and the initialization signal line pattern in each sub-pixel area is coupled to the first auxiliary signal line layer,” as recited in the abstract.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Koosha Sharifi-Tafreshi whose telephone number is (571)270-5897. The examiner can normally be reached Mon - Fri 8AM to 5PM EST.
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/KOOSHA SHARIFI-TAFRESHI/Primary Examiner, Art Unit 2628
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