DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE DRIVING CIRCUIT DRIVING PIXEL CIRCUIT TO PERFORM DISPLAY WITH DIFFERENT REFRESH FREQUENCIES
Claim Objections
Claims 1-20 are objected to because of the following informalities:
As per claim 1, the limitation “a first gate driving signa” should be “a first gate driving signal”, “each pixel circuit comprises” should be “each of the plurality of pixel circuits comprises”.
As per claim 2, the limitation “each pixel circuit comprises” should be “each of the plurality of pixel circuits comprises”, “wherein the compensation transistor remains a turned-on state in only one continuous time period in each frame, and the first initialization transistor and the writing transistor are turned on in a time-sharing manner in the continuous time period” should be “wherein the compensation transistor remains in a turned-on state in only one continuous time period in each frame, and the first initialization transistor and the writing transistor are turned on in a time-sharing manner in the only one continuous time period”.
As per claim 3, the limitation “each pixel circuit” should be “each of the plurality of pixel circuits”, “wherein the first initialization transistor, the second initialization transistor, and the writing transistor are turned on in the time-sharing manner in the continuous time period” should be “wherein the first initialization transistor, the second initialization transistor, and the writing transistor are turned on in the time-sharing manner in the only one continuous time period”.
As per claim 4, the limitation “each frame comprises one or more writing frames and one or more maintaining frames, and each of the writing frames or each of the maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in time sequence;
the continuous time period comprises at least part of the first stage, the second stage, and at least part of the third stage; and
in the first stage of the each of the writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line” should be
“each frame comprises one or more writing frames and one or more maintaining frames, and each of the one or more writing frames or each of the one or more maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in a time sequence;
the only one continuous time period comprises at least part of the first stage, at least part of the second stage, and at least part of the third stage; and
in the first stage of [[the]] each of the one or more writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line”.
As per claim 5, the limitation “wherein in the second stage of the each of the writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line” should be “wherein in the second stage of [[the]] each of the one or more writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line”.
As per claim 6, the limitation “wherein in the third stage of the each of the writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor” should be “wherein in the third stage of [[the]] each of the one or more writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor”
As per claim 7, the limitation “each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains the turned-on state in the continuous time period of each of the writing frames, the first initialization transistor is in the turned-on state in continuous duration of the each of the writing frames, and the second initialization transistor is in the turned-on state a plurality of times in the each of the writing frames or each of maintaining frames” should be “each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains in the turned-on state in the only one continuous time period of each of the one or more writing frames, the first initialization transistor is in the turned-on state in a continuous duration of [[the]] each of the one or more writing frames, and the second initialization transistor is in the turned-on state in a plurality of times in [[the]] each of the one or more writing frames or each of one or more maintaining frames”.
As per claim 8, the limitation “wherein in each of the writing frames, a first conduction start time of the second initialization transistor is earlier than a conduction start time of the first initialization transistor” should be “wherein in each of the one or more writing frames, a first conduction start time of the second initialization transistor is earlier than a conduction start time of the first initialization transistor”.
As per claim 9, the limitation “wherein in the writing frame, a conduction end time of the first initialization transistor is earlier than a conduction end time of the compensation transistor, and the conduction end time of the compensation transistor is earlier than a second conduction start time of the second initialization transistor” should be “wherein in the one or more writing frames, a conduction end time of the first initialization transistor is earlier than a conduction end time of the compensation transistor, and the conduction end time of the compensation transistor is earlier than a second conduction start time of the second initialization transistor”.
As per claim 10, the limitation “wherein the each frame comprises one or more writing frames and one or more maintaining frames, the first gate driving signal and the third gate driving signal each have one pulse in each of the writing frame, and the second gate driving signal has a plurality of pulses in the each of the writing frames or each of the maintaining frames” should be “wherein [[the]] each frame comprises one or more writing frames and one or more maintaining frames, the first gate driving signal and the third gate driving signal each have one pulse in each of the one or more writing frames, and the second gate driving signal has a plurality of pulses in [[the]] each of the one or more writing frames or each of the one or more maintaining frames”.
As per claim 11, the limitation “wherein in the writing frame, a first pulse end moment of the second gate driving signal is earlier than a pulse end moment of the third gate driving signal, and a second pulse start moment of the second gate driving signal is later than the pulse end moment of the third gate driving signal” should be “wherein in the one or more writing frames, a first pulse end moment of the second gate driving signal is earlier than a pulse end moment of the third gate driving signal, and a second pulse start moment of the second gate driving signal is later than the pulse end moment of the third gate driving signal”.
As per claim 12, the limitation “wherein in the writing frame, a pulse start moment of the first gate driving signal is equal to or later than a pulse start moment of the third gate driving signal, and a pulse end moment of the first gate driving signal is equal to or earlier than the pulse end moment of the third gate driving signal” should be “wherein in the one or more writing frames, a pulse start moment of the first gate driving signal is equal to or later than a pulse start moment of the third gate driving signal, and a pulse end moment of the first gate driving signal is equal to or earlier than the pulse end moment of the third gate driving signal”.
As per claim 13, the limitation “each pixel circuit” should be “each of the plurality of pixel circuits”, “the light-emitting control signal controls both the first light-emitting control transistor and the second light-emitting control transistor to be in a turned-off state outside the fifth stage of the each of the writing frames or the each of the maintaining frames, and controls both the first light-emitting control transistor and the second light-emitting control transistor to be in the turned-on state in the fifth stage of each writing frame or each maintaining frame” should be “the light-emitting control signal controls both the first light-emitting control transistor and the second light-emitting control transistor to be in a turned-off state outside the fifth stage of [[the]] each of the one or more writing frames or [[the]] each of the one or more maintaining frames, and controls both the first light-emitting control transistor and the second light-emitting control transistor to be in the turned-on state in the fifth stage of each of the one or more writing frames or each of the one or more maintaining frames”.
As per claim 14, the limitation “each pixel circuit” should be “each of the plurality of pixel circuits”.
As per claim 15, the limitation “each pixel circuit further comprises” should be “each of the plurality of pixel circuits further comprises”, “wherein the compensation transistor remains a turned-on state in only one continuous time period in each frame, and the first initialization transistor and the writing transistor are turned on in the time-sharing manner in the continuous time period” should be “wherein the compensation transistor remains in a turned-on state in only one continuous time period in each frame, and the first initialization transistor and the writing transistor are turned on in the time-sharing manner in the only one continuous time period”.
As per claim 16, the limitation “the plurality of gate driving circuits further comprise a second gate driving circuit configured to provide a second gate driving signal” should be “the plurality of gate driving circuits further comprises a second gate driving circuit configured to provide a second gate driving signal”, “each pixel circuit further comprises” should be “each of the plurality of pixel circuits further comprises”, “wherein the first initialization transistor, the second initialization transistor, and the writing transistor are turned on in the time-sharing manner in the continuous time period” should be “wherein the first initialization transistor, the second initialization transistor, and the writing transistor are turned on in the time-sharing manner in the only one continuous time period”.
As per claim 17, the limitation “the each frame comprises one or more writing frames and one or more maintaining frames, and each of the writing frames or each of the maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in time sequence;
the continuous time period comprises at least part of the first stage, the second stage, and at least part of the third stage; and
in the first stage of the each of the writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line” should be
“[[the]] each frame comprises one or more writing frames and one or more maintaining frames, and each of the one or more writing frames or each of the one or more maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in a time sequence;
the only one continuous time period comprises at least part of the first stage, at least part of the second stage, and at least part of the third stage; and
in the first stage of [[the]] each of the one or more writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line”.
As per claim 18, the limitation “wherein in the second stage of the each of the writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line” should be “wherein in the second stage of [[the]] each of the one or more writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line”.
As per claim 19, the limitation “wherein in the third stage of the each of the writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor” should be “wherein in the third stage of [[the]] each of the one or more writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor”.
As per claim 20, the limitation “the each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains the turned-on state in the continuous time period of each of the writing frames, the first initialization transistor is in the turned-on state in continuous duration of the each of the writing frames, and the second initialization transistor is in the turned-on state a plurality of times in the each of the writing frames or each of maintaining frames” should be “[[the]] each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains in the turned-on state in the only one continuous time period of each of the one or more writing frames, the first initialization transistor is in the turned-on state in a continuous duration of [[the]] each of the one or more writing frames, and the second initialization transistor is in the turned-on state a plurality of times in [[the]] each of the one or more writing frames or each of the one or more maintaining frames”.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 4-14 and 17-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-2, 4-14 and 17-20 of US Patent No. US 12142201. Although the conflicting claims are not identical, they are not patentably distinct from each other because the following reasons.
Claim 1 of the Present Application
Claims 1 and 2 of US Patent No. 12142201
A display panel, comprising:
a plurality of gate driving circuits, wherein the plurality of gate driving circuits comprise:
a first gate driving circuit arranged on a left side of the display area and configured to provide a first gate driving signa, and
a third gate driving circuit arranged on a right side of the display area and configured to provide a third gate driving signal; and
a plurality of pixel circuits arranged in an array in a display area of the display panel, and each pixel circuit, comprises:
a first initialization transistor,
a compensation transistor, wherein the compensation transistor is connected in series between the first node and a second node or a third node, and a gate of the compensation transistor is configured to receive the third gate driving signal.
wherein the first initialization transistor is connected in series between a first node and a first initialization line, and a gate of the first initialization transistor is configured to receive the first gate driving signal, and
A display panel, comprising:
a second gate driving circuit providing a second gate driving signal;
a fourth gate driving circuit providing a scanning signal; and
a first gate driving circuit providing a first gate driving signal;
a third gate driving circuit providing a third gate driving signal;
a pixel circuit, comprising:
a driving transistor, wherein a gate of the driving transistor is connected to a first node, a first electrode of the driving transistor is connected to a second node, and a second electrode of the driving transistor is connected to a third node;
a writing transistor, wherein the writing transistor is connected in series between a data line and the second node or the third node, and a gate of the writing transistor is connected to the scanning signal;
an initialization module, wherein the initialization module is connected to at least one of the first node, the second node, or the third node, to perform resetting based on at least one of the first gate driving signal or the second gate driving signal; and
a compensation transistor, wherein the compensation transistor is connected in series between the first node and the second node or the third node, and a gate of the compensation transistor is connected to the third gate driving signal,
wherein the compensation transistor remains a turned-on state in only one continuous time period in each frame, and the initialization module and the writing transistor are turned on in a time-sharing manner in the continuous time period.
Claim 2
The display panel as claimed in claim 1, wherein: the initialization module comprises a first initialization transistor,
the first initialization transistor is connected in series between the first node and a first initialization line, and a gate of the first initialization transistor is connected to the first gate driving signal; and
the first initialization transistor and the writing transistor are turned on in the time-sharing manner in the continuous time period.
Claim 4 of the Present Application
The display panel as claimed in claim 3, wherein:
each frame comprises one or more writing frames and one or more maintaining frames, and each of the writing frames or each of the maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in time sequence;
the continuous time period comprises at least part of the first stage, the second stage, and at least part of the third stage; and in the first stage of the each of the writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line.
Claim 4 of US Patent No. 12142201
The display panel as claimed in claim 3, wherein:
the each frame comprises one or more writing frames and one or more maintaining frames, and each of the writing frames or each of the maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in time sequence;
the continuous time period comprises at least part of the first stage, the second stage, and at least part of the third stage; and in the first stage of the each of the writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line.
Claim 5 of the Present Application
The display panel as claimed in claim 4, wherein in the second stage of the each of the writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line.
Claim 5 of US Patent No. 12142201
The display panel as claimed in claim 4, wherein in the second stage of the each of the writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line.
Claim 6 of the Present Application
The display panel as claimed in claim 4, wherein in the third stage of the each of the writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor.
Claim 6 of US Patent No. 12142201
The display panel as claimed in claim 4, wherein in the third stage of the each of the writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor.
Claim 7 of the Present Application
The display panel as claimed in claim 3, wherein:
each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains the turned-on state in the continuous time period of each of the writing frames, the first initialization transistor is in the turned-on state in continuous duration of the each of the writing frames, and the second initialization transistor is in the turned-on state a plurality of times in the each of the writing frames or each of maintaining frames.
Claim 7 of US Patent No. 12142201
The display panel as claimed in claim 3, wherein:
the each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains the turned-on state in the continuous time period of each of the writing frames, the first initialization transistor is in the turned-on state in continuous duration of the each of the writing frames, and the second initialization transistor is in the turned-on state a plurality of times in the each of the writing frames or each of maintaining frames.
Claim 8 of the Present Application
The display panel as claimed in claim 7, wherein in each of the writing frames, a first conduction start time of the second initialization transistor is earlier than a conduction start time of the first initialization transistor.
Claim 8 of US Patent No. 12142201
The display panel as claimed in claim 7, wherein in the each of the writing frames, a first conduction start time of the second initialization transistor is earlier than a conduction start time of the first initialization transistor.
Claim 9 of the Present Application
The display panel as claimed in claim 7, wherein in the writing frame, a conduction end time of the first initialization transistor is earlier than a conduction end time of the compensation transistor, and the conduction end time of the compensation transistor is earlier than a second conduction start time of the second initialization transistor.
Claim 9 of US Patent No. 12142201
The display panel as claimed in claim 7, wherein in the writing frame, a conduction end time of the first initialization transistor is earlier than a conduction end time of the compensation transistor, and the conduction end time of the compensation transistor is earlier than a second conduction start time of the second initialization transistor.
Claim 10 of the Present Application
The display panel as claimed in claim 3, wherein the each frame comprises one or more writing frames and one or more maintaining frames, the first gate driving signal and the third gate driving signal each have one pulse in each of the writing frame, and the second gate driving signal has a plurality of pulses in the each of the writing frames or each of the maintaining frames.
Claim 10 of US Patent No. 12142201
The display panel as claimed in claim 3, wherein the each frame comprises one or more writing frames and one or more maintaining frames, the first gate driving signal and the third gate driving signal each have one pulse in each of the writing frame, and the second gate driving signal has a plurality of pulses in the each of the writing frames or each of the maintaining frames.
Claim 11 of the Present Application
The display panel as claimed in claim 10, wherein in the writing frame, a first pulse end moment of the second gate driving signal is earlier than a pulse end moment of the third gate driving signal, and a second pulse start moment of the second gate driving signal is later than the pulse end moment of the third gate driving signal.
Claim 11 of US Patent No. 12142201
The display panel as claimed in claim 10, wherein in the writing frame, a first pulse end moment of the second gate driving signal is earlier than a pulse end moment of the third gate driving signal, and a second pulse start moment of the second gate driving signal is later than the pulse end moment of the third gate driving signal.
Claim 12 of the Present Application
The display panel as claimed in claim 11, wherein in the writing frame, a pulse start moment of the first gate driving signal is equal to or later than a pulse start moment of the third gate driving signal, and a pulse end moment of the first gate driving signal is equal to or earlier than the pulse end moment of the third gate driving signal.
Claim 12 of US Patent No. 12142201
The display panel as claimed in claim 11, wherein in the writing frame, a pulse start moment of the first gate driving signal is equal to or later than a pulse start moment of the third gate driving signal, and a pulse end moment of the first gate driving signal is equal to or earlier than the pulse end moment of the third gate driving signal.
Claim 13 of the Present Application
The display panel as claimed in claim 4, wherein: the plurality of gate driving circuits further comprise a fifth gate driving circuit configured to provide a light-emitting control signal; and
each pixel circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor, the first light-emitting control transistor is connected in series between the second node and a first power cable, and
a gate of the first light-emitting control transistor is configured to receive the light-emitting control signal, the second light-emitting control transistor is connected in series between the third node and a second power cable, and
a gate of the second light-emitting control transistor is configured to receive the light-emitting control signal; and
the light-emitting control signal controls both the first light-emitting control transistor and the second light-emitting control transistor to be in a turned-off state outside the fifth stage of the each of the writing frames or the each of the maintaining frames, and controls both the first light-emitting control transistor and the second light-emitting control transistor to be in the turned-on state in the fifth stage of each writing frame or each maintaining frame.
Claim 13 of US Patent No. 12142201
The display panel as claimed in claim 4,
wherein the pixel circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor, the first light-emitting control transistor is connected in series between the second node and a first power cable, and
a gate of the first light-emitting control transistor is connected to a light-emitting control line, the second light-emitting control transistor is connected in series between the third node and a second power cable, and
a gate of the second light-emitting control transistor is connected to the light-emitting control line; and
the light-emitting control line is connected to a light-emitting control signal, and the light-emitting control signal controls both the first light-emitting control transistor and the second light-emitting control transistor to be in a turned-off state outside the fifth stage of the each of the writing frames or the each of the maintaining frames, and controls both the first light-emitting control transistor and the second light-emitting control transistor to be in the turned-on state in the fifth stage of each writing frame or each maintaining frame.
Claim 14 of the Present Application
A display device, comprising a display panel, wherein the display panel comprises:
a plurality of gate driving circuits, comprising a first gate driving circuit configured to provide a first gate driving signal, and
a third gate driving circuit configured to provide a third gate driving signal; and a plurality of pixel circuits,
each pixel circuit comprising:
a first initialization transistor,
a compensation transistor, wherein the compensation transistor is connected in series between the first node and a second node or a third node, and a gate of the compensation transistor is configured to receive the third gate driving signal, and
a light-emitting device, a storage capacitor, and a boost capacitor,
wherein the storage capacitor is connected in series between the first node and a first power cable,
the boost capacitor is connected in series between the first node and a scanning line,
the light-emitting device is connected in series between the third node and a second power cable.
wherein the first initialization transistor is connected in series between a first node and a first initialization line, and the gate of the first initialization transistor is configured to receive the first gate driving signal,
Claims 2 and 14 of US Patent No. 12142201
A display device, comprising a display panel, wherein the display panel comprises:
a first gate driving circuit providing a first gate driving signal; a second gate driving circuit providing a second gate driving signal;
a fourth gate driving circuit providing a scanning signal; and
a third gate driving circuit providing a third gate driving signal;
a pixel circuit, comprising:
a driving transistor, wherein a gate of the driving transistor is connected to a first node, a first electrode of the driving transistor is connected to a second node, and a second electrode of the driving transistor is connected to a third node; a writing transistor, wherein the writing transistor is connected in series between a data line and the second node or the third node, and a gate of the writing transistor is connected to the scanning signal;
an initialization module, wherein the initialization module is connected to at least one of the first node, the second node, or the third node, to perform resetting based on at least one of the first gate driving signal or the second gate driving signal; and
a compensation transistor, wherein the compensation transistor is connected in series between the first node and the second node or the third node, and a gate of the compensation transistor is connected to the third gate driving signal,
wherein the compensation transistor remains a turned-on state in only one continuous time period in each frame, and the initialization module and the writing transistor are turned on in a time-sharing manner in the continuous time period;
wherein the pixel circuit further comprises a light-emitting device, a storage capacitor, a boost capacitor, and a third initialization transistor,
the storage capacitor is connected in series between the first node and the first power cable,
the boost capacitor is connected in series between the first node and a scanning line,
the light-emitting device is connected in series between the second light-emitting control transistor and the second power cable,
the third initialization transistor is connected in series between a third initialization line and an anode of the light-emitting device, and a gate of the third initialization transistor is connected to the gate of the second initialization transistor.
Claim 2
The display panel as claimed in claim 1, wherein: the initialization module comprises a first initialization transistor,
the first initialization transistor is connected in series between the first node and a first initialization line, and a gate of the first initialization transistor is connected to the first gate driving signal; and
the first initialization transistor and the writing transistor are turned on in the time-sharing manner in the continuous time period.
Claim 17 of the Present Application
The display device as claimed in claim 16, wherein:
the each frame comprises one or more writing frames and one or more maintaining frames, and each of the writing frames or each of the maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in time sequence; the continuous time period comprises at least part of the first stage, the second stage, and at least part of the third stage; and
in the first stage of the each of the writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line.
Claim 17 of US Patent No. 12142201
The display device as claimed in claim 16, wherein:
the each frame comprises one or more writing frames and one or more maintaining frames, and each of the writing frames or each of the maintaining frames comprises a first stage, a second stage, a third stage, a fourth stage, and a fifth stage that are performed in time sequence; the continuous time period comprises at least part of the first stage, the second stage, and at least part of the third stage; and
in the first stage of the each of the writing frames, the compensation transistor and the second initialization transistor are in the turned-on state, to reset a potential of the first node, a potential of the second node, and a potential of the third node through the second initialization line.
Claim 18 of the Present Application
The display device as claimed in claim 17, wherein in the second stage of the each of the writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line.
Claim 18 of US Patent No. 12142201
The display device as claimed in claim 17, wherein in the second stage of the each of the writing frames, the compensation transistor and the first initialization transistor are in the turned-on state, to reset the potential of the first node, the potential of the second node, and the potential of the third node through the first initialization line.
Claim 19 of the Present Application
The display device as claimed in claim 17, wherein in the third stage of the each of the writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor.
Claim 19 of US Patent No. 12142201
The display device as claimed in claim 17, wherein in the third stage of the each of the writing frames, the compensation transistor and the writing transistor are in the turned-on state, to write a data signal transmitted in the data line into the gate of the driving transistor.
Claim 20 of the Present Application
The display device as claimed in claim 16, wherein: the each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains the turned-on state in the continuous time period of each of the writing frames, the first initialization transistor is in the turned-on state in continuous duration of the each of the writing frames, and the second initialization transistor is in the turned-on state a plurality of times in the each of the writing frames or each of maintaining frames.
Claim 20 of US Patent No. 12142201
The display device as claimed in claim 16, wherein: the each frame comprises one or more writing frames and one or more maintaining frames, the compensation transistor remains the turned-on state in the continuous time period of each of the writing frames, the first initialization transistor is in the turned-on state in continuous duration of the each of the writing frames, and the second initialization transistor is in the turned-on state a plurality of times in the each of the writing frames or each of maintaining frames.
Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1, 4-14 and 17-20 of the Present Application anticipates claims 1-2, 4-14 and 17-20 of US Patent No. 12142201 since pending claims 1, 4-14 and 17-20 are a broader version of patented claims 1-2, 4-14 and 17-20 of US Patent No. 12142201.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-12 and 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “the writing frame". There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the writing frame". There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “the gate of the first initialization transistor". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon (US 20150364083).
As per claim 1, Jeon discloses a display panel (Fig. 1, #110; [0059]), comprising:
a plurality of pixel circuits (#118) arranged in an array in a display area of the display panel (#110), and a plurality of gate driving circuits (#540-550; [0060]; [0073]; [0130]),
wherein the plurality of gate driving circuits (Fig. 9, #540-550; [0130]) comprise:
a first gate driving circuit (#540) arranged on a left side of the display area and configured to provide a first gate driving signa ([0137]; [0140]), and
a third gate driving circuit (#550) arranged on a right side of the display area and configured to provide a third gate driving signal ([0138]; [0140]); and
each pixel circuit (Fig. 2, #118), comprises:
a first initialization transistor (#T4), wherein the first initialization transistor (#T4) is connected in series between a first node (#N1) and a first initialization line (i.e., VINIT line), and a gate of the first initialization transistor (#T4) is configured to receive the first gate driving signal ([0079]), and
a compensation transistor (#T3), wherein the compensation transistor (#T3) is connected in series between the first node (#N1) and a second node (i.e., node between #T1 and #T6) or a third node (#N2), and a gate of the compensation transistor (#T3) is configured to receive the third gate driving signal ([0078]).
As per claim 2, Jeon discloses the display panel as claimed in claim 1, wherein:
the plurality of gate driving circuits (#540-550) further comprise a fourth gate driving circuit (i.e., stage circuit) configured to provide a scanning signal ([0140]); and
each pixel circuit (#118) further comprises:
a driving transistor (#T1), wherein a gate of the driving transistor (#T1) is connected to the first node (#N1), a first electrode of the driving transistor (#T1) is connected to the second node (i.e., node between #T1 and #T6), and a second electrode of the driving transistor (#T1) is connected to the third node (#N2), and
a writing transistor (#T2), wherein the writing transistor (#T2) is connected in series between a data line (i.e., DL line) and the second node (i.e., node between #T1 and #T6) or the third node (#N2), and
a gate of the writing transistor (#T2) is configured to receive the scanning signal ([0077]);
wherein the compensation transistor (#T3) remains a turned-on state in only one continuous time period (Fig. 4, #t2-t4) in each frame ([0078]; [0094]), and the first initialization transistor (#T4) and the writing transistor (#T2) are turned on in a time-sharing manner in the continuous time period ([0077]; [0079]; [0093]-[0094]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Choi (US 20230108247).
As per claim 14, Jeon discloses a display device (Fig. 1, #100), comprising a display panel (#110; [0058]), wherein the display panel comprises:
a plurality of gate driving circuits (Fig. 9, #540-550; [0130]), comprising a first gate driving circuit (#540) configured to provide a first gate driving signal ([0137]), and
a third gate driving circuit (#550) configured to provide a third gate driving signal ([0138]); and
a plurality of pixel circuits (Fig. 2, #118; [0073]), each pixel circuit (#118) comprising:
a first initialization transistor (#T4), wherein the first initialization transistor (#T4) is connected in series between a first node (#N1) and a first initialization line (i.e., VINIT line), and the gate of the first initialization transistor (#T4) is configured to receive the first gate driving signal ([0079]),
a compensation transistor (#T3), wherein the compensation transistor (#T3) is connected in series between the first node (#N1) and a second node (i.e., node between #T1 and #T6) or a third node (#N2), and a gate of the compensation transistor (#T3) is configured to receive the third gate driving signal ([0078]), and
a light-emitting device (#EL), a storage capacitor (#Cst),
wherein the storage capacitor (#Cst) is connected in series between the first node (#N1) and a first power cable (i.e., ELVDD cable),
the light-emitting device (#EL) is connected in series between the third node (#N2) and a second power cable (i.e., ELVSS cable).
However, Jeon does not teach a boost capacitor, the boost capacitor is connected in series between the first node and a scanning line.
Choi teaches a boost capacitor (Fig. 15, #CBST), the boost capacitor (#CBST) is connected in series between the first node (i.e., node at gate of #T1) and a scanning line (#GL1; [0157]; [0164]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the boost capacitor disclosed by Choi to the plurality of pixel circuits of Jeon so as to compensate the increase or reduction of the gate voltage of the driving transistor when the inverted scan signal is changed to the high voltage or the low voltage (Choi: [0172]).
As per claim 15, Jeon in view of Choi discloses the display device as claimed in claim 14, wherein:
the plurality of gate driving circuits (Jeon: #540-550) further comprise a fourth gate driving circuit (i.e., stage circuit) configured to provide a scanning signal (Jeon: [0140])l; and
each pixel circuit (Jeon: #118) further comprises:
a driving transistor (Jeon: #T1), wherein a gate of the driving transistor (Jeon: #T1) is connected to the first node (Jeon: #N1), a first electrode of the driving transistor (Jeon: #T1) is connected to the second node (Jeon: i.e., node between #T1 and #T6), and a second electrode of the driving transistor (Jeon: #T1) is connected to the third node (Jeon: #N2), and
a writing transistor (Jeon: #T2), wherein the writing transistor (Jeon: #T2) is connected in series between a data line (Jeon: i.e., DL line) and the second node (Jeon: i.e., node between #T1 and #T6) or the third node (Jeon: #N2), and a gate of the writing transistor (Jeon: #T2) is configured to receive the scanning signal (Jeon: [0077]);
wherein the compensation transistor (Jeon: #T3) remains a turned-on state in only one continuous time period (Jeon: Fig. 4, #t2-t4) in each frame (Jeon: [0078]; [0094]), and the first initialization transistor (Jeon: #T4) and the writing transistor (Jeon: #T2) are turned on in a time-sharing manner in the continuous time period (Jeon: [0077]; [0079]; [0093]-[0094]).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of a display panel comprising a plurality of pixel circuits and a plurality of gate driving circuits, each of the plurality of pixel circuits comprises a first initialization transistor, wherein the first initialization transistor is connected in series between a first node and a first initialization line, and a gate of the first initialization transistor is configured to receive the first gate driving signal, and a compensation transistor, wherein the compensation transistor is connected in series between the first node and a second node or a third node, and a gate of the compensation transistor is configured to receive the third gate driving signal does not teach or fairly suggest each pixel circuit further comprises a second initialization transistor, wherein the second initialization transistor is connected in series between a second initialization line and the second node or the third node, and a gate of the second initialization transistor is configured to receive the second gate driving signal, wherein the first initialization transistor, the second initialization transistor, and the writing transistor are turned on in the time-sharing manner in the continuous time period.
Claim 16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of a display device comprising a display panel comprising a plurality of pixel circuits and a plurality of gate driving circuits, each of the plurality of pixel circuits comprises a first initialization transistor, wherein the first initialization transistor is connected in series between a first node and a first initialization line, and a gate of the first initialization transistor is configured to receive the first gate driving signal, and a compensation transistor, wherein the compensation transistor is connected in series between the first node and a second node or a third node, and a gate of the compensation transistor is configured to receive the third gate driving signal does not teach or fairly suggest each pixel circuit further comprises a second initialization transistor, wherein the second initialization transistor is connected in series between a second initialization line and the second node or the third node, and a gate of the second initialization transistor is configured to receive the second gate driving signal, wherein the first initialization transistor, the second initialization transistor, and the writing transistor are turned on in the time-sharing manner in the continuous time period.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/Examiner, Art Unit 2627
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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