33DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/979,684 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because copending application No. 18/979,684 includes all the limitations of the instant application including additional limitations such as the actions that occur during the and second periods.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-6, 12, 15, 19 and 28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawashima et al. (US 2020/0326570).
In regard to claim 1, Kawashima et al. teach a display device, comprising: a pixel array (fig. 14A), comprising a plurality of pixel units (elements 13); and a driving circuit (fig. 5A element 12), coupled to the pixel units through a plurality of scan signal lines (elements 121-123) and a plurality of data signal lines (fig. 14 elements 124 and 125), wherein each of the pixel units comprises: a first transistor, coupled to a first node (element 101); a second transistor (element 102), coupled to a second node (element NB); a third transistor, coupled to the second node (element 106); an equivalent bootstrap capacitor, coupled between the first node and the second node (104); and an equivalent pixel capacitor, coupled between the first node and a reference voltage (element 110 and element 129).
In regard to claim 2, Kawashima et al. teach wherein the driving circuit comprises: a scan driver, coupled to the pixel units through the scan signal lines (fig. 14A element 31), wherein the pixel units of each row or every two adjacent rows of the pixel array are coupled to the same two scan signal lines (fig. 14A, the first row is coupled to two scan lines), and the pixel units of different rows or two different adjacent rows of the pixel array are coupled to two different scan signal lines (fig. 14A, the second row is coupled to two different scan lines than the first row).
In regard to claim 4, Kawashima et al. teach wherein the scan driver sequentially drives the pixel units through the scan signal lines during a plurality of scan periods, the scan periods do not overlap with each other, and a total period of two of the scan periods for scanning the pixel units of a same column overlaps with a same data writing period (see fig. 11, the driving for each column requires the scanning of each row. The claim does not define data writing period so the broadest reasonable interpretation is each data writing period is a frame).
In regard to claim 5, Kawashima et al. teach wherein the driving circuit comprises: a scan driver, coupled to the pixel units through the scan signal lines (element 31), wherein the pixel units of each row of the pixel array are coupled to the same two scan signal lines (fig. 11, each row is coupled to 121 and 122), and the pixel units of any two adjacent rows of the pixel array share at least one scan signal line (fig. 11, the two rows share NB connected through transistor 102).
In regard to claim 6, Kawashima et al. teach wherein the scan driver sequentially drives the pixel units through the scan signal lines during a plurality of scan periods, the scan periods do not overlap with each other (fig. 5, elements 121, 122 and 123 do not overlap), and two scan periods for scanning the pixel units of a same column overlap with two adjacent data writing periods, wherein the two adjacent data writing periods are partially overlapped (fig. 11, nodes NA and NB are connected to multiple columns. When NB is activated is corresponds to the data writing period of multiple columns which must overlap).
In regard to claim 12, Kawashima et al. teach wherein the driving circuit comprises: a data driver, coupled to the pixel units through the data signal lines (element 32), wherein the pixel units in each column of the pixel array are coupled to a same data signal line, and the pixel units in different columns of the pixel array are coupled to different data signal lines (see fig. 14A, each column of pixels is coupled to a different data lines).
In regard to claim 15, Kawashima et al. teach wherein the driving circuit comprises: a data driver, coupled to the pixel units through the data signal lines, wherein the pixel units in each column of the pixel array are coupled to same two data signal lines, and the pixel units in different columns of the pixel array are coupled to two different data signal lines (see fig. 11. The entire device is couple together. Each component of the device is coupled with every other component).
In regard to claim 19, Kawashima et al. teach a substrate, wherein the pixel array is formed on the substrate (fig. 20A element 4011), wherein each of the pixel units further comprises a first metal layer (element 746 and paragraph 322), a first insulating layer (element 772 and paragraph 322), a second metal layer (elements 7441 and 744b and paragraph 323), a second insulating layer (element 726 and paragraph 323), a planarization layer (element 4112), a pixel electrode layer and an upper electrode layer patterned and selectively formed above the substrate (elements 4030 and 4031).
In regard to claim 28, Kawashima et al. teach a substrate, wherein the pixel array is formed on the substrate (fig. 20A element 4011); wherein each of the pixel units further comprises a first metal layer (element 746 and paragraph 322), a first insulating layer (element 772 and paragraph 322), a second metal layer (elements 7441 and 744b and paragraph 323), a second insulating layer (element 726 and paragraph 323), a planarization layer (element 4112), a third metal layer (element 4132 and paragraph 291), a third insulating layer (element 4032), a pixel electrode layer, and an upper electrode layer patterned and selectively formed above the substrate (elements 4030 and 4031).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 7, 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima et al. in view of Abe et al. (US 2012/0306844).
In regard to claim 3, Kawashima et al. teach all the elements of claim 3 except wherein the driving circuit further comprises: another scan driver, coupled to the pixel units through the scan signal lines, wherein the scan driver and the another scan driver are disposed on two sides of the pixel array.
Abe et al. teach wherein the driving circuit further comprises: another scan driver, coupled to the pixel units through the scan signal lines, wherein the scan driver and the another scan driver are disposed on two sides of the pixel array (fig. 2 elements 210 and 212).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kawashima et al. with the second scan driver of Abe et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kawashima et al. with the second scan driver of Abe et al. because separating the one circuit into two would decrease the size and complexity of each circuit.
In regard to claim 7, Kawashima et al. teach wherein the pixel units of each row of the pixel array are coupled to the same one odd-numbered scan signal line and one even-numbered scan signal line (fig. 11, each scan line is connected to elements 121-123), and the pixel units of different rows of the pixel array are coupled to two different scan signal lines (fig. 11, each row is connected to a different scan line 121).
Abe et al. teach a first scan driver, coupled to the pixel units through a plurality of odd-numbered scan signal lines of the scan signal lines; and a second scan driver, coupled to the pixel units through a plurality of even-numbered scan signal lines of the scan signal lines (fig. 2 elements 210 and 212).
In regard to claim 8, Abe et al. teach wherein the first scan driver and the second scan driver alternately drive the pixel units through the scan signal lines during a plurality of scan periods, the scan periods do not overlap with each other (paragraph 29, the scanning starts on the right side and ends on the left side).
In regard to claim 14, Kawashima et al. teach wherein the pixel units in some adjacent two columns of the pixel array are coupled to a same reference voltage line (fig. 13 Vref).
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima et al. in view of Li (US 2020/0027404).
In regard to claim 9, Kawashima et al. teach all the elements of claim 9 except a bidirectional circuit, coupled to the pixel units through the scan signal lines; and a scan driver, coupled to the bidirectional circuit through a plurality of output signal lines, wherein the bidirectional circuit comprises a plurality of bidirectional units, and the bidirectional units are coupled to two different adjacent output signal lines and two different adjacent scan signal lines (fig. 4A each group of transistors is coupled to the first two shift registers and the first two rows).
Li teaches a bidirectional circuit, coupled to the pixel units through the scan signal lines (element 30 and paragraph 25); and a scan driver, coupled to the bidirectional circuit through a plurality of output signal lines (see outputs of shift registers V1-V5), wherein the bidirectional circuit comprises a plurality of bidirectional units (fig. 4A, see groups of elements T3 and T4), and the bidirectional units are coupled to two different adjacent output signal lines and two different adjacent scan signal lines.
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kawashima et al. with the bidirectional scanning of Li. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kawashima et al. with the with the bidirectional scanning of Li because bidirectional scanning would allow the device to be placed in any orientation while still outputting the appropriate image.
In regard to claim 10, Li teaches wherein the output signal lines comprise a first output signal line and a second output signal line (see output of shift register stages V1 and V2), and the scan signal lines comprise a first scan signal line and a second scan signal line (fig. 1, see the scan lines for each pixel row), wherein each of the bidirectional units comprises: a first switch, wherein a first terminal of the first switch is coupled to the first output signal line (fig. 4A, T3 is connected to the output of V1), a second terminal of the first switch is coupled to the first scan signal line (T3 is connected to the first scan line connected to pixel P11), and a control terminal of the first switch is coupled to a first control signal (fig. 3, T3 is connected to K22); a second switch, wherein a first terminal of the second switch is coupled to the first output signal line (fig. 4A, the bottom T4 is connected to the output of V1), a second terminal of the second switch is coupled to the second scan signal line (the bottom T4 is connected to the scan line connected to P21), and a control terminal of the second switch is coupled to a second control signal (K21); a third switch, wherein a first terminal of the third switch is coupled to the second output signal line (Top T4 is connected to V2 output), a second terminal of the third switch is coupled to the first scan signal line (the top T4 is connected of the scan line of pixel P11), and a control terminal of the third switch is coupled to the second control signal (K21); and a fourth switch, wherein a first terminal of the fourth switch is coupled to the second output signal line (bottom T3), a second terminal of the fourth switch is coupled to the second scan signal line (the bottom T3 is connected to the pixel row with pixel P21), and a control terminal of the fourth switch is coupled to the first control signal (K22).
In regard to claim 11, Li teaches wherein the bidirectional circuit determines to sequentially drive the pixel units or reversely drive the pixel units through the scan signal lines according to the first control signal and the second control signal (paragraph 78).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima et al. in view of Wang et al. (US 2022/0013056).
In regard to claim 13, Kawashima et al. teach all the elements of claim 13 except wherein every two of the data signal lines are disposed between corresponding two columns of pixel units coupled thereto in the pixel array.
Wang et al. teach wherein every two of the data signal lines are disposed between corresponding two columns of pixel units coupled thereto in the pixel array (fig. 1).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kawashima et al. with the data line placement of Wang et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kawashima et al. with the data line placement of Wang et al. because the data line placement of Wang et al. would work equally as well in the apparatus of Kawashima et al. as it does in Wang et al. One of ordinary skill in the art would recognize the data line placement of Wang et al. would provide predictable results and could be chosen based on factors such as cost, design complexity and parasitic capacitance.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima et al. in view of Kim (US 2017/0053597).
In regard to claim 16, Kawashima et al. teach wherein the pixel units in each row of the pixel array are coupled to same two scan signal lines (fig. 11, the top row is connected to 121[n] and 122[m]), and the pixel units in different rows of the pixel array are coupled to two different scan signal lines (fig. 11, the third row is connected to 121[n+2] and 122[m+1]), wherein the pixel units in each column of the pixel array are coupled to a same data signal line, and the pixel units in different columns of the pixel array are coupled to different data signal lines (fig. 11, see data lines for each column) but does not teach wherein the driving circuit comprises: an integrated driver, coupled to the pixel units through the scan signal lines and the data signal lines.
Kim teaches wherein the driving circuit comprises: an integrated driver, coupled to the pixel units through the scan signal lines and the data signal lines (element 120).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kawashima et al. with the integrated circuit of Kim. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kawashima et al. with the integrated circuit of Kim because integrating the circuit would reduce manufacturing complexity.
In regard to claim 17, Kim teaches wherein the integrated driver is coupled to the pixel units in different columns of the pixel array through the data signal lines in a T-shaped connection manner (fig.1, the data lines Dm travel vertically and are connected to the pixels via a t-connection).
In regard to claim 18, Kim teaches wherein the integrated driver is coupled to the pixel units in different rows of the pixel array through the scan signal lines in a T-shaped connection manner (see fig. 1, the scan lines travel vertically and are connected to the horizontal lines in a t-shaped manner).
Allowable Subject Matter
Claims 20-27 and 29-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or make obvious the bootstrap capacitor being formed by the second metal layer, second insulating layer and pixel electrode layer. Kawashima et al. show the capacitor, element 104, being a traditional capacitor, not a capacitor formed from the pixel electrode and second metal layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm.
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/JOSEPH R HALEY/Primary Examiner, Art Unit 2621
