EMISSION CONTROL DRIVER

§102 §103 §112

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Foreign Priority This application is a continuation of U.S. Patent Application No. 18/815,757 (now U.S. Patent 12,499,841) filed on 08/26/2024, which is a continuation of U.S. Patent Application No. 17/748,926 (now U.S. Patent 12,073,791) filed on 05/19/2022 that claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2021-0149948 filed on 11/3/2021 in the Korean Intellectual Property Office. On 01/06/2026, an electronic copy of this document was retrieved by the USPTO, and thus on the office action summary sheet examiner has checked off the box “all” certified copies have been received at this time. Drawing Objection The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s), while no new matter should be entered: Claims 3 and 13 each include wherein the first output unit comprises: a second pull-down transistor connected between the second output terminal and the third power input terminal, a gate of the second pull-down transistor being connected to the second node, however the figures do not depict the first output unit (e.g., FIG. 4: 230) including a second pull-down transistor having these connections. Instead, the figures depict just a first pull-down transistor (e.g., FIG. 4: T21). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification Objection 4. The specification is objected to because the title is not descriptive. Correction is needed. Examiner suggests by way of example the following title: “EMISSION CONTROL DRIVER INCLUDES A STAGE HAVING A FIRST CONTROLLER, A SECOND CONTROLLER, AND A FIRST OUTPUT UNIT”. Claim Rejections – 35 USC §112 5. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 6. Claims 7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 at line 2 includes “the second node” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by amending it to “a second node”. Note that claim 2 at line 7 includes “a second node”, however claim 7 does not depend upon claim 2. Appropriate correction is required. Claim 17 at line 2 includes “the second node” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by amending it to “a second node”. Note that claim 12 at line 7 includes “a second node”, however claim 17 does not depend upon claim 12. Appropriate correction is required. Claim Rejections - 35 USC § 102 7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 9. Claims 1-2, 5, 7-9, 11-12, 15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Pub. No. 2017/0018245 A1 to Park et al. (“Park”). PNG media_image1.png 559 917 media_image1.png Greyscale PNG media_image2.png 938 582 media_image2.png Greyscale PNG media_image3.png 513 777 media_image3.png Greyscale PNG media_image4.png 364 599 media_image4.png Greyscale As to claim 1, Park discloses a driver(110)(FIGs. 1, 4-5; ¶¶0050, 0059, 0081, 0094) comprising a stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094), the stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094) comprising: a first transistor(TR3_1 and/or TR3_2)(FIG. 5; ¶0100) connected between an input terminal(IN)(FIG. 5; ¶0100) configured to receive a start signal (FIG. 5: TR3_2, IN; ¶0100) and a first node(NQ)(FIG. 5; ¶0100), a gate(TR3_2’s gate terminal)(FIG. 5; ¶0100) of the first transistor(TR3_2)(FIG. 5; ¶0100) being connected to a clock terminal(terminal directly adjacent to CK)(FIG. 5; ¶0097 – TR3_2’s gate terminal is coupling connected to the terminal directly adjacent to CK) configured to receive a clock signal (FIG. 5: terminal directly adjacent to CK; ¶0097); a first output unit(TR1, TR10, TR11)(FIG. 5; ¶¶0096, 0103-0104) connected between a first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) configured to receive a first voltage(CKV HIGH to vertical wiring directly above TR1)(FIGs. 4-6; ¶¶0089, 0097-0098) and a second power input terminal(wiring providing V1 to TR1 via TR10 and/or TR11)(FIG. 5: ¶¶0090, 0103-0104) configured to receive a second voltage(V1=VSS1)(FIG. 5; ¶0090), and configured to output an output signal (FIG. 5: TR1, OUT; ¶0096) in response to a voltage level of the first node(NQ)(FIG. 5: TR1; ¶0101); and a second output unit(TR2, TR12, TR13)(FIG. 5; ¶¶0096, 0105) connected between the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and a third power input terminal(wiring providing V2 to TR2 via TR12 and/or TR13)(FIG. 5: ¶¶0090, 0103, 0105) configured to receive a third voltage(V2=VSS2)(FIG. 5; ¶0090), and configured to output a carry signal(CR)(FIG. 5: TR2; ¶0096) in response to the voltage level of the first node(NQ)(FIG. 5: TRT2; ¶0096, 0101), and wherein the second voltage(V1=VSS1)(FIG. 5; ¶0090) is lower than the first voltage(CKV HIGH to vertical wiring directly above TR1)(FIGs. 4-6; ¶¶0089, 0097-0098 – inherently CKV HIGH is > V1 for CKV high signal to travel down from CK to OUT), and the third voltage(V2=VSS2)(FIG. 5; ¶0090) is lower than the second voltage(V1=VSS1)(FIG. 5; ¶0090). As to claim 2, Park discloses the driver of claim 1, as applied above. Park further discloses wherein the first output unit(TR1, TR10, TR11)(FIG. 5; ¶¶0096, 0103-0104) comprises: a first pull-up transistor(TR1)(FIGs. 5-6: CK, CKV HIGH, OUT; ¶¶0097-0098 – TR1 pulls OUT to CKV HIGH voltage) connected between the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and a first output terminal(OUT)(FIG. 5; ¶0096), a gate(TR1’s gate terminal)(FIGs. 5-6: CK, CKV HIGH, OUT; ¶¶0097-0098) of the first pull-up transistor(TR1)(FIGs. 5-6: CK, CKV HIGH, OUT; ¶¶0097-0098) being connected to the first node(NQ)(FIG. 5; ¶0100); and a first pull-down transistor(TR10 or TR11)(FIG. 5; ¶¶0103-0104) connected between the first output terminal(OUT)(FIG. 5; ¶0096) and the second power input terminal(wiring providing V1 to TR1 via TR10 and/or TR11)(FIG. 5: ¶¶0090, 0103-0104), a gate(TR10’s gate terminal or TR11’s gate terminal)(FIG. 5; ¶¶0103-0104) of the first pull-down transistor(TR10 or TR11)(FIG. 5; ¶¶0103-0104) being connected to a second node(one of: node between TR10 and the gates of TR9_1 and TR9_2, node between the gates of TR11 and TR12, node between gates of TR10 and TR13)(FIG. 5; ¶¶0103, 0108). As to claim 5, Park discloses the driver of claim 1, as applied above. Park further discloses wherein the first transistor(TR3_1 and TR3_2)(FIG. 5; ¶0100) comprises a first sub transistor(TR3_1)(FIG. 5; ¶0100) and a second sub transistor(TR3_2)(FIG. 5; ¶0100) which are connected to each other in series (FIG. 5: TR3_1 and TR3_2; ¶0100). As to claim 7, Park discloses the driver of claim 1, as applied above. Park further discloses wherein the stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094) further comprises: a second transistor(one of: TR12 and TR13)(FIG. 5; ¶0105) connected between the second node(one of: node between TR10 and the gates of TR9_1 and TR9_2, node between the gates of TR11 and TR12, node between gates of TR10 and TR13)(FIG. 5; ¶¶0103, 0108) and the third power input terminal(wiring providing V2 to TR2 via TR12 and/or TR13)(FIG. 5: ¶¶0090, 0103, 0105), a gate of the second transistor(one of: TR12 and TR13)(FIG. 5; ¶0105) being connected to the first node(NQ)(FIG. 5: TR1; ¶0101 – the gate of one of TR12 and TR13 is coupling connected to NQ). As to claim 8, Park discloses the driver of claim 1, as applied above. Park further discloses wherein the stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094) further comprises: a reset transistor(TR14_1 and/or TR14_2)(FIG. 5; ¶0114) connected between the first node(NQ)(FIG. 5; ¶0100) and the second power input terminal(wiring providing V1 to TR1 via TR10 and/or TR11)(FIG. 5: ¶¶0090, 0103-0104 - TR14_1 and/or TR14_2 are coupling connected between NQ and the wiring providing V1 to TR1 via TR10 and/or TR11), a gate of the reset transistor(gate of TR14_1 and/or gate of TR14_2)(FIG. 5; ¶0114) being connected to a reset terminal(RE)(FIG. 5; ¶0114) configured to receive a reset signal(RST)(FIGs. 4-6: RE; ¶¶0092, 0114). As to claim 9, Park discloses the driver of claim 8, as applied above. Park further discloses wherein the reset transistor(TR14_1 and/or TR14_2)(FIG. 5; ¶0114) comprises a first sub transistor(TR14_1)(FIG. 5; ¶0114) and a second sub transistor(TR14_2)(FIG. 5; ¶0114 which are connected to each other in series (FIG. 5: TR14_1 and TR14_2; ¶0114). As to claim 11, Park discloses an electronic apparatus(100)(FIG. 1; ¶0050) comprising: a controller(SC)(FIG. 1; ¶0056) outputting a driving control signal based on signals received from an external device (FIG. 1: SC; ¶0056-0057); and a driver(110)(FIGs. 1, 4-5; ¶¶0050, 0059, 0081, 0094) comprising a stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094) outputting an output signal (FIG. 5: TR1, OUT; ¶0096) based on the driving control signal (FIG. 1: SC; ¶0056-0057), the stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094) comprising: a first transistor(TR3_1 and/or TR3_2)(FIG. 5; ¶0100) connected between an input terminal(IN)(FIG. 5; ¶0100) configured to receive a start signal (FIG. 5: TR3_2, IN; ¶0100) and a first node(NQ)(FIG. 5; ¶0100), a gate(TR3_2’s gate terminal)(FIG. 5; ¶0100) of the first transistor(TR3_2)(FIG. 5; ¶0100) being connected to a clock terminal(terminal directly adjacent to CK)(FIG. 5; ¶0097 – TR3_2’s gate terminal is coupling connected to the terminal directly adjacent to CK) configured to receive a clock signal (FIG. 5: terminal directly adjacent to CK; ¶0097); a first output unit(TR1, TR10, TR11)(FIG. 5; ¶¶0096, 0103-0104) connected between a first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) configured to receive a first voltage(CKV HIGH to vertical wiring directly above TR1)(FIGs. 4-6; ¶¶0089, 0097-0098) and a second power input terminal(wiring providing V1 to TR1 via TR10 and/or TR11)(FIG. 5: ¶¶0090, 0103-0104) configured to receive a second voltage(V1=VSS1)(FIG. 5; ¶0090), and configured to output an output signal (FIG. 5: TR1, OUT; ¶0096) in response to a voltage level of the first node(NQ)(FIG. 5: TR1; ¶0101); and a second output unit(TR2, TR12, TR13)(FIG. 5; ¶¶0096, 0105) connected between the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and a third power input terminal(wiring providing V2 to TR2 via TR12 and/or TR13)(FIG. 5: ¶¶0090, 0103, 0105) configured to receive a third voltage(V2=VSS2)(FIG. 5; ¶0090), and configured to output a carry signal(CR)(FIG. 5: TR2; ¶0096) in response to the voltage level of the first node(NQ)(FIG. 5: TRT2; ¶0096, 0101), and wherein the second voltage(V1=VSS1)(FIG. 5; ¶0090) is lower than the first voltage(CKV HIGH to vertical wiring directly above TR1)(FIGs. 4-6; ¶¶0089, 0097-0098 – inherently CKV HIGH is > V1 for CKV high signal to travel down from CK to OUT), and the third voltage(V2=VSS2)(FIG. 5; ¶0090) is lower than the second voltage(V1=VSS1)(FIG. 5; ¶0090). As to claim 12, Park discloses the electronic apparatus of claim 11, as applied above. Park further discloses wherein the first output unit(TR1, TR10, TR11)(FIG. 5; ¶¶0096, 0103-0104) comprises: a first pull-up transistor(TR1)(FIGs. 5-6: CK, CKV HIGH, OUT; ¶¶0097-0098 – TR1 pulls OUT to CKV HIGH voltage) connected between the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and a first output terminal(OUT)(FIG. 5; ¶0096), a gate(TR1’s gate terminal)(FIGs. 5-6: CK, CKV HIGH, OUT; ¶¶0097-0098) of the first pull-up transistor(TR1)(FIGs. 5-6: CK, CKV HIGH, OUT; ¶¶0097-0098) being connected to the first node(NQ)(FIG. 5; ¶0100); and a first pull-down transistor(TR10 or TR11)(FIG. 5; ¶¶0103-0104) connected between the first output terminal(OUT)(FIG. 5; ¶0096) and the second power input terminal(wiring providing V1 to TR1 via TR10 and/or TR11)(FIG. 5: ¶¶0090, 0103-0104), a gate(TR10’s gate terminal or TR11’s gate terminal)(FIG. 5; ¶¶0103-0104) of the first pull-down transistor(TR10 or TR11)(FIG. 5; ¶¶0103-0104) being connected to a second node(one of: node between TR10 and the gates of TR9_1 and TR9_2, node between the gates of TR11 and TR12, node between gates of TR10 and TR13)(FIG. 5; ¶¶0103, 0108). As to claim 15, Park discloses the electronic apparatus of claim 11, as applied above. Park further discloses wherein the first transistor(TR3_1 and TR3_2)(FIG. 5; ¶0100) comprises a first sub transistor(TR3_1)(FIG. 5; ¶0100) and a second sub transistor(TR3_2)(FIG. 5; ¶0100) which are connected to each other in series (FIG. 5: TR3_1 and TR3_2; ¶0100). As to claim 17, Park discloses the electronic apparatus of claim 11, as applied above. Park further discloses wherein the stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094) further comprises: a second transistor(one of: TR12 and TR13)(FIG. 5; ¶0105) connected between the second node(one of: node between TR10 and the gates of TR9_1 and TR9_2, node between the gates of TR11 and TR12, node between gates of TR10 and TR13)(FIG. 5; ¶¶0103, 0108) and the third power input terminal(wiring providing V2 to TR2 via TR12 and/or TR13)(FIG. 5: ¶¶0090, 0103, 0105), a gate of the second transistor(one of: TR12 and TR13)(FIG. 5; ¶0105) being connected to the first node(NQ)(FIG. 5: TR1; ¶0101 – the gate of one of TR12 and TR13 is coupling connected to NQ). As to claim 18, Park discloses the electronic apparatus of claim 11, as applied above. Park further discloses wherein the stage(SRC3)(FIGs. 4-5; ¶¶0082, 0094) further comprises: a reset transistor(TR14_1 and/or TR14_2)(FIG. 5; ¶0114) connected between the first node(NQ)(FIG. 5; ¶0100) and the second power input terminal(wiring providing V1 to TR1 via TR10 and/or TR11)(FIG. 5: ¶¶0090, 0103-0104 - TR14_1 and/or TR14_2 are coupling connected between NQ and the wiring providing V1 to TR1 via TR10 and/or TR11), a gate of the reset transistor(gate of TR14_1 and/or gate of TR14_2)(FIG. 5; ¶0114) being connected to a reset terminal(RE)(FIG. 5; ¶0114) configured to receive a reset signal(RST)(FIGs. 4-6: RE; ¶¶0092, 0114). As to claim 19, Park discloses the electronic apparatus of claim 18, as applied above. Park further discloses wherein the reset transistor(TR14_1 and/or TR14_2)(FIG. 5; ¶0114) comprises a first sub transistor(TR14_1)(FIG. 5; ¶0114) and a second sub transistor(TR14_2)(FIG. 5; ¶0114) which are connected to each other in series (FIG. 5: TR14_1 and TR14_2; ¶0114). Claim Rejections – 35 USC § 103 10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. 11. Claims 6, 10, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2017/0018245 A1 to Park et al. (“Park”) in view of U.S. Patent Pub. No. 2020/0168162 A1 to Feng et al. (“Feng”). As to claim 6, Park discloses the driver of claim 5, as applied above. Park further discloses wherein the stage further comprises: the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and an intermediate node (node between TR3_1 and TR3_2)(FIG. 5; ¶0100) of the first sub transistor(TR3_1)(FIG. 5; ¶0100) and the second sub transistor(TR3_2)(FIG. 5; ¶0100) of the first transistor(TR3_1 and TR3_2)(FIG. 5; ¶0100), the first node(NQ)(FIG. 5; ¶0100). Park does not expressly disclose a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor, a gate of the leakage control transistor being connected to the first node. PNG media_image5.png 200 400 media_image5.png Greyscale Feng discloses a leakage control transistor(M1_c)(FIG. 8; ¶0097) connected between a power input terminal(terminal directly connected to VDD)(FIG. 8; ¶0097) and an intermediate node(node between M1 and M1_b)(FIG. 8; ¶0097) of the first sub transistor(M1)(FIG. 8; ¶0097) and the second sub transistor(M1_b)(FIG. 8; ¶0097) of the first transistor(M1 and M1_b)(FIG. 8; ¶0097), a gate(M1_c’s gate terminal)(FIG. 8; ¶0097) of the leakage control transistor(M1_c)(FIG. 8; ¶0097) being connected to the first node(N1)(FIG. 8; ¶0097). Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Park with Feng to provide a driver that prevents leakage current (¶0097), which can cause the driver to operate improperly. Park and Feng teach a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor (Park: FIGs. 4-6: node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node, node between TR3_1 and TR3_2; ¶¶0089, 0097-0098, 0100; Feng: FIG. 8: M1_c, terminal directly connected to VDD, node between M1 and M1_b; ¶0097), a gate of the leakage control transistor being connected to the first node (Park: FIG. 5: NQ; ¶0100; Feng: FIG. 8: M1_c’s gate terminal, N1; ¶0097). As to claim 10, Park discloses the driver of claim 9, as applied above. Park further discloses wherein the stage further comprises: the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and an intermediate node (node between TR3_1 and TR3_2)(FIG. 5; ¶0100) of the first sub transistor(TR3_1)(FIG. 5; ¶0100) and the second sub transistor(TR3_2)(FIG. 5; ¶0100) of the first transistor(TR3_1 and TR3_2)(FIG. 5; ¶0100), the first node(NQ)(FIG. 5; ¶0100). Park does not expressly disclose a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor, a gate of the leakage control transistor being connected to the first node. Feng discloses a leakage control transistor(M1_c)(FIG. 8; ¶0097) connected between a power input terminal(terminal directly connected to VDD)(FIG. 8; ¶0097) and an intermediate node(node between M1 and M1_b)(FIG. 8; ¶0097) of the first sub transistor(M1)(FIG. 8; ¶0097) and the second sub transistor(M1_b)(FIG. 8; ¶0097) of the first transistor(M1 and M1_b)(FIG. 8; ¶0097), a gate(M1_c’s gate terminal)(FIG. 8; ¶0097) of the leakage control transistor(M1_c)(FIG. 8; ¶0097) being connected to the first node(N1)(FIG. 8; ¶0097). Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Park with Feng to provide a driver that prevents leakage current (¶0097), which can cause the driver to operate improperly. Park and Feng teach a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor (Park: FIGs. 4-6: node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node, node between TR3_1 and TR3_2; ¶¶0089, 0097-0098, 0100; Feng: FIG. 8: M1_c, terminal directly connected to VDD, node between M1 and M1_b; ¶0097), a gate of the leakage control transistor being connected to the first node (Park: FIG. 5: NQ; ¶0100; Feng: FIG. 8: M1_c’s gate terminal, N1; ¶0097). As to claim 16, Park discloses the electronic apparatus of claim 15, as applied above. Park further discloses wherein the stage further comprises: the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and an intermediate node (node between TR3_1 and TR3_2)(FIG. 5; ¶0100) of the first sub transistor(TR3_1)(FIG. 5; ¶0100) and the second sub transistor(TR3_2)(FIG. 5; ¶0100) of the first transistor(TR3_1 and TR3_2)(FIG. 5; ¶0100), the first node(NQ)(FIG. 5; ¶0100). Park does not expressly disclose a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor, a gate of the leakage control transistor being connected to the first node. Feng discloses a leakage control transistor(M1_c)(FIG. 8; ¶0097) connected between a power input terminal(terminal directly connected to VDD)(FIG. 8; ¶0097) and an intermediate node(node between M1 and M1_b)(FIG. 8; ¶0097) of the first sub transistor(M1)(FIG. 8; ¶0097) and the second sub transistor(M1_b)(FIG. 8; ¶0097) of the first transistor(M1 and M1_b)(FIG. 8; ¶0097), a gate(M1_c’s gate terminal)(FIG. 8; ¶0097) of the leakage control transistor(M1_c)(FIG. 8; ¶0097) being connected to the first node(N1)(FIG. 8; ¶0097). Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Park with Feng to provide an electronic apparatus having a driver that prevents leakage current (¶0097), which can cause the driver to operate improperly. Park and Feng teach a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor (Park: FIGs. 4-6: node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node, node between TR3_1 and TR3_2; ¶¶0089, 0097-0098, 0100; Feng: FIG. 8: M1_c, terminal directly connected to VDD, node between M1 and M1_b; ¶0097), a gate of the leakage control transistor being connected to the first node (Park: FIG. 5: NQ; ¶0100; Feng: FIG. 8: M1_c’s gate terminal, N1; ¶0097). As to claim 20, Park discloses the electronic apparatus of claim 19, as applied above. Park further discloses wherein the stage further comprises: the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and an intermediate node (node between TR3_1 and TR3_2)(FIG. 5; ¶0100) of the first sub transistor(TR3_1)(FIG. 5; ¶0100) and the second sub transistor(TR3_2)(FIG. 5; ¶0100) of the first transistor(TR3_1 and TR3_2)(FIG. 5; ¶0100), the first node(NQ)(FIG. 5; ¶0100). Park does not expressly disclose a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor, a gate of the leakage control transistor being connected to the first node. Feng discloses a leakage control transistor(M1_c)(FIG. 8; ¶0097) connected between a power input terminal(terminal directly connected to VDD)(FIG. 8; ¶0097) and an intermediate node(node between M1 and M1_b)(FIG. 8; ¶0097) of the first sub transistor(M1)(FIG. 8; ¶0097) and the second sub transistor(M1_b)(FIG. 8; ¶0097) of the first transistor(M1 and M1_b)(FIG. 8; ¶0097), a gate(M1_c’s gate terminal)(FIG. 8; ¶0097) of the leakage control transistor(M1_c)(FIG. 8; ¶0097) being connected to the first node(N1)(FIG. 8; ¶0097). Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Park with Feng to provide an electronic apparatus having a driver that prevents leakage current (¶0097), which can cause the driver to operate improperly. Park and Feng teach a leakage control transistor connected between the first power input terminal and an intermediate node of the first sub transistor and the second sub transistor of the first transistor (Park: FIGs. 4-6: node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node, node between TR3_1 and TR3_2; ¶¶0089, 0097-0098, 0100; Feng: FIG. 8: M1_c, terminal directly connected to VDD, node between M1 and M1_b; ¶0097), a gate of the leakage control transistor being connected to the first node (Park: FIG. 5: NQ; ¶0100; Feng: FIG. 8: M1_c’s gate terminal, N1; ¶0097). Allowable Subject Matter 12. Claims 3-4 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Reasons for Allowance 13. The following is examiner’s statement of reasons for allowance: the claimed invention is directed to: PNG media_image6.png 585 837 media_image6.png Greyscale Dependent claim 3 identifies the distinct features: “wherein the first output unit(FIG. 4: 230) comprises: a second pull-up transistor(FIG. 4: T21) connected between the first power input terminal(FIG. 4: V1) and a second output terminal(FIG. 4: Out[k]), a gate(FIG. 4: T21’s gate terminal) of the second pull-up transistor(FIG. 4: T21) being connected to the first node(FIG. 4: QB); and1 a second pull-down transistor connected between the second output terminal and the third power input terminal, a gate of the second pull-down transistor being connected to the second node”, with all other limitations as claimed. The closest prior art, U.S. Patent Pub. No. 2017/0018245 A1 to Park et al. (“Park”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim. As to claim 3, Park discloses the driver of claim 2, as applied above. Park further discloses wherein the second output unit(TR2, TR12, TR13)(FIG. 5; ¶¶0096, 0105) comprises: a second pull-up transistor(TR2)(FIGs. 5-6: CK, CKV HIGH, CR; ¶¶0096-0098 – TR2 pulls up CR to CKV HIGH) connected between the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and a second output terminal(CR)(FIG. 5; ¶¶0096-0097), a gate(TR2’s gate terminal)(FIGs. 5-6: CK, CKV HIGH, CR; ¶¶0096-0098) of the second pull-up transistor(TR2)(FIGs. 5-6: CK, CKV HIGH, CR; ¶¶0096-0098) being connected to the first node(NQ)(FIG. 5; ¶0100); and a second pull-down transistor(TR10 or TR11)(FIG. 5; ¶¶0103-0104) connected between the second output terminal(CR)(FIG. 5; ¶¶0096-0097) and the third power input terminal(wiring providing V2 to TR2 via TR12 and/or TR13)(FIG. 5: ¶¶0090, 0103, 0105), a gate of the second pull-down transistor(TR10’s gate terminal or TR11’s gate terminal)(FIG. 5; ¶¶0103-0104) being connected to the second node(one of: node between TR10 and the gates of TR9_1 and TR9_2, node between the gates of TR11 and TR12, node between gates of TR10 and TR13)(FIG. 5; ¶¶0103, 0108). Park does not disclose the above underlined limitations. Dependent claim 13 identifies the distinct features: “wherein the first output unit(FIG. 4: 230) comprises: a second pull-up transistor(FIG. 4: T21) connected between the first power input terminal(FIG. 4: V1) and a second output terminal(FIG. 4: Out[k]), a gate(FIG. 4: T21’s gate terminal) of the second pull-up transistor(FIG. 4: T21) being connected to the first node(FIG. 4: QB); and2 a second pull-down transistor connected between the second output terminal and the third power input terminal, a gate of the second pull-down transistor being connected to the second node”, with all other limitations as claimed. The closest prior art, U.S. Patent Pub. No. 2017/0018245 A1 to Park et al. (“Park”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim. As to claim 13, Park discloses the electronic apparatus of claim 12, as applied above. Park further discloses wherein the second output unit(TR2, TR12, TR13)(FIG. 5; ¶¶0096, 0105) comprises: a second pull-up transistor(TR2)(FIGs. 5-6: CK, CKV HIGH, CR; ¶¶0096-0098 – TR2 pulls up CR to CKV HIGH) connected between the first power input terminal(node connected to both the vertical wiring directly above TR1 providing CK voltage CKV and the horizontal wiring to the right of this node)(FIGs. 4-6; ¶¶0089, 0097-0098) and a second output terminal(CR)(FIG. 5; ¶¶0096-0097), a gate(TR2’s gate terminal)(FIGs. 5-6: CK, CKV HIGH, CR; ¶¶0096-0098) of the second pull-up transistor(TR2)(FIGs. 5-6: CK, CKV HIGH, CR; ¶¶0096-0098) being connected to the first node(NQ)(FIG. 5; ¶0100); and a second pull-down transistor(TR10 or TR11)(FIG. 5; ¶¶0103-0104) connected between the second output terminal(CR)(FIG. 5; ¶¶0096-0097) and the third power input terminal(wiring providing V2 to TR2 via TR12 and/or TR13)(FIG. 5: ¶¶0090, 0103, 0105), a gate of the second pull-down transistor(TR10’s gate terminal or TR11’s gate terminal)(FIG. 5; ¶¶0103-0104) being connected to the second node(one of: node between TR10 and the gates of TR9_1 and TR9_2, node between the gates of TR11 and TR12, node between gates of TR10 and TR13)(FIG. 5; ¶¶0103, 0108). Park does not disclose the above underlined limitations. Other Relevant Prior Art 14. Other relevant prior art includes: U.S. Patent Pub. No. 2017/0116920 A1 Kwon et al. (“Kwon”) PNG media_image7.png 200 400 media_image7.png Greyscale PNG media_image8.png 200 400 media_image8.png Greyscale PNG media_image9.png 200 400 media_image9.png Greyscale As to claim 1, Kwon discloses a driver(150)(FIG. 2; ¶0050) comprising a stage(210-n)(FIG. 3; ¶0050), the stage(210-n)(FIG. 3; ¶0050) comprising: a first transistor(M1)(FIG. 3; ¶0057) connected between an input terminal(wiring between M19 and M1)(FIG. 3; ¶0057102) configured to receive a start signal(EM[n] signal)(FIG. 3: M1; ¶0057) and a first node(N1)(FIG. 3; ¶0054), a gate(M1’s gate terminal)(FIG. 3; ¶0057) of the first transistor(M1)(FIG. 3; ¶0057) being connected to a clock terminal(terminal directly adjacent to CLK2)(FIG. 3; ¶0054) configured to receive a clock signal (FIG. 3: terminal directly adjacent to CLK2; ¶0054); a first output unit(M6)(FIG. 3; ¶0066) connected between a first power input terminal(terminal directly below VGH)(FIGs. 3; ¶0065) configured to receive a first voltage(VGH)(FIG. 3: terminal directly below VGH)(FIGs. 3; ¶0065) and a second power input terminal(M7’s upper terminal)(FIGs. 3, 4A: terminal directly above CLK1; ¶¶0051, 0081) configured to receive a second voltage(CLK1 low voltage that is raised after passing through T7 {a negative voltage drop})(FIGs. 3-4: M7’s upper terminal transmits voltage provided by terminal directly above CLK1 that is slightly raised after passing through T7 {a negative voltage drop}; ¶¶0051, 0081), and configured to output an output signal(signal output from M6)(FIG. 3; ¶0062) in response to a voltage level(low voltage at N1)(FIG. 3: M4, M6; ¶¶0066, 0068) of the first node(N1)(FIG. 3; ¶0054); and a second output unit(M7)(FIG. 3; ¶0059) connected between the first power input terminal(terminal directly below VGH)(FIGs. 3; ¶0065) and a third power input terminal(terminal directly above CLK1)(FIGs. 3, 4A; ¶¶0051, 0081) configured to receive a third voltage(CLK1 low voltage)(FIG. 3: terminal directly above CLK1; ¶¶0051, 0081), and configured to output a carry signal(CARRY[n])(FIG. 3: M7; ¶0052, 0059) in response to the voltage level(low voltage at N1)(FIG. 3: M4, M6; ¶¶0066, 0068) of the first node(N1)(FIG. 3; ¶0054), and wherein the second voltage(CLK1 low voltage that is raised after passing through T7 {a negative voltage drop})(FIGs. 3-4: M7’s upper terminal transmits voltage provided by terminal directly above CLK1 that is slightly raised after passing through T7 {a negative voltage drop}; ¶¶0051, 0081) is lower than the first voltage(VGH)(FIG. 3: terminal directly below VGH)(FIGs. 3; ¶0065), and the third voltage(CLK1 low voltage)(FIG. 3: terminal directly above CLK1; ¶¶0051, 0081) is lower than the second voltage(CLK1 low voltage that is raised after passing through T7 {a negative voltage drop})(FIGs. 3-4: M7’s upper terminal transmits voltage provided by terminal directly above CLK1 that is slightly raised after passing through T7 {a negative voltage drop}; ¶¶0051, 0081). Conclusion 15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIRK W HERMANN whose telephone number is (571) 270-3891. The examiner can normally be reached on Monday-Friday, 9am-5pm, EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KIRK W HERMANN/Primary Examiner, Art Unit 2623 1 As stated in the above drawing objection, the figures do not depict the following limitations. 2 As stated in the above drawing objection, the figures do not depict the following limitations.