DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/23/26 have been fully considered but they are not persuasive.
Regarding the 35 U.S.C. 101 rejection of the claims, Applicant argues that it is evident that neither "generating, by the LLM, a dependency map", nor "generating, based on the dependency map, a plurality of virtual batches" (as recited in the claims) amounts to a mental process that can be practically performed in a human mind because the human mind is inherently unequipped to execute the algorithmic operations of a Large Language Model, and as such, argues that the claims do not recite a mental process (Arguments, pg. 9-10).
Examiner respectfully disagrees as limitations “generating, by the LLM, a dependency map comprising: one or more index markers for each of the plurality of tokens, and a correlation marker for each of the one or more index markers” corresponds to using an LLM to perform an analysis/evaluation function, where the LLM is described in Applicant’s original specification as being a component of memory 204 of a computing device (see pg. 9, para. [0034]) i.e., merely tying an abstract idea of analysis to generic computer components. Also, limitation “generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference” corresponds to performing an analysis/evaluation function to infer/generate tokens or output (see para. [0043]-[0044] of Applicant’s original specification as well as fig. 3B). The use of an LLM to perform function corresponds to using generic elements to perform an abstract idea, where such generic computer implementation does not make the abstract idea patent eligible because a “wholly generic computer implementation is not generally the sort of ‘additional feature’ that provides any ‘practical assurance that the process is more than a drafting effort designed to monopolize the abstract idea itself.’” Alice, 573 U.S. at 223–24 (“The mere recitation of a generic computer cannot transform a patent-ineligible abstract idea into a patent-eligible invention.”); Trinity Info Media, LLC v. Covalent, Inc., 72 F.4th 1355, 1362 (Fed. Cir. 2023) (performing the abstract idea on a handheld device, web servers, and a database did not prevent the claims from being directed to an abstract idea). Therefore, Examiner maintains the rejection of the claims.
Regarding the 35 U.S.C. 103 rejection of the claims with references Roberts and Avinash, Applicant argues that a prima facie case has not been established in the rejection of the claims as secondary reference Avinash fails to disclose limitation “generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference” (Arguments, pg. 10-11).
Examiner respectfully disagrees. Roberts discloses its memory system managing a mapping, which may be referred to as a key-value (KV) cache, between one or more tokens and one or more intermediate calculation results associated with the one or more tokens, where the intermediate calculation result refers to a representation of the token, such as a key matrix and/or a value matrix (para. [0021]; para. [0065]), corresponding to preceding limitation “generating, by the LLM, a dependency map comprising: one or more index markers for each of the plurality of tokens”.
What Roberts does not explicitly disclose include limitations “generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference” and “selecting, by the LLM, one or more of the plurality of virtual batches as a final inference”.
Avinash discloses its model instances 31-1 as including cached intermediate states used to accelerate inference, where an inference session may generate significant amounts of computational results/outputs/inferences that can be re-used for future inference runs using a Key value (KV) cache (col. 48, ln 49-65) and where a model instance 31-1 is configured with an input structure that has a batch dimension/ rows of an array, and where inference on the batch occurs in parallel, such that outputs can contain the batch dimension (col. 49, ln 18-33) i.e., output/batch inferences are based on cached intermediates states/KV cache/mapping and as such limitation “generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference”. Avinash further discloses obtaining a final output based on the outputs 3 (col. 49, ln 18-41), i.e., selecting one or more outputs, and as such, limitation “selecting, by the LLM, one or more of the plurality of virtual batches as a final inference”. When combined with the teachings of Roberts with the suggestion/motivation of providing outputs to tune a model for complex query processing (Avinash, col. 11, ln 44-58), the combination of Roberts and Avinash discloses the limitations of claim 1 and the other independent claims, and as such, Examiner maintains that a prima facie case of obviousness is/was established in the rejection of the claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to the abstract idea of textual/token data analysis without significantly more. The independent claims 1, 9 and 15 recite the steps of generating, with a large language model (LLM), a plurality of tokens (i.e., a data analysis/evaluation step), generating, by the LLM, a dependency map comprising: one or more index markers for each of the plurality of tokens and a correlation marker for each of the one or more index markers (i.e., a data analysis/evaluation step), generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference (i.e., a data analysis/evaluation step) and selecting, by the LLM, one or more of the plurality of virtual batches as a final inference (i.e., a judgement step), corresponding to step achievable by a human in mentally/manually generating textual data, a mapping and batches of data, while selecting from the batches of data, and as such correspond to the mental processes category of abstract ideas. This judicial exception is not integrated into a practical application because the claims are directed to an abstract idea with additional generic computer elements, where the generically recited computer elements (device, processor, memory, LLM, medium) do not add a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer; The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because steps “generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference and selecting, by the LLM, one or more of the plurality of virtual batches as a final inference.” correspond to well-understood, routine, conventional computer functions of “collecting information, analyzing it, and displaying certain results of the collection and analysis” as recognized by the court decisions listed in MPEP § 2106.05 and as provided by cited references including Roberts and Avinash (PTO 892 form).
The dependent claims also recite mental processes and do not add significantly more than the abstract idea and are as such similarly rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1, 5, 6, 8, 9, 13-15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts 2026/0029952 A1 (“Roberts”) in view of Avinash US 12,524,459 B1 (“Avinash”)
Per claim 1, Roberts discloses a method comprising:
generating, with a large language model (LLM), a plurality of tokens (a computing system may provide a sequence of input tokens (e.g., an ordered list of input tokens), which may be referred to as a prompt, to a large language model to generate a sequence of output tokens …, para. [0013]);
generating, by the LLM, a dependency map comprising: one or more index markers for each of the plurality of tokens (the memory system may manage a mapping, which may be referred to as a key-value (KV) cache, between one or more tokens and one or more intermediate calculation results associated with the one or more tokens. As described herein, an intermediate calculation result refers to a representation of the token, such as a key matrix and/or a value matrix.… The memory system may add new entries in the mapping table to include an association between the newly generated token and the associated key and value matrices…., para. [0021]; The memory system 220 may update the mapping to include an association between each token (e.g., the one or more input tokens) and their intermediate computation state matrices, which may reduce the amount of computation used to generate the next predicted token …, para. [0065], association between tokens and key and value matrices as map, key and value matrices as including more than one index); and
a correlation marker for each of the one or more index markers (para. [0021]; The memory system 220 may update the mapping to include an association between each token (e.g., the one or more input tokens) and their intermediate computation state matrices, which may reduce the amount of computation used to generate the next predicted token …, para. [0065], key and corresponding value matrices as including more than one index);
Roberts does not explicitly disclose generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference or selecting, by the LLM, one or more of the plurality of virtual batches as a final inference
However, these features are taught by Avinash:
generating, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference (col. 42, ln 21-32; Model instance(s) 31-1 can include cached intermediate states of active or inactive model(s) used to accelerate inference of those models. For instance, an inference session with a particular model may generate significant amounts of computational results that can be re-used for future inference runs (e.g., using a KV cache for transformer-based models)…., col. 48, ln 49-65; Model host 31 can perform inference over batches of input requests 33 in parallel. For instance, a model instance 31-1 can be configured with an input structure that has a batch dimension. Separate input(s) 2 can be distributed across the batch dimension (e.g., rows of an array). The separate input(s) 2 can include completely different contexts. The separate input(s) 2 can be multiple inference steps of the same task. The separate input(s) 2 can be staggered in an input structure, such that any given inference cycle can be operating on different portions of the respective input(s) 2. In this manner, for instance, model host 31 can perform inference on the batch in parallel, such that output(s) 3 can also contain the batch dimension and return the inference results for the batched input(s) 2 in parallel …, col. 49, ln 18-33, output/batch inferences based on cached intermediates states/KV cache/mapping as implying limitation); and
selecting, by the LLM, one or more of the plurality of virtual batches as a final inference (fig. 18; col. 25, ln 43-47; col. 47, ln 50-67; col. 48, ln 49-65; Model host 31 can perform inference over batches of input requests 33 in parallel. For instance, a model instance 31-1 can be configured with an input structure that has a batch dimension…. In this manner, for instance, model host 31 can perform inference on the batch in parallel, such that output(s) 3 can also contain the batch dimension and return the inference results for the batched input(s) 2 in parallel … Output payload 34 can include or be based on output(s) 3 from machine-learned model(s) 1. Model host 31 can process output(s) 3 to obtain output payload 34. This can include chaining multiple rounds of inference (e.g., iteratively, recursively, across the same model(s) or different model(s)) to arrive at a final output for a task …, col. 49, ln 18-41, final output containing inferred batch dimension as implying limitation)
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the teachings of Avinash with the method of Roberts in arriving at the missing features of Roberts, because such combination would have resulted in providing outputs to tune a model for complex query processing (Avinash, col. 11, ln 44-58).
Per claim 5, Roberts in view of Avinash discloses the method of claim 1,
Avinash discloses wherein the plurality of virtual batches include a single physical batch of a batch length (fig. 13; fig. 15; fig. 18; col. 49, ln 18-41).
Per claim 6, Roberts in view of Avinash discloses the method of claim 5,
Avinash discloses wherein the batch length is based on a size of a cache memory (col. 48, ln 49-65; col. 49, ln 18-33).
Per claim 8, Roberts in view of Avinash discloses the method of claim 1,
Avinash discloses wherein: two or more of the plurality of virtual batches share a first input (Model host 31 can perform inference over batches of input requests 33 in parallel. For instance, a model instance 31-1 can be configured with an input structure that has a batch dimension. Separate input(s) 2 can be distributed across the batch dimension (e.g., rows of an array). The separate input(s) 2 can include completely different contexts. The separate input(s) 2 can be multiple inference steps of the same task…., col. 49, ln 18-33);
one or more other virtual batches of the plurality of virtual batches comprises a second input (Separate input(s) 2 can be distributed across the batch dimension (e.g., rows of an array). The separate input(s) 2 can include completely different contexts. The separate input(s) 2 can be multiple inference steps of the same task…., col. 49, ln 18-33);
the one or more other virtual batches is different than any of the two or more of the plurality of virtual batches (Separate input(s) 2 can be distributed across the batch dimension (e.g., rows of an array). The separate input(s) 2 can include completely different contexts. The separate input(s) 2 can be multiple inference steps of the same task…., col. 49, ln 18-33); and
the first input is different than the second input (Separate input(s) 2 can be distributed across the batch dimension (e.g., rows of an array). The separate input(s) 2 can include completely different contexts. The separate input(s) 2 can be multiple inference steps of the same task…., col. 49, ln 18-33).
Per claim 9, Roberts discloses electronic device comprising:
one or more processors (para. [0079]); and
a memory storing instructions, which, when accessed by the one or more processors (para. [0079]), cause the one or more processors to:
generate, with a large language model (LLM), a plurality of tokens (a computing system may provide a sequence of input tokens (e.g., an ordered list of input tokens), which may be referred to as a prompt, to a large language model to generate a sequence of output tokens …, para. [0013]);
generate, by the LLM, a dependency map comprising: one or more index markers for each of the plurality of tokens (the memory system may manage a mapping, which may be referred to as a key-value (KV) cache, between one or more tokens and one or more intermediate calculation results associated with the one or more tokens. As described herein, an intermediate calculation result refers to a representation of the token, such as a key matrix and/or a value matrix.… The memory system may add new entries in the mapping table to include an association between the newly generated token and the associated key and value matrices…., para. [0021]; The memory system 220 may update the mapping to include an association between each token (e.g., the one or more input tokens) and their intermediate computation state matrices, which may reduce the amount of computation used to generate the next predicted token …, para. [0065], association between tokens and key and value matrices as map, key and value matrices as including more than one index); and
a correlation marker for each of the one or more index markers (para. [0021]; The memory system 220 may update the mapping to include an association between each token (e.g., the one or more input tokens) and their intermediate computation state matrices, which may reduce the amount of computation used to generate the next predicted token …, para. [0065], key and corresponding value matrices as including more than one index);
Roberts does not explicitly disclose to: generate, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference or select, by the LLM, one or more of the plurality of virtual batches as a final inference
However, these features are taught by Avinash:
generate, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference (col. 42, ln 21-32; Model instance(s) 31-1 can include cached intermediate states of active or inactive model(s) used to accelerate inference of those models. For instance, an inference session with a particular model may generate significant amounts of computational results that can be re-used for future inference runs (e.g., using a KV cache for transformer-based models)…., col. 48, ln 49-65; Model host 31 can perform inference over batches of input requests 33 in parallel. For instance, a model instance 31-1 can be configured with an input structure that has a batch dimension. Separate input(s) 2 can be distributed across the batch dimension (e.g., rows of an array). The separate input(s) 2 can include completely different contexts. The separate input(s) 2 can be multiple inference steps of the same task. The separate input(s) 2 can be staggered in an input structure, such that any given inference cycle can be operating on different portions of the respective input(s) 2. In this manner, for instance, model host 31 can perform inference on the batch in parallel, such that output(s) 3 can also contain the batch dimension and return the inference results for the batched input(s) 2 in parallel …, col. 49, ln 18-33, output/batch inferences based on cached intermediates states/KV cache/mapping as implying limitation); and
select, by the LLM, one or more of the plurality of virtual batches as a final inference (fig. 18; col. 25, ln 43-47; col. 47, ln 50-67; col. 48, ln 49-65; Model host 31 can perform inference over batches of input requests 33 in parallel. For instance, a model instance 31-1 can be configured with an input structure that has a batch dimension…. In this manner, for instance, model host 31 can perform inference on the batch in parallel, such that output(s) 3 can also contain the batch dimension and return the inference results for the batched input(s) 2 in parallel … Output payload 34 can include or be based on output(s) 3 from machine-learned model(s) 1. Model host 31 can process output(s) 3 to obtain output payload 34. This can include chaining multiple rounds of inference (e.g., iteratively, recursively, across the same model(s) or different model(s)) to arrive at a final output for a task …, col. 49, ln 18-41, final output containing inferred batch dimension as implying limitation)
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the teachings of Avinash with the device of Roberts in arriving at the missing features of Roberts, because such combination would have resulted in providing outputs to tune a model for complex query processing (Avinash, col. 11, ln 44-58).
Per claim 13, Roberts in view of Avinash discloses the electronic device of claim 9,
Avinash discloses wherein the plurality of virtual batches include a single physical batch of a batch length (fig. 13; fig. 15; fig. 18; col. 49, ln 18-41).
Per claim 14, Roberts in view of Avinash discloses the electronic device of claim 13,
Avinash discloses a cache memory, wherein the batch length is based on a size of the cache memory (col. 48, ln 49-65; col. 49, ln 18-33)
Per claim 15, Roberts discloses a non-transitory, computer-readable medium storing instructions, which, when accessed by one or more processors, cause the one or more processors to:
generate, with a large language model (LLM), a plurality of tokens (a computing system may provide a sequence of input tokens (e.g., an ordered list of input tokens), which may be referred to as a prompt, to a large language model to generate a sequence of output tokens …, para. [0013]);
generate, by the LLM, a dependency map comprising: one or more index markers for each of the plurality of tokens (the memory system may manage a mapping, which may be referred to as a key-value (KV) cache, between one or more tokens and one or more intermediate calculation results associated with the one or more tokens. As described herein, an intermediate calculation result refers to a representation of the token, such as a key matrix and/or a value matrix.… The memory system may add new entries in the mapping table to include an association between the newly generated token and the associated key and value matrices…., para. [0021]; The memory system 220 may update the mapping to include an association between each token (e.g., the one or more input tokens) and their intermediate computation state matrices, which may reduce the amount of computation used to generate the next predicted token …, para. [0065], association between tokens and key and value matrices as map, key and value matrices as including more than one index); and
a correlation marker for each of the one or more index markers (para. [0021]; The memory system 220 may update the mapping to include an association between each token (e.g., the one or more input tokens) and their intermediate computation state matrices, which may reduce the amount of computation used to generate the next predicted token …, para. [0065], key and corresponding value matrices as including more than one index);
Roberts does not explicitly disclose to: generate, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference or select, by the LLM, one or more of the plurality of virtual batches as a final inference
However, these features are taught by Avinash:
generate, based on the dependency map, a plurality of virtual batches, each of the plurality of virtual batches comprising a discrete inference (col. 42, ln 21-32; Model instance(s) 31-1 can include cached intermediate states of active or inactive model(s) used to accelerate inference of those models. For instance, an inference session with a particular model may generate significant amounts of computational results that can be re-used for future inference runs (e.g., using a KV cache for transformer-based models)…., col. 48, ln 49-65; Model host 31 can perform inference over batches of input requests 33 in parallel. For instance, a model instance 31-1 can be configured with an input structure that has a batch dimension. Separate input(s) 2 can be distributed across the batch dimension (e.g., rows of an array). The separate input(s) 2 can include completely different contexts. The separate input(s) 2 can be multiple inference steps of the same task. The separate input(s) 2 can be staggered in an input structure, such that any given inference cycle can be operating on different portions of the respective input(s) 2. In this manner, for instance, model host 31 can perform inference on the batch in parallel, such that output(s) 3 can also contain the batch dimension and return the inference results for the batched input(s) 2 in parallel …, col. 49, ln 18-33, output/batch inferences based on cached intermediates states/KV cache/mapping as implying limitation); and
select, by the LLM, one or more of the plurality of virtual batches as a final inference (fig. 18; col. 25, ln 43-47; col. 47, ln 50-67; col. 48, ln 49-65; Model host 31 can perform inference over batches of input requests 33 in parallel. For instance, a model instance 31-1 can be configured with an input structure that has a batch dimension…. In this manner, for instance, model host 31 can perform inference on the batch in parallel, such that output(s) 3 can also contain the batch dimension and return the inference results for the batched input(s) 2 in parallel … Output payload 34 can include or be based on output(s) 3 from machine-learned model(s) 1. Model host 31 can process output(s) 3 to obtain output payload 34. This can include chaining multiple rounds of inference (e.g., iteratively, recursively, across the same model(s) or different model(s)) to arrive at a final output for a task …, col. 49, ln 18-41, final output containing inferred batch dimension as implying limitation)
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the teachings of Avinash with the medium of Roberts in arriving at the missing features of Roberts, because such combination would have resulted in providing outputs to tune a model for complex query processing (Avinash, col. 11, ln 44-58).
Per claim 19, Roberts in view of Avinash discloses the non-transitory, computer-readable medium of claim 15,
Avinash discloses wherein the plurality of virtual batches include a single physical batch of a batch length (fig. 13; fig. 15; fig. 18; col. 49, ln 18-41).
Per claim 20, Roberts in view of Avinash discloses the non-transitory, computer-readable medium of claim 19,
Avinash discloses wherein the batch length is based on a size of a cache memory (col. 48, ln 49-65; col. 49, ln 18-33).
2. Claims 2-4, 10-12 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Avinash as applied to claims 1, 9 and 15 above, and further in view of Miao et al “SpecInfer: Accelerating Large Language Model Serving with Tree-based Speculative Inference and Verification” (“Miao” - IDS)
Per claim 2, Roberts in view of Avinash discloses the method of claim 1,
Roberts discloses wherein: the dependency map is a dependency array configured as ordinal pairs of the index markers and the correlation markers (para. [0021]; para. [0065]); and
Roberts in view of Avinash does not explicitly disclose for each ordinal pair, the correlation marker is less than the corresponding index marker
However, this feature is suggested by Miao (where 𝑄 , 𝐾𝑖 , and 𝑉𝑖 denote the query, key, and value tensors …j < k … Intuitively, when computing the attention output of the 𝑗-th token in the sequence, all subsequent tokens should have an attention score of −∞ to indicate that the subsequent tokens will not affect the attention output of the 𝑗-th token …, sec. 4.1).
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the teachings of Miao with the method of Roberts in arriving at the missing features of Roberts, because such combination would have resulted in preserving causality when generating tokens (Miao, sec. 4.1)
Per claim 3, Roberts in view of Avinash and Miao discloses the method of claim 2,
Miao discloses wherein the index markers are determined by positions of the correlation markers in the dependency array (when computing the attention output of the 𝑗-th token in the sequence …, sec. 4.1).
Per claim 4, Roberts in view of Avinash discloses the method of claim 1,
Roberts in view of Avinash does not explicitly disclose wherein: one or more of the plurality of virtual batches comprise one or more masked markers at one or more positions in the one or more of the plurality of virtual batches or the one or more masked markers are configured to indicate the one or more positions in the one or more of the plurality of virtual batches are not correlated with any of the plurality of tokens
However, these features are taught by Miao;
wherein: one or more of the plurality of virtual batches comprise one or more masked markers at one or more positions in the one or more of the plurality of virtual batches (To preserve causality when generating tokens (i.e., a token in the sequence should not affect the hidden states of any preceding tokens), the following causal mask function is applied …, sec. 4.1); and
the one or more masked markers are configured to indicate the one or more positions in the one or more of the plurality of virtual batches are not correlated with any of the plurality of tokens (Intuitively, when computing the attention output of the 𝑗-th token in the sequence, all subsequent tokens should have an attention score of −∞ to indicate that the subsequent tokens will not affect the attention output of the 𝑗-th token …, sec. 4.1)
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the teachings of Miao with the method of Roberts in arriving at the missing features of Roberts, because such combination would have resulted in preserving causality when generating tokens (Miao, sec. 4.1).
Per claim 10, Roberts in view of Avinash discloses the electronic device of claim 9,
Device claim 10 and method claim 2 are related as device and the method of using same, with each claimed element's function corresponding to the claimed method step. Accordingly claim 10 is similarly rejected under the same rationale as applied above with respect to claim 2.
Per claim 11, Roberts in view of Avinash and Miao discloses the electronic device of claim 10,
Device claim 11 and method claim 3 are related as device and the method of using same, with each claimed element's function corresponding to the claimed method step. Accordingly claim 11 is similarly rejected under the same rationale as applied above with respect to claim 3.
Per claim 12, Roberts in view of Avinash discloses the electronic device of claim 9,
Device claim 12 and method claim 4 are related as device and the method of using same, with each claimed element's function corresponding to the claimed method step. Accordingly claim 12 is similarly rejected under the same rationale as applied above with respect to claim 4.
Per claim 16, Roberts in view of Avinash discloses the non-transitory, computer-readable medium of claim 15,
Medium claim 16 and method claim 2 are related as medium and the method of using same, with each claimed element's function corresponding to the claimed method step. Accordingly claim 16 is similarly rejected under the same rationale as applied above with respect to claim 2.
Per claim 17, Roberts in view of Avinash and Miao discloses the non-transitory, computer-readable medium of claim 16,
Medium claim 17 and method claim 3 are related as medium and the method of using same, with each claimed element's function corresponding to the claimed method step. Accordingly claim 17 is similarly rejected under the same rationale as applied above with respect to claim 3.
Per claim 18, Roberts in view of Avinash discloses the non-transitory, computer-readable medium of claim 15,
Medium claim 18 and method claim 4 are related as medium and the method of using same, with each claimed element's function corresponding to the claimed method step. Accordingly claim 18 is similarly rejected under the same rationale as applied above with respect to claim 4.
3. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Avinash as applied to claim 1, and further in view of Zhang et al US 2025/0383914 A1 (“Zhang”)
Per claim 7, Roberts in view of Avinash discloses the method of claim 1,
Roberts in view of Avinash does not explicitly disclose comparing, by the LLM, the plurality of virtual batches, wherein the selecting of the one or more of the plurality of virtual batches as the final inference is based at least in part on the comparison
However, this feature is taught by Zhang (Abstract; para. [0008]; para. [0025]; para. [0068])
It would have been obvious to one of ordinary skill in the art before the effective filing of the invention to combine the teachings of Zhang with the method of Roberts in arriving at the missing features of Roberts, because such combination would have resulted in reducing idle time in a computing process while ensuring efficient utilization and fair management of resources (Zhang, para. [0008]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892 form.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OLUJIMI A ADESANYA whose telephone number is (571)270-3307. The examiner can normally be reached Monday-Friday 8:30-5:00pm.
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/OLUJIMI A ADESANYA/Primary Examiner, Art Unit 2658
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