DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 20230072492), in the view of Komazawa (US 20220230585), and further in the view of Qing (US 20240249676).
Regarding claim 1: Ji teaches a display apparatus (Fig. 1 #100), comprising: a display panel; and a plurality of subpixels disposed in a display area of the display panel (Fig. 1 and paragraph [0042-0044] teach a display panel 100; and a plurality of subpixels P disposed in a display area DA), each of the plurality of subpixels including a light emitting element and a pixel circuit configured to independently drive the light emitting element (Fig. 4 and paragraph [0073-0086] teach each of the subpixels P including a light emitting element ED and a pixel circuit to drive the light emitting element ED), wherein the pixel circuit includes: a driving transistor arranged to drive the light emitting element; a first thin film transistor arranged to connect a first node and a second node of the driving transistor in response to a first scan signal; and a third thin film transistor arranged to connect a high-potential power line and the first node of the driving transistor in response to a signal (Fig. 4 and paragraph [0073-0086] teach a driving transistor DT to drive the light emitting element ED; a first thin film transistor ST3; and a third thin film transistor ET2 and all connected in a similar manner as claimed).
Ji does not explicitly disclose the third thin film transistor connected to an (N+1) scan signal of an (N+1)th row line, N being a positive integer, and wherein an Nth row line and the (N+1)th row line share the (N+1) scan signal.
However, Komazawa teaches the third thin film transistor connected to an (N+1) scan signal of an (N+1)th row line, N being a positive integer (Figs. 1-2 and paragraph [0037-0042] teach the third thin film transistor 204 connected to a second scan line or N+1 scan line 107). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify Ji’s invention by including above teachings of Komazawa, because utilizing scan signal for emission control transistor eliminates the need of separate emission driver, hence simplifying the driving circuit design while achieving similar results. The rationale would have been to use a known method or technique to achieve predictable results.
Furthermore, Qing teaches wherein an Nth row line and the (N+1)th row line share the (N+1) scan signal (Fig. 1 and paragraph [0062-0077] teach Nth row line P1 and the (N+1)th row line P2 share the (N+1) or O2 scan signal). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify Ji’s invention by including above teachings of Qing, because sharing scan signal between two rows of pixels is very well-known and widely used in the art to achieve optimal driving the light emitting elements for high display quality, as shown by Qing. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 2: Ji teaches wherein the pixel circuit further includes: a second thin film transistor arranged to connect a third node of the driving transistor and a data line in response to a second scan signal; a fourth thin film transistor arranged to connect the third node of the driving transistor and the light emitting element in response to a light emission control signal; a fifth thin film transistor arranged to connect an initialization voltage line and a fourth node of the light emitting element in response to the light emission control signal; and a storage capacitor connected between the second node of the driving transistor and the fourth node of the light emitting element (Fig. 4 and paragraph [0073-0086] teach a second thin film transistor ST2; a fourth thin film transistor ET1; a fifth thin film transistor ST1; and a storage capacitor Cst; and all elements are connected in a similar manner as claimed).
Regarding claim 11: Ji teaches further comprising a gate driving circuit disposed in a bezel area of the display panel, the gate driving circuit including: a first scan driving circuit configured to supply the first scan signal and the (N+1) scan signal; a second scan driving circuit configured to supply the second scan signal; and a light emission control driving circuit configured to supply the light emission control signal (Fig. 1 and paragraph [0045-0051] teach a gate driving circuit 200 disposed in a bezel area BZ of the display panel; including a first scan driving circuit 210; a second scan driving circuit 220; and a light emission control driving circuit 230).
Regarding claim 12: Ji teaches wherein: the first scan driving circuit is disposed in a first bezel area adjacent to one side of the display area; the second scan driving circuit is disposed in a second bezel area adjacent to another side of the display area that is opposite the one side of the display area; and the light emission control driving circuit is disposed in any one of the first and second bezel areas (Fig. 1 and paragraph [0045-0051] teach a first and second bezel areas BZ1/BZ2 on sides of the display area DA; and each of the scan drivers and/or emission drivers can be located in the either of the bezel areas BZ1 or BZ2).
Claims 3-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 20230072492), in the view of Komazawa (US 20220230585), in the view of Qing (US 20240249676), and further in the view of Tu (US 20250356807).
Regarding claims 3-5: Ji teaches wherein the driving transistor and the first to fifth thin film transistors include at least one of an oxide transistor (Fig. 4 and paragraph [0056-0057, 0118]).
Combination of Ji, Komazawa, and Qing do not explicitly disclose a polysilicon transistor; wherein: the first thin film transistor and the driving transistor are N-type oxide transistors; and the third thin film transistor is a P-type polysilicon transistor; and wherein: the fourth thin film transistor is a P-type polysilicon transistor; and the fifth thin film transistor is an N-type oxide transistor.
However, Tu teaches a polysilicon transistor; wherein: the first thin film transistor and the driving transistor are N-type oxide transistors; and the third thin film transistor is a P-type polysilicon transistor; and wherein: the fourth thin film transistor is a P-type polysilicon transistor; and the fifth thin film transistor is an N-type oxide transistor (Figs. 2, 4 and paragraph [0027, 0033, 0041, 0056]). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Ji, Komazawa, and Qing by including above teachings of Tu, because utilizing polysilicon transistors and N-type or P-type transistors for various transistors within a pixel circuit is very well-known and widely used in the art to achieve optimal driving results as desired, and there are only limited types of transistors that can be utilized for pixel circuits and would have been merely a matter to design choice to try the limited options and select the desired type to achieve desired results, as shown by Tu. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 13: Combination of Ji, Komazawa, Qing, and Tu teach wherein during an anode reset frame period: the first and second scan driving circuits are deactivated; and only the light emission control driving circuit is activated to supply the light emission control signal (Tu in Figs. 6, 11-12 and paragraph [0056-0062] teach during an anode reset period the first SC1 and second SC2 scan driving circuits are deactivated and only the light emission control driving circuit EM is activated to supply the light emission control signal). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify combination of Ji, Komazawa, and Qing by including above teachings of Tu, because an anode reset period is commonly used in the pixel driving in order to remove residual accumulated charge from the light emitting diode to achieve optimal display quality, as shown by Tu. The rationale would have been to use a known method or technique to achieve predictable results.
Allowable Subject Matter
Claims 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6: None of the cited references either alone or in combination teach “wherein: in each frame period, the pixel circuit includes an initialization period, a sampling period, a light emission preparation period, and a light emission period; the first scan signal has a gate-high voltage during a first period including the initialization period and the sampling period, and has a gate-low voltage during remaining periods in each frame period other than the first period; the second scan signal has the gate-low voltage during a second period including the sampling period, and partially overlaps the first period, and has the gate-high voltage during remaining periods in each frame period other than the second period; and the light emission control signal has the gate-high voltage during a third period including initialization period, sampling period, and light emission preparation period of a plurality of row lines, and has the gate-low voltage during remaining periods in each frame period other than the third period”.
Conclusion
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/AMIT CHATLY/Primary Examiner, Art Unit 2624
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